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JPS60183439U - integrated circuit - Google Patents

integrated circuit

Info

Publication number
JPS60183439U
JPS60183439U JP1984071174U JP7117484U JPS60183439U JP S60183439 U JPS60183439 U JP S60183439U JP 1984071174 U JP1984071174 U JP 1984071174U JP 7117484 U JP7117484 U JP 7117484U JP S60183439 U JPS60183439 U JP S60183439U
Authority
JP
Japan
Prior art keywords
integrated circuit
abstract
corners
passivation film
recorded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1984071174U
Other languages
Japanese (ja)
Inventor
毅 安東
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1984071174U priority Critical patent/JPS60183439U/en
Publication of JPS60183439U publication Critical patent/JPS60183439U/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は、従来の集積回路に用いられるポンディングパ
ッド部の平面図である。第２図および第３図は本考案の
一実施例および他の実施例の平面図である。 １．１１．２１・・・ポンディングパッド部、２゜１２
．２２・・・パッシベーション膜、３，１３，２３・・
・電極配線。FIG. 1 is a plan view of a bonding pad section used in a conventional integrated circuit. 2 and 3 are plan views of one embodiment and another embodiment of the present invention. 1.11.21...Ponding pad part, 2゜12
．． 22... Passivation film, 3, 13, 23...
・Electrode wiring.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 電極パターンの端部を角部を丸めたもしくは角部のない
形状にパッシベーション膜から露出せしめた構造を有す
ることを特徴とする集積回路。An integrated circuit characterized by having a structure in which the ends of an electrode pattern are exposed from a passivation film with rounded corners or no corners.
JP1984071174U 1984-05-16 1984-05-16 integrated circuit Pending JPS60183439U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1984071174U JPS60183439U (en) 1984-05-16 1984-05-16 integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984071174U JPS60183439U (en) 1984-05-16 1984-05-16 integrated circuit

Publications (1)

Publication Number Publication Date
JPS60183439U true JPS60183439U (en) 1985-12-05

Family

ID=30608426

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984071174U Pending JPS60183439U (en) 1984-05-16 1984-05-16 integrated circuit

Country Status (1)

Country Link
JP (1) JPS60183439U (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997008773A1 (en) * 1995-08-25 1997-03-06 Matsushita Electric Industrial Co., Ltd. Dielectric filter, production method therefor and package member obtained by packaging the filter
JP2001351920A (en) * 2000-06-07 2001-12-21 Mitsubishi Electric Corp Semiconductor device and its manufacturing method
JP2007258596A (en) * 2006-03-24 2007-10-04 Fujifilm Corp Semiconductor device manufacturing method and semiconductor device
JP2011238951A (en) * 2011-07-08 2011-11-24 Renesas Electronics Corp Semiconductor device and method of manufacturing same
JP2016046454A (en) * 2014-08-26 2016-04-04 太陽誘電株式会社 Thin film electronic components

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997008773A1 (en) * 1995-08-25 1997-03-06 Matsushita Electric Industrial Co., Ltd. Dielectric filter, production method therefor and package member obtained by packaging the filter
JPH0964612A (en) * 1995-08-25 1997-03-07 Matsushita Electric Ind Co Ltd Dielectric filter, method of manufacturing the same, and mounting body mounting the same
JP2001351920A (en) * 2000-06-07 2001-12-21 Mitsubishi Electric Corp Semiconductor device and its manufacturing method
JP2007258596A (en) * 2006-03-24 2007-10-04 Fujifilm Corp Semiconductor device manufacturing method and semiconductor device
JP2011238951A (en) * 2011-07-08 2011-11-24 Renesas Electronics Corp Semiconductor device and method of manufacturing same
JP2016046454A (en) * 2014-08-26 2016-04-04 太陽誘電株式会社 Thin film electronic components

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