JPS61297191A - Integrated circuit card - Google Patents
Integrated circuit cardInfo
- Publication number
- JPS61297191A JPS61297191A JP60138907A JP13890785A JPS61297191A JP S61297191 A JPS61297191 A JP S61297191A JP 60138907 A JP60138907 A JP 60138907A JP 13890785 A JP13890785 A JP 13890785A JP S61297191 A JPS61297191 A JP S61297191A
- Authority
- JP
- Japan
- Prior art keywords
- card
- chips
- chip
- vinyl chloride
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Credit Cards Or The Like (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明はカード状基体にＩＣチップを組込んだＩＣカ
ードに関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an IC card in which an IC chip is incorporated into a card-like base.
ＩＣカード状基体にＣＰＵ、メモリ等のＩＣチップを組
込んで従来からの磁気カードを発展させたような機能を
持たせたものであり、キャッジ−カードその他への応用
が考えられている。It has a function similar to that of a conventional magnetic card by incorporating an IC chip such as a CPU and memory into an IC card-like base, and is considered to be applied to cash cards and other applications.
このようなＩＣカードはＩＣチップを内蔵しない通常の
磁気カード等との互換性維持、例えばエンボスの形成や
磁気テープの貼着を可能とする等の要求から、カード状
基体の少くなくとも表面部材は塩化ビニル樹脂のような
有機物のシートであることか望まれる。Such IC cards are required to maintain compatibility with ordinary magnetic cards that do not have built-in IC chips, for example, to be able to form embossing and attach magnetic tape, so at least the surface material of the card-like base is required. Preferably, the material is a sheet of organic material such as vinyl chloride resin.
従来の１０カードは第４図（ａ）（ｔ））にその−例を
示すように、１０チツプ１を搭載し、配線パターン２と
ワイヤ３を介してチップ１に接続された入出力端子４が
形成された薄厚のガラスエポキシ基板からカる配線基板
５を塩化ビニール樹脂からなる基体６の開口部７にはめ
込み開口部７の基体６の下部にエポキシ樹脂８を充填し
て基体６を固定するという構造となっている。The conventional 10 card is equipped with a 10 chip 1 and has an input/output terminal 4 connected to the chip 1 via a wiring pattern 2 and a wire 3, as shown in FIGS. A wiring board 5 made from a thin glass epoxy board on which is formed is fitted into an opening 7 of a base 6 made of vinyl chloride resin, and the lower part of the base 6 in the opening 7 is filled with epoxy resin 8 to fix the base 6. The structure is as follows.
しかしながら、上記構造において１０は厚さが０．３〜
の厚さのものを使用した場合、カードに曲げの力が加わ
った時には１０のチップけ８ｉの単結晶からなるために
変形に耐えられずに破壊するという問題があ−た。However, in the above structure, 10 has a thickness of 0.3 to
When using a card having a thickness of 100 lbs., there was a problem that when a bending force was applied to the card, the card could not withstand deformation and would break because it was made of a single crystal of 8i with 10 chips.
この発明は、曲げ応力に対してＩＣの破壊を減少するこ
とを目的とする。さらに、ＩＣチップの高密度実装をす
ることの目的もある。ざらに、別の目的はカードの表面
からの鋭い傷に対１７て■０の機能上の破壊を減少させ
ることにある。The purpose of this invention is to reduce IC failure due to bending stress. Furthermore, there is also the purpose of high-density packaging of IC chips. Another purpose is to reduce the functional damage caused by sharp scratches from the surface of the card.
この発明に係るＩＣカードの構成につき第１図を用いて
説明する。The structure of the IC card according to the present invention will be explained using FIG. 1.
熱可塑性樹脂からなるカード基材１０の中に、ＣＰＵの
機能を有する１０チツプ１１と、メモリ機能を有する１
０チツプ１２を、チップ裏面をダイボンド接着剤１６を
介して重ね帖り合わせたものが埋設されており、チップ
間の接続は導電層による回路パターン１３．１４を介し
て行なわれる。In the card base material 10 made of thermoplastic resin, there are 10 chips 11 having a CPU function and 1 chip having a memory function.
0 chips 12 are buried with the back surfaces of the chips stacked together with a die-bonding adhesive 16 interposed therebetween, and connections between the chips are made through circuit patterns 13 and 14 made of conductive layers.
１５はカードのＩｌｏのための端子である。15 is a terminal for Ilo of the card.
また、１０チツプの素子面同士を対向させることもでき
る。その場合、ＩＯチップ間にフィルムに回路パターン
を印刷した本のを介在させるようにすればよい。ここで
、■（］チップとしては２個以上使用されるものが望ま
しい。また、導電層としては金属或いは導電性樹脂等が
用いられる。Furthermore, the element surfaces of 10 chips can also be made to face each other. In that case, a book with circuit patterns printed on film may be interposed between the IO chips. Here, it is preferable that two or more chips are used as (2) chips. Also, metal, conductive resin, or the like is used as the conductive layer.
この発明による１０カードは、１０チツプが二つ以上重
ね帖り合わされているので曲げに対する耐久力が著るし
く向上する。Since the 10 card according to the present invention has two or more 10 chips stacked together, its durability against bending is significantly improved.
また、チップの素子面側を互に向き合せたものでは素子
がカードの表面側に々いので、鋭い物がカードにあた−
でも素子に影響がなく、カードの信頼性が高まる。Also, if the element sides of the chips face each other, the elements are closer to the front side of the card, so sharp objects may hit the card.
However, it does not affect the elements and increases the reliability of the card.
また、カードの厚さ方向にＩＣチップを２個収容できる
のでＩＣチップを一層にだけ配置する場合に比べ単純に
２倍の実装密度が上がり、月つ配線のひきまわしが少く
なるために、実際の実装密度はさらに向上できる。これ
は１０のチップの数が多い場合に、実装密度の向上でき
ることは大きな利点と彦る。In addition, since two IC chips can be accommodated in the thickness direction of the card, the packaging density is simply doubled compared to arranging IC chips in a single layer, and the amount of wiring required is reduced. The packaging density can be further improved. This is a great advantage in that it can improve the packaging density when there are a large number of 10 chips.
第２図はこの発明の一実施例のｉ０カードの工程の断面
図である。FIG. 2 is a sectional view of the i0 card manufacturing process according to an embodiment of the present invention.
ＣＩ）Ｕの機能を有する０、 ２８ ＩＩ膜厚（３チク
プ２０（ＴＭＰ８００４８東芝Ｉｆりと０．２８ｉｉ＋
厚６４ビットＰＲＯＭ２１ （’Ｉ”ＭＭ２７６４東芝
製）をエポキシ系接着剤２２（エボテックＨ−２０Ｅ
エポキシ・テクノロジー社製）を介して第２図（ａ）
のような構成を行うた。CI) U function 0, 28 II film thickness (3 chips 20 (TMP80048 Toshiba Ifrito 0.28ii+
A 64-bit thick PROM21 ('I'MM2764 made by Toshiba) was glued with epoxy adhesive 22 (Evotech H-20E).
(manufactured by Epoxy Technology) as shown in Figure 2 (a)
I did a configuration like this.
次いで０．３１１１１厚さのポリ塩化ビニールシート２
３．２４を２枚用意し、各々のチップ２０．２１の寸法
より５００μ大きい穴をあけて第２図（ｂ）のように１
０チツプをシートに収容した。Then 0.31111 thick PVC sheet 2
Prepare two pieces of 3.24, drill a hole 500μ larger than the size of each chip 20.
0 chips were accommodated in the sheet.
次いで加熱加圧（１４０℃、１０％）して、一体化した
。Then, they were integrated by heating and pressurizing (140° C., 10%).
次いで、スピンナーで感光性樹脂２５（フォトニースＵ
Ｒ−３１００東し製）を塗布した。塗布膜厚は５μｍで
あった。Next, apply photosensitive resin 25 (Photonice U) using a spinner.
R-3100 (manufactured by Toshi) was applied. The coating film thickness was 5 μm.
次に写真法で■０のボンデングノクット部のみ除去され
るようにマスクを介して紫外線を照射して第２図（Ｃ）
においてピアホール２７を形成した。裏面も同様に行っ
た。さらに上下配線のための０．５ｍ径貫通孔２６のも
のをドリルにより形成した。Next, using a photographic method, ultraviolet rays were irradiated through a mask so that only the bonded nook part of ■0 was removed, as shown in Figure 2 (C).
A pier hole 27 was formed in the step. I did the same thing on the back side. Furthermore, a 0.5 m diameter through hole 26 for upper and lower wiring was formed using a drill.
次にこの貫通孔に平均粒径２μの銀粉を重量比で９２チ
、塩化ビニール樹脂８チ、及びシクロヘモヤノンを溶剤
とする導電性樹脂からなるペーストを流し込み、貫通孔
内を導電性ペースト２９で充満し、さらにＩＯ接続を含
めた回路ノくターン２８を前記導電性ぺ−、ストを用い
て印刷した。これを６０℃で減圧乾燥後、オーバレイと
しての７５μｍの塩化ビニール樹脂フィルムを表裏面に
静置して加熱加圧プレスして一体化した。３０けカード
表面にでるＩｌｏの部分であり、あらかじめ表面にＡ
ｕを１μｍメッキした７５μｍ厚の銅片３１を前記オー
バレイに穴をあけてそこに静置しておいたものである。Next, a paste consisting of silver powder with an average particle size of 2 μm at a weight ratio of 92 cm, vinyl chloride resin of 8 cm, and a conductive resin using cyclohemoyanone as a solvent is poured into this through hole, and the inside of the through hole is filled with conductive paste 29. Further, a circuit circuit 28 including IO connections was printed using the conductive paste. After drying this under reduced pressure at 60° C., a 75 μm vinyl chloride resin film as an overlay was placed on the front and back surfaces and heated and pressed to integrate. This is the Ilo part that appears on the front of the 30-card card, and A is written on the front in advance.
A 75 μm thick copper piece 31 plated with U to a thickness of 1 μm was left in a hole in the overlay.
また、この例で感光性樹脂と塩化ビニールとの間の密着
は余りよくないため、感光性樹脂層にはマスクによって
１ｌｌｊｌの円状に除去されるように回路パターンに影
響しない部分に全面にわたって分布するようにした。こ
のため塩化ビニール２３゜２４とオーバレイ２５との密
着は良好であった。In addition, in this example, since the adhesion between the photosensitive resin and vinyl chloride is not very good, the photosensitive resin layer is distributed over the entire surface in areas that do not affect the circuit pattern, so that it is removed in a circular shape of 1 1 1 ljl by a mask. I decided to do so. Therefore, the adhesion between the vinyl chloride 23°24 and the overlay 25 was good.
１０の収容位置は第３図に示すような位置、即ちカード
の一頂点ＡからＸ方向２５１１％Ｙ方向１５關の位置に
１０チツプの一頂点Ｂがくるように配置した。カードの
長辺は８６ｍｍ、短辺け５４１１１であった。得られた
カードは厚さ０．７５ｍ１１であった。The 10 chips were housed at a position as shown in FIG. 3, that is, one vertex B of the 10 chips was placed at a position 2511% in the X direction and 15 degrees in the Y direction from one vertex A of the card. The long side of the card was 86 mm, and the short side was 54111 mm. The resulting card had a thickness of 0.75 ml.
このカードを、次の条件で各種油げ試験を行つた１とこ
ろ、試験の前後においてカードの機能においていずれも
問題がなかった。When this card was subjected to various oiling tests under the following conditions, no problems were found in the card's functionality before and after the tests.
■長辺方向において、水平面から頂点で２０龍浮き上が
るような曲げくりかえし １０００回■短辺方向におい
て、水平面から頂点で１０１ｍ浮き上がるような曲げく
りかえし １０００回■対角線の角をおさえて１５０の
ねじりを加えてこれをくりかえし１０００回 その後他
の対角線の角をおさえて同様に試験する。■In the long side direction, repeat the bend so that the apex rises 20 meters from the horizontal plane 1000 times ■In the short side direction, repeat the bend so that the apex rises 101 m from the horizontal plane 1000 times ■Hold the diagonal corner and add 150 twists Repeat this 1000 times, then hold the other diagonal corners and test in the same way.
比較のために行った第３図の位置に収容した前記のメモ
リチップを収容したものでは、配線は行なわなかつたも
のの短辺方向の曲げ試験において１００回目の観察でチ
ップが折れていた。また０、１龍のガラスエポキシ基板
上にワイヤボンデングで結線したものを塩化ビニール樹
脂中に収容した従来型ＩＣカードにおい、ても、短辺方
向の曲げ試験で１００回目の観察において■０カードの
機能が損われていた。In the case of the memory chip housed in the position shown in FIG. 3, which was carried out for comparison, the chip was broken at the 100th observation in a bending test in the short side direction, although wiring was not performed. In addition, in a conventional IC card in which wires are connected by wire bonding on a glass epoxy board of 0 and 1 and housed in vinyl chloride resin, even when observed for the 100th time in a bending test in the short side direction, function was impaired.
第５図（ａ）において前述した実施例と同様な方法によ
り、０２０機能を有するＩＣチップ５１及び塩化ビニー
ルシート５２、感光性樹脂層５３、及び４電性樹脂によ
る導体パターン５４を形成した。In FIG. 5(a), an IC chip 51 having a 020 function, a vinyl chloride sheet 52, a photosensitive resin layer 53, and a conductive pattern 54 made of a tetraelectric resin were formed by the same method as in the example described above.
同様にもう１つのメモリチップ５５の方も塩化ビニール
樹脂５６、感光性樹脂５７、導電性樹脂による導体パタ
ーン５８を配したものＡ、Ｂをそれぞれ別個に作成した
。作成法は１０チツプを重ねる工程以外は実施例１と同
様である。Similarly, another memory chip 55, A and B, each having a vinyl chloride resin 56, a photosensitive resin 57, and a conductor pattern 58 made of a conductive resin were prepared separately. The manufacturing method was the same as in Example 1 except for the step of stacking 10 chips.
次いで、嫌気性接着剤をチップの配線面に塗布してから
（ロックタイト３２５日本口ツクタイト社製１．２０μ
ｍの硬質塩化ビニールフィルムをＡ。Next, apply an anaerobic adhesive to the wiring surface of the chip (Loctite 325, manufactured by Nihonguchi Tsuctite Co., Ltd., 1.20μ).
m hard vinyl chloride film A.
Ｂに挿入し、１分間硬化はせた後、力の熱加圧プレス（
１３５℃ １０％）で熱圧着した。After inserting it into B and curing for 1 minute, press it with a strong heat press (
Thermocompression bonding was carried out at 135°C (10%).
次いで、導電パターン５４．５８の結線すべき点に０．
５龍ｙの貫通孔５９を形成した。次にこの貫通孔を実施
例１と同様な導電性樹脂ペーストを充填し、乾燥後導電
パターン６２を印刷で形成し、カードのＩ１０バット６
３を実施例１と同様に静置して７５μの塩化ビニール樹
脂からなるオーバレイ６１を重ね合せて加熱加圧して■
０の素子面側を対向させた１ ０カードを得た。１０カ
ードの位置は実施例１と同様であり、実施例１と同様な
試験においてもＩＯの破損はなかった。Next, 0.
A through hole 59 with a diameter of 5 mm was formed. Next, this through hole is filled with the same conductive resin paste as in Example 1, and after drying, a conductive pattern 62 is formed by printing, and the I10 batt 6 of the card is
3 was allowed to stand still in the same manner as in Example 1, and an overlay 61 made of 75 μm vinyl chloride resin was overlaid and heated and pressed.
A 10 card with the element side of the 0 facing each other was obtained. The position of the 10 card was the same as in Example 1, and even in the same test as in Example 1, there was no damage to the IO.
さらに、１０チツプの内蔵されているカードの表面に５
０ｇの荷重を加えた。蓄針を圧Ｉ〜あて蓄針を移動させ
たところ、カードの表面は傷がついたものの１０カード
の機能は損なわれなかった。In addition, 5 chips are placed on the front of the card with 10 chips built-in.
A load of 0 g was applied. When the accumulator was moved from pressure I to pressure, the surface of the card was scratched, but the function of the 10 card was not impaired.
第１図は本発明のＩＯカードの構成を説明するための断
面図、第２図は本発明の一実施例を説明するための工程
の断面図、第３図は本発明の一実施例におけるＩＣチッ
プの位置を示すための正面図、第４図は従来方法におけ
る１０カードの構成の一例を示す斜視図及び断面図、第
５図は本発明の他の一実施例におけるＩ Ｏカードの工
程の断面図である。
１１．１２・・・ＩＣチップ、１３・・・導体パターン
、１４・・導体パターン、１５・ カード■１０パット
、１６・・・接着層。
代理人弁理士 則 近 憲 佑 （ほか１名）第８図
（ａ）
（ｂ）
第４図FIG. 1 is a cross-sectional view for explaining the structure of the IO card of the present invention, FIG. 2 is a cross-sectional view of a process for explaining one embodiment of the present invention, and FIG. 4 is a perspective view and sectional view showing an example of the structure of 10 cards in the conventional method, and FIG. 5 is a process for forming an IO card in another embodiment of the present invention. FIG. 11.12... IC chip, 13... Conductor pattern, 14... Conductor pattern, 15. Card ■10 pad, 16... Adhesive layer. Representative patent attorney Kensuke Chika (and 1 other person) Figure 8 (a) (b) Figure 4
Claims (1)
せて内蔵したことを特徴とするＩＣカード。(1) An IC card characterized by having a plurality of IC chips built-in, stacked one on top of the other in the thickness direction of the card.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60138907A JPS61297191A (en) | 1985-06-27 | 1985-06-27 | Integrated circuit card |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60138907A JPS61297191A (en) | 1985-06-27 | 1985-06-27 | Integrated circuit card |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61297191A true JPS61297191A (en) | 1986-12-27 |
Family
ID=15232923
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60138907A Pending JPS61297191A (en) | 1985-06-27 | 1985-06-27 | Integrated circuit card |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61297191A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998029263A1 (en) * | 1996-12-27 | 1998-07-09 | Rohm Co., Ltd. | Card mounted with circuit chip and circuit chip module |
| JPWO2021095252A1 (en) * | 2019-11-15 | 2021-05-20 |
-
1985
- 1985-06-27 JP JP60138907A patent/JPS61297191A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998029263A1 (en) * | 1996-12-27 | 1998-07-09 | Rohm Co., Ltd. | Card mounted with circuit chip and circuit chip module |
| JPH10193848A (en) * | 1996-12-27 | 1998-07-28 | Rohm Co Ltd | Circuit chip-mounted card and circuit chip module |
| AU742212B2 (en) * | 1996-12-27 | 2001-12-20 | Rohm Co., Ltd. | Card mounted with circuit chip and circuit chip module |
| CN1080652C (en) * | 1996-12-27 | 2002-03-13 | 罗姆股份有限公司 | Card mounted with circuit chip and circuit chip module |
| US6422473B1 (en) | 1996-12-27 | 2002-07-23 | Rohm Co., Ltd. | Circuit chip mounted card and circuit chip module |
| JPWO2021095252A1 (en) * | 2019-11-15 | 2021-05-20 |
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