JPS6126223B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device.

There are broadly two methods for forming a diffusion layer of a different conductivity type on a semiconductor substrate with a concentration higher than that of the semiconductor substrate. One is to selectively form each diffusion layer region using two different masks, and the other is to use a Si ₃ N ₄ film and selectively oxidize with one mask. This is a method of forming a diffusion layer. In the former case, it is possible to increase the junction breakdown voltage by separating each diffusion layer, but since two masks are used to obtain the desired junction breakdown voltage, the spacing between the diffusion layers must be adjusted in consideration of mask alignment accuracy. This has the disadvantage that the element density of the semiconductor device is reduced more than necessary. The latter method requires only one mask, but has the disadvantage that the respective diffusion layers are in complete contact with each other, making it impossible to increase the junction breakdown voltage.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that eliminates the drawbacks of the above methods and can stably increase the junction breakdown voltage without unnecessarily reducing the element density of the semiconductor device.

The present invention is characterized by an insulated gate type semiconductor device,
A method for manufacturing a semiconductor device including a channel stopper region and a source/drain diffusion layer region located in the channel stopper region via a spaced region, wherein After continuously forming a silicon dioxide film on the source and drain diffusion layer regions and forming a silicon nitride film thereon, the silicon nitride film is left on the source and drain regions and on the channel stopper region, and the silicon dioxide film is left on the source and drain regions and on the channel stopper region. A step of selectively removing the silicon nitride film on the region and forming a thermal oxide film on the removed portion, and then a step of selectively removing the silicon nitride film on the region, and then forming a thermal oxide film on the region other than the channel stopper region and a part of the separated region in contact with the channel stopper region. a step of masking with a photoresist, a step of removing the silicon nitride film remaining in the channel stopper region using the photoresist as a mask, and implanting an impurity of the same conductivity type as the substrate; and after removing the photoresist, Forming a thermal oxide film on the channel stopper region and the separation region, and then removing the silicon nitride film and silicon dioxide film remaining on the gate region between the source and drain to form a gate oxide film. , forming a gate electrode, and forming source and drain diffusion layers.

The present invention will be described below using a method for manufacturing an N-channel insulated gate field effect transistor as an example, while comparing it with a conventional method.

A conventional manufacturing process for an N-channel insulated gate field effect transistor will be described with reference to FIGS. 1a to 1d.

As shown in FIG. 1a, after a SiO ₂ film 2 and a Si ₃ N ₄ film 3 are formed over the entire surface of a P-type semiconductor substrate 1, the source, drain, and gate regions are formed using a photoresist 4 by photolithography. covered with Si ₃ N ₄ film 3
Then, the SiO ₂ film 2 is sequentially etched and boron B is ion-implanted into the channel stopper region to increase the impurity concentration on the semiconductor substrate surface and form a P ⁺ impurity region 5 (FIG. 1b). Thereafter, the photoresist 4 is removed, and at the same time as driving in the P ⁺ impurity region 5 in an oxidizing atmosphere, a field oxide film 6 is formed on the P ⁺ impurity region 5 . In this case, since the Si ₃ N ₄ film 3 is formed on the source, drain, and gate regions, they are not oxidized. Next, Si ₃ N ₄ film 3 and SiO ₂ film 2 are deposited on the source, drain, and gate regions.
(FIG. 1C), form a gate oxide film 7, and form a gate electrode 8 of polysilicon, then diffuse phosphorus into the source/drain region and the gate electrode 8 of polysilicon by a melt-through method in an oxidizing atmosphere. Do push-in. A source diffusion layer 9 and a drain diffusion layer 10 are formed. After that, openings are made on the source and drain diffusion layers, and a source electrode 11 and a drain region 12 are formed using aluminum.
(Figure 1d).

According to the above conventional method, the source and drain diffusion layers 9 and 10 are connected to the field oxide film 6 and the gate electrode 8.
Since it is formed using a mask as P ⁺ impurity region 5
completely in contact with Therefore, there is a drawback that the junction breakdown voltage of the source and drain diffusion layers decreases and the junction capacitance increases.

Next, referring to FIGS. 2a to 2d, the source of a conventional N-channel insulated gate field effect transistor,
The manufacturing process for separating the drain diffusion layer and channel stopper region will be described. Semiconductor substrate 1
A SiO ₂ film 2 is formed on the SiO 2 film 2, the SiO ₂ film in the channel stopper region is etched by photolithography, and boron ions are implanted using the SiO ₂ film 2 as a mask. (Figure 2a). Next, P ⁺ impurity concentration regions 5 are formed by indentation in an oxidizing atmosphere, and areas other than the source, drain, and gate regions are covered with photoresist 4 by photolithography (Fig. 2b), and the source, drain, and gate regions are The upper SiO ₂ film 2 is etched (FIG. 2c). Thereafter, the gate is oxidized in the same manner as in the conventional method, a gate electrode 8 is formed of polysilicon, source and drain diffusion layers 9 and 10 are formed, contact holes are opened, and source and drain electrodes 11 and 10 are formed.
12 (Fig. 2d).

Although the P ⁺ impurity region 5 and the source/drain diffusion layer can be provided separately from the channel stopper region 5 by the above-mentioned conventional method, a mask that limits the P ⁺ impurity region and a mask that limits the source, drain, and gate regions are required. It is necessary to consider the mask alignment accuracy l of There is a drawback.

Next, an embodiment in which the present invention is applied to the manufacture of an N-channel insulated gate field effect transistor will be described with reference to FIGS. 3a to 3f.

First, a SiO ₂ film 2 and a Si ₃ N ₄ film 3 are deposited on a semiconductor substrate 1.
(Figure 3a). Next, by photolithography, the P ⁺ impurity region and the source, drain, and gate regions are defined with a first mask and covered with a photoresist 4 (FIG. 3b). Separation region 13 between P ⁺ impurity region and source/drain diffusion layer
After etching the Si ₃ N ₄ film 3 and removing the photoresist 4, the SiO ₂ film 14 is thermally oxidized to a thickness that can be used as a mask for ion implantation to form a P ⁺ impurity region on the isolation region 13. (Fig. 3c). Thereafter, the source, drain, and gate regions are defined with a second mask by photolithography and covered with a photoresist 4, and after removing the thin oxide film on the Si ₃ N ₄ film 3, the Si ₃ N ₄ film 3 is removed. , the SiO ₂ film 2 is sequentially etched. At this time,
Although a portion of the SiO ₂ film 14 is also etched, the film thickness is set in advance in consideration of the thickness of the SiO ₂ film 2 to be removed by etching. After that, using the photoresist 4' and the SiO ₂ film 14 on the isolation area as a mask,
Boron ions are implanted to form a P ⁺ impurity region (FIG. 3d). After that, after removing the photoresist, the P ⁺ impurity region 5 is pushed in an oxidizing atmosphere, and at the same time a field oxide film 6 is formed on the P ⁺ impurity region.
on the source, drain, and gate regions.
The Si ₃ N ₄ film 3 and the SiO ₂ film 2 are sequentially etched (FIG. 3e). Thereafter, a gate oxide film 7 is formed and a gate electrode 8 is formed of polysilicon in the same manner as in the conventional method described above. Source and drain diffusion layers 9 and 10 are formed using the field oxide film 6 and gate electrode 8 as masks, and at the same time the gate electrode is formed. Dope polysilicon, open contact holes, and form source and drain electrodes 1.
1 and 12 (Fig. 3 f).

According to the above embodiment, SiO ₂ on the separation region between the P ⁺ impurity region 5 and the source/drain diffusion layers 9 and 10
Since the film serves as a mask for boron ion implantation to form a P ⁺ impurity region similarly to the photoresist 4' formed by the second mask, the distance of the isolation region 13 is determined by the mask alignment between the first mask and the second mask. (Generally, in order to improve the junction breakdown voltage, the separation region needs to be about 5μ, taking into account the junction depth, and the mask alignment accuracy is about 1 to 2μ.) The first mask is used to cover the source, drain, and gate regions positioned by the first mask; in fact, the first mask positions the P ⁺ impurity region, the isolation region, and the source, drain, and gate regions. Therefore, there is no need to consider the mask alignment accuracy of the first mask and the second mask, and P ⁺
Since the isolation regions between the impurity region and the source and drain diffusion layers can be positioned with high precision, the distance between the isolation regions can be kept at the minimum required distance, and the junction breakdown voltage can be stably improved without unnecessarily reducing the element density of the semiconductor device. Junction capacitance can be reduced.

In the above example, both the P ⁺ impurity region and the drain and source diffusion layers are separated, but if only one of them is to be separated, the position of the P ⁺ impurity region on the side of the diffusion layer that is not separated is determined using the second mask. In addition, when forming a transistor in which the P ⁺ impurity region and the source/drain diffusion layer are separated and a transistor in which the source and drain diffusion layers are not separated in one semiconductor device, the second mask is used to similarly separate the diffusion layer side that is not separated.
All that is necessary is to position the P ⁺ impurity region. Even in this case, the invention can be applied without impairing the advantages of the invention. In addition, in the above embodiment, ion implantation is performed to form the P ^{+ impurity} region, and melt-through diffusion is performed to form the source and drain diffusion layers. Ion implantation may be used to form the layer. In that case, the SiO ₂ film 2 and Si ₃ N ₄ film 3 may be made thick enough to serve as a mask for diffusion, and the polysilicon of the gate electrode may be made thick enough to serve as a mask for ion implantation. In addition, in the above embodiment, melt-through diffusion was performed, so the gate oxide film in the source and drain regions was not removed. However, when implanting impurities by ion implantation, etc., the polysilicon is etched and then the source is etched using the polysilicon as a mask. ,
The gate oxide film on the drain region may be removed.

Further, in the above embodiment, an N-channel insulating effect transistor was described, but the present invention can also be applied to a P-channel insulating effect transistor.

As explained above, according to the manufacturing method of the present invention, by positioning the separation region between the first conductivity type impurity region and the second conductivity type impurity region using a single mask, the element density of the semiconductor device is reduced more than necessary. It is possible to stably improve the junction breakdown voltage and reduce the junction capacitance without causing any damage.

[Brief explanation of the drawing]

1A to 1D are cross-sectional views showing the manufacturing process of an N-channel insulated gate field effect transistor using a conventional flat method, and FIGS.
Figures a to d are cross-sectional views showing the conventional manufacturing process when the source and drain diffusion layers and channel stopper regions of an N-channel insulated gate field effect transistor are provided separately;
FIGS. 3a to 3f are cross-sectional views showing the manufacturing process of one embodiment of the present invention. 1... Semiconductor substrate, 2... SiO ₂ film, 3...
Si ₃ N ₄ film, 4,4'...photoresist, 5...P ⁺
Impurity region, 6... Field oxide film, 7... Gate oxide film, 8... Gate electrode, 9... Source diffusion layer, 10... Drain diffusion layer, 11... Source electrode, 12... Drain electrode, 13 ... Separation region, 14 ... SiO ₂ film in the separation region.

Claims (1)

[Claims] 1. A method for manufacturing an insulated gate semiconductor device including a channel stopper region and a source/drain diffusion layer region located in the channel stopper region via a spaced region, wherein the channel stopper region on a semiconductor substrate After forming a silicon dioxide film continuously on the separation region and the source and drain diffusion layer regions and forming a silicon nitride film thereon, a step of selectively removing the silicon nitride film on the separated region, leaving a silicon nitride film, and forming a thermal oxide film on the removed portion, and then forming a thermal oxide film on the channel stopper region and in contact with the channel stopper region; a step of masking areas other than a part of the separation region with a photoresist, a step of removing the silicon nitride film remaining in the channel stopper region using the photoresist as a mask, and implanting an impurity of the same conductivity type as the substrate; After removing the photoresist, forming a thermal oxide film on the channel stopper region and the spacing region;
The method further comprises the step of removing the silicon nitride film and silicon dioxide film remaining on the gate region between the source and drain, forming a gate oxide film and a gate electrode, and forming a source and drain diffusion layer. A method for manufacturing a semiconductor device.