JPH0212012B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device in which device characteristics do not change.

FIG. 1 is a cross-sectional view of a semiconductor device obtained by a conventional manufacturing method. By providing a p-type region 4 with a high impurity concentration below a channel in a p-type semiconductor substrate 1, an n-type source region 2, an n-type The MOS transistor structure prevents a current that is poorly controlled by the gate electrode 6 from flowing between the shaped drain regions 3 and also prevents a significant increase in stray capacitance between the source regions 2 and drain regions 3 and the p-type regions 4. Proposed. Note that 5 is a gate insulating film, 7 and 8 are source and drain electrodes, respectively.
9 is an insulating film.

This structure consists of source and drain regions 2, 3
It has a drawback that the device characteristics change due to changes in the relative positions of the p-type region 4 and the p-type region 4. It consists of an exposure process for forming source and drain regions 2 and 3 and a p
This is because the exposure process for forming the shaped region 4 is performed separately, and the relative position varies depending on the alignment accuracy.

This invention was made to eliminate the above-mentioned drawbacks, and the source and drain regions and p
The relative position with respect to the shaped region is determined in one exposure process, so that a semiconductor device with stable element characteristics can be obtained. This invention will be explained in detail below.

FIGS. 2a to 2f are cross-sectional views of manufacturing steps showing an embodiment of the present invention. First, as shown in Figure 2a, p
A polysilicon layer 12 doped with n-type impurities is formed on a shaped semiconductor substrate 11 . Note that the polysilicon layer 12 is usually formed so that only the region where a predetermined transistor is formed is in direct contact with the surface of the semiconductor substrate. Next, an insulating film 13 such as SiO ₂ is deposited on the polysilicon layer 12, a nitride film 14 is deposited on the polysilicon layer 12, and a resist film 15 is deposited on the polysilicon layer 12, and an opening 27 is formed in a predetermined portion of the resist film 15.

Next, the nitride film 14 exposed in the opening 27 and the insulating film 13 are sequentially removed as shown in FIG. 2b, to expose the polysilicon layer 12.

Next, the resist film 15 is removed, and the polysilicon layer 12 exposed in the opening 27 is oxidized to form an oxide film 16 as shown in FIG. 2c. In this case, the n-type impurity doped in the polysilicon layer 12 may be oxidized at a low temperature to prevent it from diffusing into the semiconductor substrate 11 as much as possible, or the impurity may be ion-implanted only into the polysilicon layer 12 exposed in the opening 27. Possible methods include doping with carbon to slow down the oxidation rate.
However, even if such a method is used, the n-type impurity doped into the polysilicon layer 12 diffuses into the semiconductor substrate 11, as shown in FIG. There are cases. Therefore, the subsequent steps will be explained assuming that the n-type region 17 has been formed.

Next, as shown in FIG. 2d, using the nitride film 14 as a mask, the oxide film 16 is removed by a method with less lateral etching, such as ion beam etching, to expose the semiconductor substrate surface, and then etched by the same or other etching method. The surface of the semiconductor substrate is removed to an extent exceeding the depth of the n-type region 17 using the method described above. Note that 16' is the remaining portion of the oxide film 16.

Next, a p-type impurity is implanted at a predetermined depth through the opening 27 by ion implantation to form a p-type impurity region 18.

Next, a gate oxide film 19 is formed as shown in FIG. 2e. Note that p-type impurity region 18 may be formed after forming gate oxide film 19.

Next, the n-type impurity is further diffused from the polysilicon layer 12 by a thermal process, and the p-type impurity region 1
After activating the ions implanted in 8 and forming a p-type high impurity concentration region 20 as shown in FIG. 2f, and removing the nitride film 14, a gate electrode 26 is provided.

Note that the remaining portion 16' of the insulating film 13 and the oxide film 16
An insulating film 21 is formed by the diffusion of n-type impurities in the polysilicon layer 12.
2. A drain region 23 is formed, and the polysilicon layer 12 on both of these regions becomes a source electrode 24 and a drain electrode 25, respectively.

In the above process description, p-type high impurity concentration region 2
It is important that the p-type impurity introduction port for forming 0 and the n-type impurity introduction port for forming the source and drain regions 22 and 23 are positioned relative to the opening 27. The p-type high impurity concentration region 20 and the source and drain regions 22 and 23 are positioned by one exposure process.

FIGS. 3a to 3c are manufacturing process diagrams showing another embodiment of the present invention. The manufacturing process of this example is the second
After going through the same steps as shown in FIG. 3B, as shown in FIG. 3A, the polysilicon layer 12 is further removed through the opening 27 to expose the surface of the semiconductor substrate.

Next, in an oxidation step, the side surface of the polysilicon layer 12 facing the opening 27 and the surface of the semiconductor substrate are oxidized to form an oxide film 28. From now on, Fig. 2 d
By going through the steps similar to those described below, a semiconductor device having a structure similar to that shown in FIG. 2, as shown in FIG. 3c, can be obtained.

Note that in the above embodiment, the p-type semiconductor substrate 11
It goes without saying that a semiconductor substrate of the opposite conductivity type may be used. In that case, the conductivity type of each part may be opposite. Further, although the opening 27 was used as an impurity introduction port for forming the p-type high impurity concentration region 20, any opening 27 may be used as long as the impurity can be introduced into a predetermined position. Similarly, the impurity introduction ports for forming the source region 22 and the drain region 23 do not necessarily have to be in the form of openings, but can introduce the necessary impurities as shown in the embodiments shown in FIGS. 2 and 3. It is fine as long as it can be done.

As described in detail above, the present invention is capable of determining the relative positions of the impurity introduction port for forming a high impurity concentration and the impurity introduction ports for forming the source region and the drain region in one exposure process. Therefore, the relative positioning of the source region, the drain region, and the high impurity concentration region can be performed with high precision. Furthermore, an oxide film is formed on the side surfaces of the opening, and the thickness of this film can be controlled, so that by increasing the thickness, the interelectrode capacitance can be reduced. Therefore, there is an advantage that a stable high-quality semiconductor device can be obtained without causing a change in element characteristics unlike the conventional method.

[Brief explanation of drawings]

Figure 1 is a cross-sectional view of a conventional semiconductor device, Figure 2a
-f are sectional views of the manufacturing process showing one embodiment of the present invention, and Figures 3a to 3c are sectional views of the manufacturing process showing another embodiment of the invention. In the figure, 11 is a p-type semiconductor substrate, 12 is a polysilicon layer, 13 and 21 are insulating films, 14 is a nitride film,
15 is a resist film, 16 is an oxide film, 16' is the remainder,
17 is an n-type region, 18 is a p-type impurity region, 19 is a gate oxide film, 20 is a p-type high impurity concentration region, 2
2 is a source region, 23 is a drain region, 24 is a source electrode, 25 is a drain electrode, 26 is a gate electrode, 27 is an opening, 28 is an oxide film, and 29 is a metal material.

Claims (1)

[Claims] 1 The first conductivity type semiconductor substrate has the first
a source region and a drain region of a second conductivity type opposite to the conductivity type, further comprising a channel region on the surface portion of the semiconductor substrate, and a gate electrode provided on the channel region with a gate insulating film interposed therebetween; A method for manufacturing a semiconductor device having at least a first conductivity type high impurity concentration region localized in the semiconductor substrate at a predetermined depth below the channel region,
forming a three-layer thin film on the surface of the semiconductor substrate in which a polysilicon layer doped with impurities of a second conductivity type, an oxide film, and a nitride film are sequentially laminated; and forming an opening in a predetermined portion of the three-layer thin film; exposing the polysilicon layer or the semiconductor surface;
oxidizing the polysilicon layer exposed in the opening to convert a predetermined length of the polysilicon layer from the opening end under the nitride film into an oxide film, and using the nitride film as a mask to convert the polysilicon layer exposed in the opening a step of removing the oxide film leaving a portion under the nitride film to expose the semiconductor surface; and introducing an impurity of a first conductivity type to a predetermined depth of the semiconductor substrate through the opening using the nitride film as a mask. Then, the step of forming the high impurity concentration region and the step of introducing the second conductivity type impurity in the remaining polysilicon layer into the semiconductor and forming the source and drain regions in the same exposure step for the high impurity concentration region are performed. 1. A method of manufacturing a semiconductor device, comprising at least a step of forming the semiconductor device in a predetermined position.