JPS5951152B2 - Manufacturing method of semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device.

A conventional silicon gate MOS transistor was constructed as shown in FIG.

In the figure, 1 is a silicon substrate, 2 is a source region, 3 is a drain region, 4 is a field silicon dioxide film, and 5 is a silicon substrate.
5 is a silicon dioxide film for gates, 6 is a polycrystalline silicon film for gates, 7 is a polycrystalline silicon film for wiring, 8 is a silicon dioxide film grown by a vapor phase growth method, Ba is a corner of the silicon dioxide film, 9 is a silicon dioxide film For example, aluminum electrodes are shown. In the silicon gate MOS transistor having such a structure, since the corner portion 8a of the silicon dioxide film is approximately at a right angle, there is a problem in that the electrode 9 becomes thin at that portion and is easily disconnected. To solve this problem, a silicon gate MOS transistor as shown in FIG. 2 was proposed. This transistor is manufactured by cutting the corners of a silicon dioxide film to form an inclined surface, laminating a polycrystalline silicon film on this silicon dioxide film 4, and selectively oxidizing the polycrystalline silicon film using a silicon nitride film 10 as a mask to form a silicon dioxide film. The structure is the same as that of FIG. 1 except that a polycrystalline silicon film 10a and a wiring polycrystalline silicon film 7 are formed. In this transistor, since the corner portions of the silicon dioxide film 4 are sloped surfaces, the corner portions 8a of the silicon dioxide film 8 stacked thereon are also sloped surfaces. Therefore, the problem of the electrode 9 becoming thinner and breaking at the corner 8a has been solved. However, since the level difference between the silicon dioxide film 8 and the silicon substrate 1 has not been eliminated, it has been difficult to achieve high integration. On the other hand, short channel MOS
In order to improve the breakdown voltage drop due to the punch-through phenomenon between the source and drain and to reduce the dependence of the threshold voltage on the channel length, the transistor has source and drain diffusion layers 2 and 3 as shown in FIG. , shallow portions 2a and 3a are formed. Furthermore, since making the entire structure shallow increases the sheet resistance and lowers the PN junction breakdown voltage, deep portions 2b and 3b are also formed. Other parts are the same as in FIG. The deep parts 2b, 3b of the source, drain, and diffusion layers 2, 3 are formed by a thermal diffusion method, and the shallow parts 2a, 3a are formed by an ion implantation method or a so-called forced diffusion method in which thermal diffusion is performed through a silicon dioxide film. be done. However, the ion implantation method requires complicated operations and requires forced diffusion. According to this method, manufacturing is not easy because N-type impurities are difficult to intrude and shallow diffusion is difficult. SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device that can easily manufacture a high-voltage semiconductor device.

The method for manufacturing a semiconductor device of this invention is an N-channel MOS.
Transistors will be explained.

First, as shown in FIG. 4A, a silicon dioxide film 12 is formed on a silicon substrate 11, and an opening 12a is provided in the silicon dioxide film 12 using a photoresist film pattern. The surrounded portion of the silicon dioxide film 12 is defined as a gate oxide film 12b. This gate oxide film 1
The width of 2b is chosen to be 1-4 μm in order to realize a short channel MOS transistor. Next, silicon substrate 1
A polycrystalline silicon film 13 is laminated on top of the polycrystalline silicon film 13. Next, as shown in FIG. 4B, a silicon nitride film 14 is formed on the polycrystalline silicon film 13, and a silicon dioxide film (not shown) is formed on this silicon nitride film 14, using a photoresist mask. Then pattern the silicon dioxide film. Then, the silicon nitride film 14 is patterned using the patterned silicon dioxide film as a mask. In this way, the pattern mask of the silicon nitride film 14 is formed on the polycrystalline silicon film 13 corresponding to the gate oxide film 12b and part of the source and drain regions on both sides thereof. Then, using the pattern mask of the silicon nitride film 14, the polycrystalline silicon film 13 is replaced with the gate oxide film 1.
The field oxide film 15a is selectively oxidized until reaching 2b.
, an oxide film 15b for electrode isolation is formed. As a result, a thick portion 13a and a thin portion 13b of the polycrystalline silicon film 13 are formed in the source and drain regions. This thick portion 13a becomes the source and drain electrode portions. Note that 13c is a portion of the polycrystalline silicon film 13 corresponding to a gate electrode portion. In addition, the polycrystalline silicon film 13
In selective oxidation, when the polycrystalline silicon film 13 is oxidized, the thickness becomes almost double the initial thickness. Therefore, in order to flatten the element surface, it is necessary to etch the increased thickness in advance. . Next, as shown in FIG. 4C, after removing the pattern mask of the silicon nitride film 14, an N-type impurity (phosphorus or arsenic) is added to the silicon substrate
heat diffuses to. As a result, the N-type impurity is contained in the polycrystalline silicon film portion 13C corresponding to the gate electrode portion and the polycrystalline silicon film portions 13a and 13 in the source and drain regions.
b. The N-type impurities diffused into the polycrystalline silicon film portions 13a and 13b of the source and drain regions are further diffused into the silicon substrate 11 to form source and drain diffusion layers 16. At this time, the thick part 1 of the polycrystalline silicon film in the source and drain regions
Since the N-type impurity is diffused deeply into the silicon substrate 11 from 3a, the deep portion 16 of the source/drain diffusion layer 16
A is formed, and the N-type impurity is diffused shallowly from the thin portion 13b, so that a shallow portion 16b of the source/drain diffusion layer 16 is formed. Note that the diffusion of the N-type impurity is restricted by the gate oxide film 12b and the oxide films 15a and 15b, so that it is not diffused into the silicon substrate 11 from this portion. Next, as shown in Figure 4D,
A silicon dioxide film 17 is laminated on the surface of the element to form electrode openings 18, and an aluminum film 19 is formed in a desired pattern for wiring. In this way, according to this embodiment, the polycrystalline silicon film 13 in the source and drain regions
A thick part 13a and a thin part 13b are formed in the source and drain diffusion layer 16 using the thick part 13a and the thin part 13b.
Since the shallow portion a and the shallow portion 16b are formed, an N-channel MOS transistor with high breakdown voltage can be easily manufactured.

In addition, the source and drain regions and the aluminum wiring are not in direct contact with each other, and the impurity-doped polycrystalline silicon film 1
Since layers 3a and 13c are used as intermediate conductive layers, the entire surface of the device can be flattened. the result,
High integration can be achieved. FIG. 5 is an explanatory diagram of another embodiment of the invention.

That is, the silicon substrate 1 on both sides of the gate oxide film 12b
A stepped portion is formed by etching the portion 1, and a polycrystalline silicon film 13 is filled therein, and the polycrystalline silicon film 3 is selectively oxidized to form a thick portion of the polycrystalline silicon film in the source and drain regions. 13a and a thin portion is formed. The rest is the same as the previous embodiment. As a result, the oxidation depth during selective oxidation of the polycrystalline silicon film 13 can be selected within a wide range from beyond the upper end surface of the gate oxide film 12b to reaching the etching step of the silicon substrate 11. can. As a result, selective oxidation of polycrystalline silicon film 13 can be easily controlled. As described above, the method for manufacturing a semiconductor device of the present invention includes forming a first insulating layer on the main surface of a substrate of one conductivity type, and forming a second insulating layer sandwiching the first region of the main surface of the substrate.
and forming an opening in the first insulating layer so that a third region is exposed; stacking a polycrystalline silicon film on the first insulating layer; a step of stacking an insulating layer and removing a portion of the second insulating layer, leaving a portion of the second insulating layer corresponding to the entire first region of the main surface of the substrate and the outside of the second and third regions; The polycrystalline silicon film is selectively oxidized to a silicon oxide film using the second insulating layer portion as a mask so as to extend beyond the upper end of the first insulating layer on the first region. , forming a thin layer of unoxidized polycrystalline silicon film inside the third region; removing the remaining second insulating layer to expose the polycrystalline silicon film; An impurity layer of the other conductivity type is diffused into the substrate to form a shallow portion of the diffusion layer under the thin layer of unoxidized polycrystalline silicon film, and an impurity layer of the other conductivity type is diffused into the substrate to form a shallow portion of the diffusion layer under the thin layer of unoxidized polycrystalline silicon film. Since the method includes a step of forming a deep portion of the diffusion layer, a semiconductor device with high breakdown voltage can be easily manufactured.

Further, by adding a step of exposing the polycrystalline silicon film and making the surface of the silicon oxide film substantially flush with the surface of the polycrystalline silicon film, a highly integrated semiconductor device can be manufactured.

[Brief explanation of drawings]

Figures 1 to 3 are explanatory diagrams explaining the drawbacks of the conventional example;
FIG. 4 is a process explanatory diagram of one embodiment of the present invention, and FIG. 5 is a process explanatory diagram of another embodiment. DESCRIPTION OF SYMBOLS 11... Silicon substrate, 12... Silicon dioxide film, 12a... Opening part, 12b...
...Gate oxide film,]3...Polycrystalline silicon film, 13a...Thick film part, 13b...
Thin film portion, ]4...Silicon nitride film, 15a...
... Field oxide film, J5b ... Oxide film for electrode separation, 16 ... Source, drain diffusion layer, 16a ... Deep part, 16b ...・Shallow part.

Claims (1)

[Scope of Claims] 1. A first insulating layer is formed on the main surface of a substrate of one conductivity type, and second and third insulating layers are formed as source and drain regions, respectively, sandwiching a first region that becomes a channel region on the main surface of the substrate. forming an opening in the first insulating layer to expose a region; laminating a polycrystalline silicon film on the first insulating layer and the exposed portion; insulating layers are laminated, and the second insulating layer is selectively removed to cover the entire surface of the first region of the main surface of the substrate and the second and third insulating layers.
a step of leaving a part of the second insulating layer on the region; and using the remaining second insulating layer as a mask, applying the polycrystalline silicon film to the top surface of the first insulating layer on the first region. a step of leaving a thin layer of an unoxidized polycrystalline silicon film in a part of the second and third regions by selectively oxidizing the polycrystalline silicon film to a silicon oxide film so as to cover the second and third regions; and is removed to expose the polycrystalline silicon film, and an impurity layer of the other conductivity type from the polycrystalline silicon film is diffused into the substrate to form the impurity layer below the thin layer of the unoxidized polycrystalline silicon film. A method for manufacturing a semiconductor device, comprising the steps of forming shallow portions of the source and drain regions and forming deep portions of the source and drain regions below the exposed polycrystalline silicon film. 2. A first insulating layer is formed on the main surface of a substrate of one conductivity type so that second and third regions, which will become source and drain regions, respectively, sandwiching a first region which will become a channel region on the main surface of the substrate are exposed. forming an opening in the first insulating layer, laminating a polycrystalline silicon film on the first insulating layer and the exposed portion, and further laminating a second insulating layer on the polycrystalline silicon film. , the second insulating layer is selectively removed to completely cover the first region and the second and third regions of the main surface of the substrate.
a step of leaving a part of the second insulating layer on the region; and using the remaining second insulating layer as a mask, applying the polycrystalline silicon film to the upper end of the first insulating layer on the first region. a step of leaving a thin layer of an unoxidized polycrystalline silicon film in a part of the second and third regions by selectively oxidizing the polycrystalline silicon film to a silicon oxide film so as to cover the second and third regions; and removing the polycrystalline silicon film thereunder to expose the polycrystalline silicon film so that the surface of the silicon oxide film is substantially flush with the surface of the polycrystalline silicon film, and removing impurities of a conductivity type other than the exposed polycrystalline silicon film. a layer is diffused into the substrate to form shallow portions of the source and drain regions under the thin layer of unoxidized polycrystalline silicon film and to form shallow portions of the source and drain regions under the exposed polysilicon film. A method for manufacturing a semiconductor device including a step of forming a deep portion of a drain region.