JPS61232633A - Semiconductor integrated circuit device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a master slice type semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device that aims to increase the utilization rate of elements such as transistors and capacitors.

[Conventional technology]

A master slice type semiconductor integrated circuit device is a MOS
A large number of elements such as transistors and capacitors are formed in an array, and these are appropriately wired to obtain a desired circuit device. Generally, MOS transistors are mainly required to configure operational amplifiers and analog switches, and capacitors are required to configure swissotide capacitor filters and MOS analog/digital converters.

In conventional devices of this kind, a long gate length transistor is preferable from the viewpoint of noise for the input stage transistor of the operational amplifier, and a short channel length transistor is preferable from the viewpoint of driving ability for the output stage transistor, etc. Usually, a configuration is provided in which several types of MUS transistors with different gate lengths and gate widths and capacitors with different capacities are arranged.

[Problem that the invention seeks to solve]

Although the conventional semiconductor integrated circuit device described above is equipped with MOS transistors with several types of gate lengths and gate widths, the composition ratio of each gate length and width transistor required for the circuit to be realized is determined by the device. If it does not match the composition ratio of each gate length/width transistor,
The ratio of the number of available transistors to the total number of transistors included in a device, that is, the transistor utilization rate, is reduced, resulting in an increase in device chip size, a decrease in yield, and
This will result in increased costs. This also applies to capacitors.

Furthermore, since the conventional method uses several types of transistors, it is difficult to arrange transistors of the same type symmetrically, which makes it incompatible with fully differential circuit technology that can improve the power supply noise rejection ratio. There is also the problem of not being able to fully benefit from the technology.

[Failure to solve the problem]

In the semiconductor integrated circuit device of the present invention, M(JS) transistors and capacitors are arranged with the same standard, and preferably an array of 1M08 transistors is arranged on both sides of an array of capacitors. The array is arranged line-symmetrically with respect to the array.

In a semiconductor integrated circuit device with 0MO8 configuration, P channel M
The OS transistor and the N-channel MOS transistor are each equal and symmetrical with respect to the capacitor arrangement.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a partial plan view showing an embodiment of the semiconductor integrated circuit device of the present invention, and shows one unit of the arrangement of each element. In the figure, 1 is a capacitor array, and 2.3 is an MUS transistor array arranged on both sides of this capacitor array 10.

In the capacitor array 1, all four capacitors 3 are configured to the same standard with a common first electrode 4 and individually provided second electrodes 5, and these are integrated into a vertical force circuit, which is horizontally connected. There are multiple rows of them.

The λ1i (JS) transistor array 2 is composed of an N-channel MO8 transistor array 6 provided on the capacitor array side and a P-channel MO8 transistor array 7 provided outside of the N-channel MO8 transistor array 6.
gate 8 and an N-type gate formed correspondingly thereto.
A plurality of equal N-channel MO8 transistors 10 each having a drain region 9 are arranged in rows in the horizontal direction.

Similarly, the P-channel MO8 transistor array 7 is composed of a plurality of equal P-channel MO8 transistors each composed of a gate electrode 11 and a correspondingly formed P-type source/drain region 12.
U8 transistors 13 are arranged in rows in the horizontal direction.

In the inspection, the N-channel MO8 transistor row 6 and the P-channel MUD transistor row 7 are arranged so as to be symmetrical with respect to the center line S along the direction in which the capacitor array 1 is arranged. Further, in this example, the gate width (channel width) of the N-channel MO8 transistor 10 is slightly smaller than that of the P-channel MJS transistor 13.

Therefore, according to such a configuration, as represented by the N-channel MO8 transistor 10, for example,
If you want to configure a MOS transistor with twice the gate length, you can easily obtain it by connecting two MO8 transistors IOA and IOB in series with a contact 20 and a wiring 21 as shown in Figure 2. can. Furthermore, if two MUS transistors 1OC and 10D are connected in parallel using a contact 22 and a wiring 23 as shown in FIG. 3, a MOS transistor with twice the gate width can be constructed. Of course, if three or more MOS transistors are connected in series or in parallel, the gate length will be three times or more.

A MOS transistor with a gate width can be configured.

FIG. 4 shows an example in which the fully differential amplifier shown in FIG. 5 is constructed using the semiconductor integrated circuit device. Select two P-channel MOS transistors QPI QP□ from the channel MUS transistor row 7, and similarly
Channel MUS transistor array 6 to two channel MO8 transistors QNI each.

QN2, QN3, and QN4 are selected, and these are connected by a contact 24 and a wiring 25.

With this configuration, MUS transistors of the same standard and symmetrically formed are wired symmetrically to form a fully differential amplifier, and characteristics with the same power supply noise rejection ratio can be obtained.

Although an application example of the capacitor array is omitted here, any capacitance can be obtained by connecting any number of capacitors in parallel.

Note that the present invention is equally applicable to H-channel or P-channel MO8 type semiconductor integrated circuit devices.

〔Effect of the invention〕

As explained above, in the present invention, since the capacitor and the MUS transistor are configured to the same standard, it is possible to easily obtain a capacitor or a HIOS transistor of any standard by combining these, and it is possible to easily obtain a capacitor or a HIOS transistor of any standard. It can be achieved. Furthermore, by arranging the capacitors and the 1v108 transistors line-symmetrically, the symmetry of the characteristics in the case of configuring the circuit can be made excellent, and the effects of the fully differential circuit technology can be fully obtained.

[Brief explanation of the drawing]

FIG. 1 is a partial plan view of an element arrangement according to an embodiment of the present invention, and FIGS. 2 and 3 show gate lengths, respectively. FIG. 4 is a plan view showing a transistor configuration when doubling the gate width, FIG. 4 is a plan view showing an example of the configuration of a fully differential amplifier, and FIG.
The diagram is required for the circuit diagram. 1...Capacitor array, 2...hio
s transistor array, 3... capacitor, 6.
...408 transistor rows to N channel, 7...
...P-channel MO8 transistor row, 10...
...N-channel Pvios transistor, 13...
. . . P-channel type l08 transistor, 20, 22.
24...Contact, 21,23°25...
...Wiring, QN1-QN4 ...N-channel PvIJS transistor, QpI QP2 ...
...P channel MOS transistor, S...
center line.

Claims (3)

[Claims] (1) A semiconductor integrated circuit device comprising an array of MOS transistors and capacitors, characterized in that the MOS transistors and the capacitors have the same standard. (2) The semiconductor integrated circuit device according to claim 1, wherein the MOS transistors include a P-channel MOS transistor and an N-channel MOS transistor, and the MOS transistors of each channel are formed to the same standard. (3) The array composed of MOS transistors is arranged on both sides of the array composed of capacitors and is line-symmetrical with respect to the array of capacitors as claimed in claim 1 or 2. The semiconductor integrated circuit device described in .