JPS6350851Y2 - - Google Patents

Description

[Detailed explanation of the idea]

The present invention relates to a semiconductor device, particularly a master slice that can configure various CMIS/ICs by changing wiring. CMIS (complementary metal-insulator-semiconductor) devices include inverters, NAND gates, NOR gates, and various other logic elements, but they have many common parts, so they are master slices that only have source and drain regions formed on the substrate and no wiring. mass-produce it,
By applying various types of wiring to this master slice to manufacture desired logic elements, manufacturing costs, time required, etc. can be greatly reduced.
There are many benefits to be gained. However, in this type of conventional method, the master slice consists of at most two or three types.
It could only be used for CMIS/IC, and there was not much profit. This invention significantly improves this and provides a master slice that can be used for many, for example, over 20 types of CMIS/IC, and
It is very effective when used for. In a semiconductor device that can configure various CMIS-ICs by changing wiring, the present invention forms a well of an opposite conductivity type in a semiconductor substrate of a first conductivity type, and forms a well in the center and both sides of the well of the opposite conductivity type. forming a first conductivity type channel FET pair having a first conductivity type source/drain region and a gate electrode between the two regions; and forming a first conductivity type channel FET pair in the first conductivity type semiconductor substrate. Corresponding to the FET pair, opposite conduction type source/drain regions are formed at the center and on both sides thereof, and an opposite conduction type channel FET pair is provided with a gate electrode between the two regions, and the first conduction type channel Among the FET pair and the opposite conduction type channel FET pair, the P channel FET
The first conduction type channel FET has a gate width larger than that of the N-channel FET and has an equal gate length.
a plurality of unit cells each formed of a pair of channel FETs of opposite conductivity type and a pair of channel FETs of opposite conductivity type are arranged and formed separately and independently, and a high impurity concentration region of a first conductivity type is formed on the side of the semiconductor substrate of the first conductivity type; and a high impurity concentration region of the opposite conductivity type is formed on the well side of the opposite conductivity type at a position sandwiching the unit cell for power connection. will be explained in detail. FIG. 1 shows one constituent element (unit cell) of a master slice according to the present invention, and in the present invention, a master slice is a structure in which a large number of such constituent elements are arranged on a semiconductor substrate. As shown in the figure, this component consists of a central source/drain region (a region that serves as both a source and drain region) 2, source/drain regions 1 and 3 on both sides, and gate electrodes 7 and 8 between these regions. For example, a portion A corresponding to two n ^- channel FETs (field effect transistors) provided in a p ^- type well 14 of an opposite conductivity type to an n - type semiconductor substrate 13 and a central source/drain region 5 and source/drain regions 4, 6 on both sides thereof, and gate electrodes 9, 1 between these regions.
0, and consists of a portion B provided on the n ^- type semiconductor substrate 13 and corresponding to two P channel FETs. 14a is a p ⁺ type channel cut region provided at the periphery of the p ⁻ type well 14, and 13a is an n ⁺ type channel cut region provided in the substrate around portion B. 11 is another one for power supply V _SS
2 is a contact window for power supply V _DD . When the constituent elements (unit cells) have the above-described structure, series-parallel connection of FETs, etc. can be performed extremely easily. That is, as shown in FIG. 2a, the source/drain region 1 is connected to the power source V _SS or V _DD , the source/drain region 3 is used as an output electrode, and the input signals S ₁ and S ₂ are applied to the gate electrodes 7 and 8, respectively. As shown in figure b, the FET is
A circuit is obtained in which the two are connected in series. Further, as shown in Figure c, the source/drain regions 1 and 3 are commonly connected to serve as an output electrode, the source/drain region 2 is connected to a power supply V _SS or V _DD , and the gate electrodes 7 and 8 are connected to an input signal S. ₁ and _S2 , this becomes a circuit with two FETs connected in parallel, as shown in Figure d.
Furthermore, as shown in figure e, if the gate electrodes 7 and 8 are also connected in common and the input signal S is added to them, this results in a single gate whose width is doubled.
Configure FET. In order to increase the gate width by 3 times, 4 times, etc., it is sufficient to use a plurality of the constituent elements shown in FIG. 1 and connect them in parallel in the same way. In the component (unit cell) shown in FIG. 1, the gate width is different between the n-channel FET pair part A and the P-channel FET pair part B, and the latter is twice as large as the former. This is due to the following reason. That is, when configuring a CMIS inverter, it is better to make the gate lengths Ln and Lp of the n-channel FET (Qn) and p-channel FET (Qp) equal for breakdown voltage and other reasons, but in this case, the electron mobility μn and the hole movement Ratio of degree μp μn/
Since μp is approximately 2, in order to equalize the mutual conductance gm of these FETs, it is necessary to set the gate widths Wn and Wp of FETs Qn and Qp to Wp/Wn=2. If gm of FET Qp and Qn are made equal,
The threshold value V _THO of the CMIS inverter can be set to V _DD /2 (here the same sign is used for the power supply and its voltage), thereby maximizing the noise margin of the inverter. In this way, Wp/Wn=
If it is set to 2, the AC transient characteristics of the CMIS inverter will be good (t _TLH = t _THL ), and the DC characteristics (input/output characteristics) will also be good. Each of the constituent elements (unit cells) shown in Figure 1
Depending on the type of logic element to be assembled, the FET portion may or may not be directly connected to a power supply. Figure 3a shows a well-known CMIS inverter, Figure 3b shows a NAND gate, and Figure 3c shows a NOR gate.In general, in the case of CMIS, the power supply (ground) V _SS is connected to the source region of the n-channel FET Qn and the substrate of the FET. Connected to some p ^- type wells.
If this connection cannot be made directly with aluminum wiring, a diffusion layer is used, but n-channel FET Qn
In this case, it is easy to use the p ⁺ type layer, which is the channel stopper, so it is used. However, in normal impurity diffusion, boron (B) is used as an impurity for p-type and phosphorus (P) is used for n-type, and the diffusible impurity concentration of boron is about one order of magnitude lower than that of phosphorus. When using a p ⁺ type channel stopper such as this, there is a problem in terms of conductivity. Therefore, in the present invention, as shown in FIG. 4, a p ^- type well 14 is used, and an n ⁺ layer 15 is formed therein separately from the source/drain regions 1 and 2, and this is used as a part of the power supply line. In this example, 1 is used as a drain region and 2 is used as a source region, and the source/drain region 3 and gate electrode 8 are omitted for simplicity.
The FET pair is illustrated as one FET. 16
is a p ⁺ type channel stopper provided around the n-channel FET formed by 1, 2, and 7;
7 to 21 are electrodes or lead wire parts formed by vapor-depositing aluminum, 22 is an insulating layer such as SiO ₂ , and the power supply V _SS is 17-14a-15-16-2
It is connected to the source region 2 through a path of 0. Note 1
8 and 19 are used as signal lines. When using the diffusion layer of the wiring for the power supply V _DD , the channel stopper of the p-channel FET Qp is an n ⁺ type region, so it can be used. Fifth
The figure shows an example, 23 is an n ⁺ type channel stopper formed on the n ^- type substrate 13, 24 to 28
is an electrode or lead wire made of vapor-deposited aluminum, and is a p-channel FET formed by 4, 5, and 9.
The connection of the power supply V _DD to the source region 4 of Qp is 2
The route is 4-23-27-4. Also in this example, the source/drain region 6 and the gate electrode 10 are omitted for simplicity, and the FET pair is illustrated as one FET, and 25 and 26 are used as signal lines. Since the power supply V _SS is connected to the n-channel FET Qn and the power supply V _DD is connected to the p-channel FET Qp, these electrode windows 11 and 12 are shaped like strips along the FETs Qn and Qp, as shown in FIG. These electrode windows and source/drain regions 1 to 1 are formed in advance.
By connecting predetermined regions 3, 4 to 6 with aluminum wiring, any of regions 1 to 3 or 4 to 6 can be used as a source region. Figures 6 and 7 show examples of configuring various CMIS logic circuits using the master slice of the present invention; the former is a quad 2 OR gate using four out of five sets of constituent elements; The latter shows an example of a quad 2 AND gate. Figure 6 corner two
The equivalent circuit of the OR gate is shown in Figure 8,

Performs the logic of [Formula]. Inverters I ₁ to I ₄ and NAND gate NA are connected to the upper p-channel FET Qp as shown in FIG.
It is obtained by connecting the lower n-channel FET Qn. In this figure, inverter I ₃ is connected in parallel with FET Qp of the FETs Qp and Qn on the right side of the drawing, and Qp is connected in parallel with FET Qp that constitutes inverter I ₃ .
Qn is getting used to playing. Furthermore, two FETs Qp and Qn forming the inverter _I4 are connected in parallel. The equivalent circuit of the quad-to-and-gate shown in Fig. 7 is as shown in Fig. 9, and the equivalent circuit of Fig. 6 and 8 is as shown in Fig. 9.
Compared to the Kado to Or shown in the figure, the Nand Gate is simply replaced by the Noah Gate NR. Corresponding parts are indicated with the same reference numerals. As is clear from the detailed explanation above,
According to the present invention, for example, by providing 16 elements in a master slice and simply changing the wiring pattern of one layer, quad-to-or, quad-to-and (i.e., 2-input OR or AND), 4-circuit, triple-3 (3-input. More than 20 types of logic circuits can be constructed, including dual-four (4-input, 2-circuit), single-eight (8-input, 1-circuit), and exclusive-OR circuits, and the wiring pattern design is particularly easy. . Of course, if the number of constituent elements is further increased, a wider variety of logic circuits can be constructed, and the manufacturing cost and time required for LSI etc. can be greatly reduced.

[Brief explanation of drawings]

FIG. 1 is a plan view showing the constituent elements (unit cells) of a semiconductor device according to the present invention, FIG. c is a circuit diagram showing an example of a CMIS gate, FIGS. 4 and 5 are cross-sectional views explaining the power supply wiring method, FIGS. 6 and 7 are plan views showing examples of master slice connection, and FIGS. FIG. 9 is an equivalent circuit diagram of FIGS. 6 and 7. In the drawing, 1 to 3 and 4 to 6 are source/drain regions, 7, 8, 9, and 10 are gate electrodes, 13 is a semiconductor substrate, and 14 is a well.

Claims (1)

[Claims for Utility Model Registration] In a semiconductor device that can configure various CMIS-ICs by changing wiring, a well of an opposite conductivity type is formed in a semiconductor substrate of a first conductivity type, and a well of an opposite conductivity type is formed in the center of the well of the opposite conductivity type. and a first conductivity type channel FET pair having a first conductivity type source/drain region on both sides thereof and a gate electrode between the two regions, and forming a first conductivity type channel FET pair in the first conductivity type semiconductor substrate. Corresponding to the pair of channel FETs of one conductivity type, source/drain regions of opposite conductivity type are formed at the center and on both sides thereof, and a pair of channel FETs of opposite conductivity type is formed with a gate electrode between the two regions, Of the pair of channel FETs of one conductivity type and the pair of channel FETs of opposite conductivity type, one consisting of a P channel FET has a gate width larger than that of the pair consisting of an N channel FET, and is formed to have an equal gate length; A plurality of unit cells each composed of a pair of first conduction type channel FETs and a pair of opposite conduction type channel FETs are formed in a separate and independent array, 1. A semiconductor device comprising: a high impurity concentration region of an opposite conductivity type formed on a semiconductor substrate side of the semiconductor substrate; and a high impurity concentration region of an opposite conductivity type formed at a position sandwiching the unit cell between the wells for power supply connection.