JPS63292647A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To change the rise-up of an output signal slowly, by connecting the gate parts of at least two or more MOSFETs in series, thereby sequentially shifting the switching starting time of each MOSFET. CONSTITUTION:Polysilicon parts, which are to become the gates of MOSFETs, are continuously formed in series. Contacts 8 for diffused regions 2 and 3 and an aluminum layer 5 are provided on both sides of a polysilicon gate 4. Dotted line parts P and P form one P-channel MOSFET. Eight units such as these are connected in series for the P-channel MOSFET. Eight units are connected in series also for N-channel MOSFETs. In this structure, switching of each FET is sequentially performed from P1 or N1 at a constant delay interval. Therefore, the rise-up and fall-down of a signal waveform, which is outputted from an output terminal become gentle, and noises to signal lines and power source lines are decreased.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to eight output driver circuits that are part of the configuration of a large-scale integrated circuit device (LSI), and particularly relates to noise generated in power supply lines, signal lines, etc. Regarding a structure for reducing.

[Conventional technology]

In an LSI, a large number of circuit elements are formed on one semiconductor chip to provide circuit functions.

LSIs have a small current driving capacity for signals flowing inside them, so when outputting signals to other chips or external equipment, the distance between the chips or external equipment is longer than inside the LSI, resulting in attenuation. easy. Therefore, an output driver is usually provided on the output end side of the LSI to increase the current driving capability.

In a normal gate array type LSI, multiple MO5
An output driver is configured by connecting the outputs of type field effect transistors (MOSFETs) in parallel. FIG. 4(a) is a plan view of a layout pattern of the circuit configuration of an output driver showing an example thereof, and FIG. 4<C) is an equivalent circuit of the configuration. In the figure, 1 is a p-type well region formed in an n-type semiconductor substrate, and 2 is an n-M well region formed in the well region 1.
A diffusion region for O8, 3 a diffusion region for pMO3 formed in the semiconductor substrate, 54 a polysilicon gate 1-
155 is the first N-th aluminum layer, 6 is the second aluminum layer, 57 is the first aluminum layer 55-4 and p
58 is a contact between the first aluminum layer 55-2, 55-3 and each diffusion region 2.3, 59 is a contact between the first aluminum layer 55-4 and the power supply line. Contact 6-1, 60 is the input signal line between the first J-th aluminum layer 55-5 and the polysilicon gate.
) indicates contact with i54.

In FIG. 4(a), an n-type semiconductor substrate has a p-well region 1 and a diffusion region 2 for an nMOS formed therein.
and pMO3 diffusion regions 3 are formed, and N-
MOSFETs and P-MOSFEs shown as P1-P8
A driver circuit is formed by providing multilayer wiring on the substrate using a glabella insulating film (not shown). That is,
In the first M aluminum layer 55, the bonding pad 55
-1, an output signal line 55-2 including contact formation layers 55-3 and 55-4 with the power supply line, and an input signal line 55-5 are formed, and the power supply line (Vss
line 6-1, DD line 6-2).

In multilayer wiring, since the second aluminum layer 6 cannot be directly connected to the semiconductor substrate, for example, when connecting the p-well region 1 and the Vss line 6-1, the method shown in FIG.
), a contact 57 is formed between the p-well region 1 formed in the substrate S and the first aluminum layer 55-4, and the first aluminum layer 55-4 and the Vss
A contact 59 is formed in the glabella insulating film between the lines 6-1 to complete the connection. Connections between the I-th aluminum layer 55 and each diffusion region are also formed and wired so as to obtain the equivalent circuit shown in FIG. 4(C). That is, the fourth
To illustrate the P-MOSFET shown by the dotted line P in Figure (a), the input signal is
is inputted to the polysilicon gate 54 from the contact 60, and outputted from the contact 58 to the bonding pad 55-1 through the output side signal line 55-2. Also 58
' denotes a contact between the diffusion region 3 and the first aluminum layer 55-3, which is connected to the second aluminum layer (in this case, the VDD line 6-2) via a contact 59'. Other MOSFETs are connected in the same way, and as a result, P1 to P8, N1 to N8, as shown in the equivalent circuit of FIG. 4(C).
It has a structure in which complementary MO5FETs consisting of are connected in parallel.

[Problem that the invention seeks to solve]

However, in the driver circuit configuration shown in FIG.
-5, the switching of the P-MOSFETs Pi to P8 and the switching of the N-MOSFETs N1 to N8 are performed almost simultaneously, as is clear from FIG. 4(c). Therefore, there is a problem in that the rising and falling slopes of the transient voltage waveform during switching when a signal is input become steep, which causes large induced noise to be generated in the power supply line and the signal line.

Therefore, an object of the present invention is to solve the above problems by implementing an LSI
The present invention provides an output driver having a circuit configuration such that the output signal of the output driver changes slowly.

[Means and operations for solving the problem] In an output driver circuit using complementary MOSFETs in an LSI, the gate portions of at least two MOSFETs are connected in series.

With this configuration, each MO3FET and MO
A delay circuit mainly composed of a polysilicon gate between SFETs, a stray capacitance in a gate oxide film, and a polysilicon resistor is used as a delay element of each transistor. This delay circuit is always formed in the manual stage of each MOS FET, so that the switching start time of each MOS FET is sequentially shifted, and thus the rise of the output signal changes slowly.

〔Example〕

(1) First Embodiment One embodiment of the present invention will be described with reference to FIGS. 1 and 2.

FIG. 1(a) is a plan view of an example of the layout pattern of the output driver of the present invention, FIG. 1(b) is an equivalent circuit diagram thereof, and FIG. 2 is a diagram illustrating the basic principle of this embodiment.

In FIG. 1, 1 is a p-well region formed in a semiconductor substrate, 2 is a diffusion region for nMOS, and 3 is a pMO3
4 is the polysilicon gate, 4' is its input 4-r, 5 is the first aluminum layer 1.6 is the power supply line, 6-1 is the Vss line, 6-2 is the VD
D line, 7 is the contact between the first layer aluminum layer 5 and the p-well region 1; 1-18 is the contact between the first layer aluminum layer 5 and each diffusion region 2.3; 9 is the contact between the first layer aluminum layer 5 and each diffusion region 2.3; Contact between aluminum layer 5 and power supply line 6 is shown.

In FIG. 1(a), the semiconductor substrate has a p-well region 1 similar to the conventional example explained in FIG.
A diffusion region 2 for pMO3 and a diffusion region 3 for pMO3 are formed,
A P-MOSFET Pi-P8 is formed by a polysilicon gate 4 formed through a gate oxide film (not shown).
, N-MO3FETN1 to N8 are formed on this semiconductor substrate through a glabella insulating film (not shown).
A multilayer wiring including a first aluminum layer 5 and a second aluminum layer 6 is provided. That is, the first aluminum layer 5 includes an output side signal line 5-2 including a bonding pad 5-1, and a contact formation layer 5-3.5- with a diffusion layer.
The second layer of aluminum N6 constitutes the Vss line 6-1 and the VDD line 6-2.

As is clear from FIG. 1(a), in this embodiment, each MO8F
Polysilicon that becomes the gate of the ET is formed continuously in series. By providing contacts 8 between each diffusion region 2.3 and the aluminum layer 5 on both sides of the polysilicon gate 4, the dotted line portions P and P in FIG. 1(a) form one P-channel MO3FET. As shown in FIG. 2, one FET and the polysilicon gate 4 in its vicinity form a delay element by the stray capacitance 34 formed by the polysilicon gate and the underlying gate oxide film, and the resistance 33 of the polysilicon gate. B is now formed on its input side. In the pattern of Fig. 1(a), eight such units are connected in series for P-channel M-O3FET, and eight such units are connected in series for N-channel MO3FET. The equivalent circuit diagram is shown in FIG. 1' (tt).

In Fig. 1(b), one FET is connected from the signal input.
The delay T until switching of Pn is the delay time T+ due to the stray capacitance of FET Pl and the resistance of polysilicon, FE
Since it is the sum of the delay time T2- of TP2, (T=TI +
T2 + - Tn) Switching of each FET is performed sequentially from Pl or N1 at a fixed delay interval.

Therefore, the rising and falling edges of the signal waveform outputted to the output end are smooth, and noise to the signal line and power supply line is reduced.

(2) Second embodiment Another embodiment of the present invention will be explained with reference to FIG.

When actually connecting a large number of polysilicon gates in series, or changing the output signal by staggering the switching start time of each F7E'T, if the delay time is too long, the time until switching may be delayed too much, causing the signal to change. have a negative impact on

Therefore, in the second implementation, the polysilicon gate is separated into a polysilicon gate 40 for the N-channel FET portion and a polysilicon gate 41 for the P-channel FET portion, and input signal lines are connected to both ends of each polysilicon gate 40 and 41, respectively. The structure includes a contact IO with the first aluminum layer 5-5.

With this structure, the input signals to the P-channel FET and N-channel FET are input from two places through the two contacts 10.10, so that the overall switching delay is half that of the first embodiment.

〔Effect of the invention〕

By adopting the configuration of the present invention, it is possible to sequentially delay the start of switching of each FET in response to the input signal to the output driver of the LSI, and therefore, by slowly changing the output signal of the driver, noise generated in the power supply line and signal line can be reduced. You can lower the level.

Furthermore, by shortening the length of the polysilicon gate layers arranged in series and simultaneously inputting signals from a plurality of locations, the switching delay of each transistor can be shortened and the signal waveform can be made variable.

[Brief explanation of drawings]

FIG. 1(a) is a plan view of a layout pattern according to an embodiment of the present invention, FIG. 1(b) is an equivalent circuit diagram thereof, FIG. 2 is a detailed explanatory diagram of the present invention, and FIG. 3 is a plan view of a layout pattern of an embodiment of the present invention. Layout pattern of the example, Fig. 4 (a
) is a plan view of a conventional layout pattern, FIG. 4(b) is an explanatory diagram of its wiring state, and FIG. 4(C) is its equivalent circuit diagram. 1 = It-well region 2-n diffusion region for MOS 3-pMO5 diffusion region 4.40.41-polysilicon gate 5-first layer aluminum layer 6-second layer aluminum layer

Claims (3)

[Claims] (1) A gate array integrated circuit having an output driver in which the outputs of a plurality of field effect transistors are connected in parallel, including an output driver in which gates connected to input signal lines of at least two or more field effect transistors are connected in series. A semiconductor integrated circuit device characterized by: (2) The semiconductor integrated circuit device according to claim 1, wherein the gate is made of polysilicon. (3) The first aspect of the present invention is characterized in that the gates are connected in series in an N-channel field effect transistor section and a P-channel field effect transistor section, respectively.
The semiconductor integrated circuit device described in .