JPS61227423A - Synchronous circuit - Google Patents

Abstract

PURPOSE:To apply phase matching of clock signals by deciding a change position in which the adjacent storage contents differ mutually in the order corresponding to the order of a delay signal of plural latch circuits. CONSTITUTION:Suppose that an inverter train is longer so that a delay time larger than the period of a clock input signal C1 inputted to an inverter 11 exists, the waveform having a period of the clock C1 is formed. The waveform is stored in D flip-flops 21-25 at the leading of a synchronous input signal S1 to decide a position where a signal stored in the adjacent flip-flops changes from a low to a high level. AND gates 31-34 are used to decide the changed position and to gate an output of a delay circuit. It is possible to output plural signals satisfying the said condition from the AND gates 31-34, but an OR gate 41 overlaps them to obtain a desired clock output signal C0 without practical hindrance where the clock high levels are sprad more or less.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a synchronization circuit that synchronizes a clock signal with other signals.

[Conventional technology]

Conventionally, this type of synchronous circuit inputs a significant signal and a clock signal to a D-type flip-flop, etc., and generates a signal in which the significant signal is delayed until the rising edge or falling edge of the clock signal. , the signal was synchronized with the clock signal.

[Problem that the invention seeks to solve]

Since the conventional synchronization circuit described above achieves synchronization by delaying the significant signal to the clock signal, the synchronized signal is expected to have a delay corresponding to the maximum clock period with respect to the significant signal. Therefore, the delay in the operation caused by this synchronized signal with respect to the significant signal has a variation equivalent to the clock cycle, and the accuracy of the response operation to the significant signal is limited by the clock cycle. There is.

[Means for solving problems]

The synchronous circuit of the present invention includes a delay circuit that outputs a plurality of delayed signals obtained by sequentially delaying a clock signal, and a plurality of delay circuits that respectively store states of the plurality of delayed signals at the time of synchronization with a synchronous input signal. a latch circuit of the plurality of latch circuits, a change position determination circuit that determines a change position in which the memory contents of adjacent ones in the head corresponding to the order of the delayed signals of the plurality of latch circuits are different; and a gate circuit that allows the delayed signal to pass through.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

Clock input signal C! is input to the delay circuit 1, which outputs a plurality of signals that are sequentially delayed little by little. A plurality of delayed output signals of the delay circuit 1 are input to a latch circuit 2 and a gate circuit 4.

The latch circuit 2 receives the synchronous input signal S! A plurality of output signals from the delay circuit 1 at the time of the rising edge of the delay circuit 1 are stored, and the stored signals are input to the change position determination circuit 3.

The change position determination circuit 3 detects signals that are different from each other among the plurality of signals input to the latch circuit 2, and determines the position at which the stored signal in the latch circuit is changing. This shows how far the signal CX travels through the delay circuit 1 from when the clock input signal CI changes until when the synchronous input signal S2 rises. The gate circuit 4 inputs the output of the delay circuit 1 and the determination result of the change position determining circuit 3, and outputs the output of the delay circuit 1 corresponding to this change position as a clock output signal co.

FIG. 2 is a circuit diagram of the embodiment shown in FIG.

Clock input signal CI is input to inverter 11, and inverters 11 to 19 are connected in series, with inverter 19 being the final stage. These inverters 11~
19 is a set of two tables υ, and their outputs are input to data input terminals of corresponding D-type flip-flops 22-25 and AND gates 31-34, respectively. In addition, the clock input signal CI is input to the D type flip-flop 21.
is input to the data input terminal of Synchronous input signal S! is D
It is input to the clock input terminals of type flip-flops 21 to 25, and operates at the rising edge of the signal.

AND gates 31 to 34 are three-man-operated AND gates, which output signals from the corresponding locations of the inverter arrays 11 to 19, and the positive outputs of the two corresponding front stages and the inverted outputs of the rear stages of the D type flip-flops 21 to 25. is the input. OR
+gate 41 inputs the outputs of AND gates 31 to 34, and this output becomes clock output signal co.

Inverters 11 to 19 form a delay circuit in pairs, and correspond to delay circuit 1 in FIG. Further, assuming that this inverter array is so long that it has a delay time longer than the cycle of the clock input signal CI input to the inverter 11, a waveform of one cycle of the clock CI is created here. This waveform is synchronized with the input signal S! (startup), the D type flip-flop 21
~25, D type flip 70 knobs 21~25
Determine the position where the signal stored in the matching (next to) changes from low level to high level. The delay time of the output of the delay circuit made up of inverters 11 to 19 corresponding to this changing position corresponds to the time from the rise of the clock input signal CI to the rise of the synchronization input signal SX. Therefore, the delay circuit output at this change position is a delay signal of the signal CI that rises in synchronization with the rise of the synchronous input signal Sx. The AND gates 31 to 34 serve both to determine the change position and to gate the delay circuit output at that position.

There is a possibility that a plurality of signals satisfying this condition are outputted from the AND gates 31 to 34.

Although the high level of the clock increases somewhat when the signals are superimposed by the OR gate 41, the desired clock output signal Cot- can be obtained without causing any practical problems.

FIG. 3 is a timing diagram showing the operation of the circuit diagram shown in FIG. 2. The clock output signal co is the synchronous input signal S! This shows that the signal is switched when the clock CI rises, and the signal has the same period as the clock CI.

〔Effect of the invention〕

As explained above, the present invention provides means for generating a clock signal that is synchronized with the significant signal when synchronizing the significant signal with the clock signal, thereby reducing variations in response to the significant signal. This has the advantage that the phases of clock signals in systems that operate using many independent clock signals can be adjusted using one synchronization signal.

[Brief explanation of drawings]

1 and 2 are a block diagram and a circuit diagram showing one embodiment of the present invention, respectively, and FIG. 3 is a timing diagram showing the operation of the circuit diagram shown in FIG. 2. CI...Riatsuk input signal %S!・・・・・・
Synchronous input signal, co...Clock output signal, 1
1-19... Inverter, 21-25...
...D type flip-flop, 31-34...
・AND gate% 41...OR1 gate. ¥1 autopsy

Claims (1)

[Claims] a delay circuit that outputs a plurality of delayed signals obtained by sequentially delaying a clock signal; a plurality of latch circuits that respectively store states of the plurality of delay signals at the time of synchronization with a synchronization input signal; a change position determination circuit for determining a change position where adjacent ones in the order corresponding to the order of the delayed signals of the latch circuit have different stored contents; and a gate for passing the delayed signal corresponding to the change position. A synchronous circuit comprising a circuit.