JPH04363914A - Synchronization clock generator - Google Patents

Abstract

PURPOSE:To realize the synchronization clock having high synchronization precision without need of a high frequency clock. CONSTITUTION:Delay clocks DC1-DC5 generated by delaying a reference clock S1 are given in a one-to-one correspondence to clock input terminals CK of flip-flips 201-205. Moreover, the delay clocks DC1-DC5 are given to an input terminal group of as clock selection circuit 221. Furthermore, output signals S201-S205 are given to the other input terminal group of the clock selection circuit 221. Moreover, an asynchronous signal S2 is given to a reset input terminal R of the flip-flops 201-205, and output signals S201-S205 from a data output terminal Q of the clock selection circuit 221. In the circuit 221, a clock closest to an edge of the asynchronizing signal S2 among the delay clocks DC1-DC5 is detected and a desired clock is selected among the delay clocks DC1-DC5 in response to the result of detection, Thus, the synchronization clock is outputted with high precision from the clock selection circuit 221.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous clock generation circuit that synchronizes a reference clock input signal with an external asynchronous input signal and outputs it as a synchronous clock.

0002

2. Description of the Related Art FIG. 12 is a block diagram showing a conventional synchronous clock generation circuit. As shown in the figure, an asynchronous signal S2 is applied to one input of a counter 402 from an asynchronous signal input terminal 2 into which an asynchronous trigger signal is input, and a frequency division enable signal S4 is an output of the counter 402.
02 is given to the frequency divider 403. Also, a high frequency clock S4 which is the output of the high frequency clock generation circuit 401
01 is applied to the other input of the counter 402 and the other input of the frequency divider 403, and the synchronous clock S5, which is the output of the frequency divider 403, is applied to the synchronous clock output terminal 5.

Note that the frequency of the high frequency clock S401 is higher than the frequency of the synchronous clock S5.

Next, the operation will be explained. FIG. 13 is a timing chart showing the operation of a conventional synchronous clock generation circuit. As shown in the figure, when the counter 402 detects the trigger of the asynchronous signal S2 from the asynchronous signal input terminal 2, it starts counting the high frequency clock S401 which is the output of the high frequency clock generation circuit 401. When the count reaches a certain number (3 in this example), the counter 402 outputs a frequency division enable signal S402 to the frequency divider 403. By the frequency division enable signal S402, the frequency divider 40
3 divides the high frequency clock S401 by a predetermined frequency division ratio (8 in this example) and outputs it from the synchronous clock output terminal 5 as the synchronous clock S5.

In this conventional circuit, even if the falling edge of the trigger input of the asynchronous signal S2 fluctuates within the range shown by the broken line in FIG. 13, the synchronous clock S5 comes out at the same timing. In other words, the synchronization accuracy is high frequency clock S401
The higher the frequency, the better the synchronization accuracy, and approximately, it can be said that the synchronization accuracy = the period of the high frequency clock S401.

For example, if it is desired to obtain a synchronization accuracy of 1 ns, the frequency of the high frequency clock S401 must be 1 GHz.

[0007]

Since the conventional synchronous clock generation circuit is constructed as described above, it has been necessary to increase the frequency of the high-frequency clock in order to improve the synchronization accuracy. However, there are problems with noise generated inside the synchronization clock generation circuit, and there is a limit to increasing the frequency of the high-frequency clock, resulting in the problem that high synchronization accuracy cannot be obtained.

[0008] This invention was made to solve the above problems, and does not require a high frequency clock.
The purpose of this invention is to obtain a synchronous clock generation circuit with high synchronization accuracy.

[0009]

[Means for Solving the Problems] A synchronous clock generation circuit according to a first aspect of the present invention is a synchronous clock generation circuit that generates a synchronous clock synchronized with an asynchronous input signal, and is configured by connecting a plurality of delay elements in series. , a delay clock generation circuit that generates a plurality of delayed clocks by sequentially delaying a reference clock with a delay element, and a delay clock generation circuit that is activated in response to an asynchronous input signal and stores a predetermined value by controlling each of the plurality of delay clocks. A memory circuit consisting of a plurality of memory elements, and outputs of the plurality of memory elements are used as control signals to detect the clock whose edge is temporally closest to the edge of the asynchronous input signal from among the plurality of delayed clocks. The clock selection circuit selects a desired delay clock from a plurality of delay clocks according to the detection result and outputs the selected delay clock as a synchronization clock.

A synchronous clock generation circuit according to a second aspect of the invention is a synchronous clock generation circuit that generates a synchronous clock synchronized with an asynchronous input signal, and is configured by connecting a plurality of delay elements in series, and a reference clock is connected to the delay element. A delay clock generation circuit that generates multiple delayed clocks by sequentially delaying them with As a control signal, one of the plurality of delayed clocks whose edge is temporally closest to the edge of the asynchronous input signal is detected,
The clock selection circuit selects a desired delay clock from among the plurality of delay clocks according to the detection result and outputs the selected delay clock as a synchronization clock.

[0011]

[Operation] In the first aspect of the invention, a plurality of delayed clocks are generated by sequentially delaying a reference clock using a delay element, and a memory circuit consisting of a plurality of memory elements activated in response to an asynchronous input signal. A predetermined value is stored by controlling each of the plurality of delay clocks, and the output of the plurality of storage elements is used as a control signal, and from among the plurality of delay clocks, the clock whose edge is temporally closest to the edge of the asynchronous input signal is used. , selects the desired delayed clock from among multiple delayed clocks according to the detection result, and outputs it as a synchronous clock. Therefore, a high-precision synchronous clock can be generated without the need for a high-frequency clock generation circuit. can be generated.

[0012] In the second invention, a plurality of delayed clocks are generated by sequentially delaying a reference clock using delay elements, and a plurality of delayed clocks are generated by controlling an asynchronous input signal to a storage circuit made up of a plurality of storage elements. Using the outputs of multiple storage elements as control signals, one of the multiple delayed clocks whose edge is temporally closest to the edge of the asynchronous input signal is detected, and multiple delayed clocks are stored in accordance with the detection result. Since a desired delayed clock is selected from among the delayed clocks and outputted as a synchronous clock, a highly accurate synchronous clock can be generated without requiring a high frequency clock generation circuit.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a circuit diagram of a synchronous clock generation circuit showing a first embodiment of the present invention. As shown in the figure, the reference clock S1 is input from the reference clock input terminal 1.
is input to the delay element 211, and the delayed clock DC1, which is the output of the delay element 211, is input to the delay element 212.The reference clock S1 input from the reference clock input terminal 1 is input to the delay elements 211 to 215 in turn. is given to.

Further, the delayed clock DC1, which is the output of the delay element 211, is connected to the negative logic clock input terminal CK of the flip-flop 201, and the delayed clock DC2, which is the output of the delay element 212, is connected to the negative logic clock input terminal CK of the flip-flop 202. CK, each delay element 211
Delayed clocks DC1 to D, which are the outputs of
C5 is applied to the negative logic clock input terminals CK of each of the flip-flops 201 to 205 on a one-to-one basis. Further, the delayed clocks DC1 to DC5 are applied to one input terminal group of the clock selection circuit 221.

Further, the asynchronous signal S2 inputted from the asynchronous signal input terminal 2 is input to the flip-flops 201 to 20.
The output signals S201 to S205 from the data output terminal Q are applied to the other input terminal group of the clock selection circuit 221. Furthermore, the output signals S201D to S205D of the output terminal group of the clock selection circuit 221 are output to the flip-flop 2.
01 to 205 are applied to each data input terminal D.

Note that the delay elements after delay element 215 and the flip-flops after flip-flop 205 are omitted.

Next, the operation of the circuit shown in FIG. 1 will be explained. FIG. 2 is a timing chart showing the operation of the circuit shown in FIG. As shown in the figure, the reference clock S1 is applied to the delay element 2.
11 to 215, delay clocks DC1 to DC5 are generated by being delayed by a predetermined time.

Now, as shown in the figure, the asynchronous signal S2 is set to "H".
When a falling trigger from the level to the "L" level occurs, the reset input terminals R of the flip-flops 201 to 205 go to the "L" level, and the flip-flop 2
01 to 205 are ready for operation. Therefore, each of the flip-flops 201 to 205 starts taking in data at the falling edge of the signal input to the clock input terminal CK. When the falling edges E1 and E2 of the delayed clocks DC1 and DC2, which are the outputs of the delay elements 211 and 212, occur, the asynchronous signal S2 is still at the "H" level, so at this timing, the flip-flops 201 and 2
02 cannot operate. For this reason, the flip-flop 20
1, 202 is the level applied to the data input terminal D at the next falling edge E6, E7 of the delayed clocks DC1, DC2 (as described later, the data input terminal D of the flip-flop 201 is at "H" level, the flip-flop 2
The data input terminal D of 02 outputs "L" level) to the output Q as output signals S201 and S202.

Next, when the falling edges E3 to E5 of the delayed clocks DC3 to DC5, which are the outputs of the delay elements 213 to 215, occur, the asynchronous signal S2 is at the "L" level, so the flip-flops 203 to 205 are At this timing, the level applied to the data input terminal D is outputted to the output terminal Q as output signals S203 to S205. Here, as will be described later, an input signal S2 is applied from the clock selection circuit 221 to the data input terminals D of the flip-flops 201 to 205.
The levels of 01D to S205D are all “H” at first.
level, so flip-flops 203 to 20
The output signals S203 to S205 of No. 5 become "H" level.

The clock selection circuit 221 selects the output signals S201 to S2 of the flip-flops 201 to 205.
05, the delay clock corresponding to the one that rises earliest in time, that is, the delay clock whose edge is temporally closest to the edge of the asynchronous input signal S2 (Fig. 2
In the example, the delayed clock DC3) is detected from among the delayed clocks DC1 to DC5. Next, based on this, a desired delayed clock (in the example of FIG. 2, the delayed clock DC3) is selected from among the delayed clocks DC1 to DC5, and outputted from the synchronized clock output terminal 3 as the synchronized clock S3. , the levels of the data input terminals D of the flip-flops 201 to 205 are set so that their selection states do not change thereafter. Note that details of the clock selection circuit 221 will be described later.

Next, another embodiment of the present invention will be described. FIG. 3 is a circuit diagram of a synchronous clock generation circuit showing a second embodiment of the invention. As shown in the figure, the reference clock S1 input from the reference clock input terminal 1 is input to the delay element 211, the delayed clock DC1 which is the output of the delay element 211 is input to the delay element 212, and so on. A reference clock S1 input from an input terminal 1 is sequentially applied to delay elements 211 to 215.

Further, the delayed clock DC1, which is the output of the delay element 211, is connected to the negative logic clock input terminal CK of the flip-flop 201, and the delayed clock DC2, which is the output of the delay element 212, is connected to the negative logic clock input terminal CK of the flip-flop 202. CK, each delay element 211
Delayed clocks DC1 to D, which are the outputs of
C5 is applied to the negative logic clock input terminals CK of each of the flip-flops 201 to 205 on a one-to-one basis. Further, the delayed clocks DC1 to DC5 are applied to one input terminal group of the clock selection circuit 221.

Further, the asynchronous signal S2 inputted from the asynchronous signal input terminal 2 is input to the flip-flops 201 to 20.
It is applied to the set input terminal S of No. 5. Furthermore, the output signal S201D of the output terminal group of the clock selection circuit 221
or S205D are flip-flops 201 to 20
5 are connected to each data input terminal D.

Note that the delay elements after delay element 215 and the flip-flops after flip-flop 205 are omitted.

In the operation of this embodiment, compared to the previous embodiment, the output signal S2 of the clock selection circuit 221, which will be described later, is
The polarities of 01D to S205D are inverted, and the output signals S201 to S20 of flip-flops 201 to 205 among the signals shown in the timing chart of FIG.
This embodiment is the same as the previous embodiment except that the polarities of 5 are all reversed.

As described above, in the embodiments shown in FIGS. 1 and 3, even if the trigger input of the asynchronous signal S2 fluctuates within the range shown by the broken line in FIG. The state of is not changed, and the synchronized clock S3 will come out at the same timing. That is, the synchronization accuracy can be approximated to the delay value of one stage of delay elements 211 to 215. In other words, approximately, it can be said that synchronization accuracy=delay value for one stage of delay element. In a semiconductor integrated circuit, the delay value for one stage of delay elements can be set to 1 ns or less, and extremely high synchronization accuracy can be obtained compared to conventional synchronous clock generation circuits.

FIG. 4 is a circuit diagram showing an example of the structure of the clock selection circuit 221 shown in FIGS. 1 and 3. In FIG. As shown in the figure, the output signals S201 to S205 of the flip-flops 201 to 205 applied to one input terminal group of the clock selection circuit 221 are input to the flip-flop output change point detection circuit 301, and the flip-flop output change detection circuit 301 detects the change in the flip-flop output. The output of the output circuit 301 is connected to the switches 311 to 3.
15 are connected to gate terminals G for controlling conduction and non-conduction. Moreover, the delay elements 212 to 216 (
Delayed clocks DC2 to DC6, which are the outputs of the delay elements 216 (not shown in FIGS. 1 and 3), are applied to the input terminals of the switches 311 to 315.
Each output terminal of 1 to 315 is a multi-input OR circuit 3
21 input. Further, the output of the multi-input OR circuit 321 is connected to the synchronous clock output terminal 3. In addition, the flip-flop output change point detection circuit 301
Output signals S201D to S205D are applied to data input terminals D of flip-flops 201 to 205 in FIGS. 1 and 3.

FIG. 5 is a circuit diagram showing an example of the configuration of a flip-flop output change point detection circuit 301, which is a component of the clock selection circuit 221. As shown in the figure, one of the output signals S201 to S205 of the flip-flops 201 to 205 is inverted, and the other is not inverted.
By inputting 01 to 505, one side can be set to “L”.
” level When the other one is “H” level, the NAND circuit 311
The outputs S311 to S315 of the output terminals S311 to S315 are at "L" level, and are at "H" level at other times. Furthermore, the NAND circuit 50
The outputs from 1 to 505 correspond to the signals S201D to S2.
05D is also applied to the data input terminals D of the flip-flops 201 to 205 in FIG. In the case of the embodiment shown in FIG. 3, as described above, the NAND circuit 50
The inverted output of 1 to 505 is the signal S201D.
or S205D.

Next, the operations of the clock selection circuit shown in FIG. 3 and the flip-flop output change point detection circuit shown in FIG. 4 will be explained. The flip-flop output change point detection circuit 301 detects the output signals S20 of the flip-flops 201 to 205.
1 to S205, adjacent output signals are compared by NAND circuits 501 to 505 in which one input is inverted, and when the levels of the two inputs become the above-described predetermined pattern, the output signals S311 to S205 are compared. It operates by setting one of the switches 315 to "L" level (until then, all of them are in the "H" level state) to make one of the corresponding switches 311 to 315 conductive. In the example of FIG. 2, the output S3 of the NAND circuit 502
12 becomes "L" level, and the corresponding switch 312 becomes conductive. When one of the switches 311 to 315 becomes conductive, a corresponding one of the delayed clocks DC1 to DC5 (delayed clock DC3 in the example of FIG. 2) is applied to the input of the OR circuit 321 through the conductive switch, and the OR circuit The output of the circuit 321 is outputted to the synchronous clock output terminal 3 as the synchronous clock S3.

[0030] Also, at this time, the conductive switch 312
Since the "L" level output of the NAND circuit 502 corresponding to the signal S202D is fed back to the data input terminal D of the flip-flop 202, even if the falling edge E7 of the delayed clock DC2 occurs, the output of the flip-flop 20
The output signal S202 of No. 2 maintains the "L" level, and therefore the "L" level of the output of the NAND circuit 502 also does not change.

FIG. 6 is a circuit diagram showing another example of the structure of the clock selection circuit shown in FIG. 4. As shown in the figure, the connection relationship between the delayed clock and the switch is different from that of the clock selection circuit shown in FIG. That is, the delayed clocks DC1 to D
C5 are connected to the input terminals of switches 311-315, respectively. The rest of the configuration is the same as the clock selection circuit shown in FIG. 4, so the explanation will be omitted.

In the clock selection circuit shown in FIG.
Under the same timing conditions as the clock selection circuit shown in FIG. 4, the synchronous clock S3 output from the synchronous clock output terminal 3 is different. That is, for example, in FIG.
When the timing condition is such that the synchronous clock DC2 is selected, the synchronous clock DC1 is selected in FIG.
In FIG. 6, when the timing condition is such that the synchronous clock DC2 is selected, the synchronous clock DC1 is selected. In this way, the delayed clock output from the synchronous clock output terminal 3 as the synchronous clock S3 can be shifted by one. In this manner, by changing the connection relationship between the delayed clock and the switch, a desired delayed clock can be output from the synchronous clock output terminal as the synchronous clock S3.

Note that in the configuration of FIG. 4, the first delay element 2
The configuration is such that the delayed clock DC1 from 11 is not selected as the synchronous clock S3, and in the configuration of FIG. 6, the delayed clock output from the last delay element is the synchronous clock S3.
The configuration is such that it is not selected as 3. However, Figure 4
In this case, if the number of delay elements is prepared so that the reference clock S1 can be delayed by one period or more, the delayed clock DC
Since a delayed clock having the same phase as 1 appears after the delayed clock DC5, a delayed clock having the same phase as the delayed clock DC1 can be selected as the synchronous clock S3. Also,
Also in FIG. 6, the number of delay elements is set to 1 when the reference clock S1 is
If you prepare for a delay of more than one cycle, the delayed clock that is in phase with the delayed clock output from the last delay element will appear before the delayed clock output from the last delay element.
A delayed clock that is in phase with the delayed clock output by the last delay element can be selected as the synchronized clock S3.

Furthermore, in this embodiment, the flip-flop 2
Although the valid edges of the clock input terminals CK from 01 to 205 are negative edges, they may also be positive edges.

Furthermore, the connection relationship between the delayed clock and the switch is not limited to that shown in FIGS. 4 and 6.

Furthermore, in this embodiment, the synchronous clock is selected based on the delayed clock whose edge is closest in time to the edge of the asynchronous signal S2 applied from the asynchronous signal input terminal 2. The synchronous clock may be selected based on the delayed clock whose edge is temporally earlier and closest to the edge of the asynchronous signal S2, or
The synchronization clock may be selected based on the delayed clock having the temporally closest edge regardless of the context.

Next, still another embodiment of the present invention will be described. FIG. 7 is a circuit diagram of a synchronous clock generation circuit showing a third embodiment of the present invention. As shown in the figure, the reference clock S1 is input from the reference clock input terminal 1.
is input to the delay element 211, and the delayed clock DC1, which is the output of the delay element 211, is input to the delay element 212.The reference clock S1 input from the reference clock input terminal 1 is input to the delay elements 211 to 215 in turn. is given to.

Further, the delayed clock DC1, which is the output of the delay element 211, is connected to the data input terminal D of the flip-flop 201, and the delayed clock DC1, which is the output of the delay element 212, is connected to the data input terminal D of the flip-flop 201.
2 is applied to the data input terminal D of the flip-flop 202, and the delay clocks DC1 to DC5, which are the outputs of the respective delay elements 211 to 215, are applied to the data input terminals D of each of the flip-flops 201 to 205 on a one-to-one basis. There is. Furthermore, the delay clocks DC1 to DC5
is applied to one input terminal group of the clock selection circuit 221.

Further, the asynchronous signal S2 inputted from the asynchronous signal input terminal 2 is input to the flip-flops 201 to 20.
5 is applied to the negative logic clock input terminal CK. Furthermore, a reset signal S4 applied from the reset signal input terminal 4 is applied to the reset input terminals R of the flip-flops 201 to 205. Further, the output signals S201 to S205 from the data output terminals Q of each flip-flop 201 to 205 are outputted to the clock selection circuit 2.
It should be noted that the delay elements after the delay element 215 and the flip-flop 20 provided to the other input terminal group of 21
Flip-flops after 5 are omitted.

Next, the operation of the circuit shown in FIG. 7 will be explained. FIG. 8 is a timing chart showing the operation of the circuit shown in FIG. As shown in the figure, the reference clock S1 is applied to the delay element 2.
11 to 215, delay clocks DC1 to DC5 are generated by being delayed by a predetermined time.

Further, the reset signal S4 from the reset signal input terminal 4 falls to the "L" level, and the reset input terminals R of the flip-flops 201 to 205 become "L".
``When it comes to the level, flip-flops 201 to 205
becomes operational.

Now, as shown in the figure, when a falling trigger occurs in the asynchronous signal S2 from the "H" level to the "L" level, the flip-flops 201 to 205 switch to the asynchronous signal S2 input to the clock input terminal CK. The data at the data input terminal D is taken in at the falling edge of the signal S2. At this time, the delay clocks DC1 and DC2, which are the outputs of the delay elements 211 and 212, are at "L" level, and the delay clocks DC3 and DC2, which are the outputs of the delay elements 213 to 215, are at "L" level.
5 is the “H” level, so the flip-flop 201
The output signals S201 to S205 of the output signals S201 to S205 are as shown in the figure.

The clock selection circuit 221 selects the output signals S201 to S2 of the flip-flops 201 to 205.
05, the delay clock corresponding to the clock that rises earliest temporally, that is, the delayed clock whose edge is temporally closest to the edge of the asynchronous input signal S2 (Fig. 8
In the example, the delayed clock DC3) is detected from among the delayed clocks DC1 to DC5. Next, based on this, a desired delayed clock (in the example of FIG. 8, the delayed clock DC3) is selected from among the delayed clocks DC1 to DC5 and outputted from the synchronized clock output terminal 3 as the synchronized clock S3. Note that details of the clock selection circuit 221 will be described later.

As described above, in the example of FIG.
Even if the trigger inputs of the flip-flops 201 to 205 fluctuate within the range indicated by the broken line in FIG.
The states of 201 to S205 do not change, and the synchronized clock S3 comes out at the same timing. That is, the synchronization accuracy can be approximated to the delay value of one stage of delay elements 211 to 215. In other words, approximately, it can be said that synchronization accuracy=delay value for one stage of delay element. In a semiconductor integrated circuit, the delay value for one stage of delay elements can be set to 1 ns or less, and extremely high synchronization accuracy can be obtained compared to conventional synchronous clock generation circuits.

FIG. 9 shows the clock selection circuit 22 shown in FIG.
1 is a circuit diagram showing an example of the configuration of No. 1. FIG. As shown in the figure,
Output signal S2 of flip-flops 201 to 205 applied to one input terminal group of clock selection circuit 221
01 to S205 are input to the flip-flop output change point detection circuit 301, and the outputs of the flip-flop output change point detection circuit 301 are connected to gate terminals G that control conduction and non-conduction of the switches 311 to 315, respectively. Further, delay clocks DC2 to DC6, which are outputs of delay elements 212 to 216 (delay element 216 is not shown in FIG. 7), are applied to input terminals of switches 311 to 315.
Each output terminal is connected to an input of a multi-input OR circuit 321. Further, the output of the multi-input OR circuit 321 is connected to the synchronous clock output terminal 3.

FIG. 10 is a circuit diagram showing an example of the configuration of a flip-flop output change point detection circuit 301, which is a component of the clock selection circuit 221. As shown in the figure, by inverting one of the output signals S201 to S205 of two adjacent flip-flops and inputting the other to the NAND circuits 501 to 505 without inverting the output signals S201 to S205 of the flip-flops 201 to 205. , one side is “
The outputs S311 to S315 of the NAND circuits are configured to be at the "L" level when the other one is at the "H" level, and to be at the "H" level otherwise.

Next, the clock selection circuit of FIG. 9 and the clock selection circuit of FIG.
The operation of the flip-flop output change point detection circuit will be explained. Flip-flop output change point detection circuit 301
is the output signal S2 of the flip-flops 201 to 205
NAND circuits 501 to 505 in which one input of adjacent output signals is inverted among 01 to S205.
When the levels of the two inputs match the predetermined pattern described above, one of the outputs S311 to S315 is set to "L" level and one of the corresponding switches 311 to 315 is made conductive. It works like that. In the example of FIG. 8, the NAND circuit 502
The output S312 of the switch becomes "L" level, and the corresponding switch 312 becomes conductive. When one of the switches 311 to 315 conducts, the delayed clock DC2 to DC
6 (delayed clock DC3 in the example of FIG. 8) is connected to the multi-input OR circuit 3 through the conductive switch.
21, and is output from the output of the multi-input OR circuit 321 to the synchronous clock output terminal 3 as the synchronous clock S3.

FIG. 11 is a circuit diagram showing another example of the structure of the clock selection circuit shown in FIG. 9. As shown in the figure, the connection relationship between the delayed clock and the switch is different from that of the clock selection circuit shown in FIG. That is, the delay clock DC1~
DC5 is connected to the input terminals of switches 311 to 315, respectively. The rest of the configuration is the same as the clock selection circuit shown in FIG. 9, so the explanation will be omitted.

In the clock selection circuit shown in FIG. 11, the synchronous clock S3 outputted from the synchronous clock output terminal 3 is different from that of the clock selection circuit shown in FIG. 9 under the same timing conditions. That is, for example, when the timing condition is such that the synchronous clock DC2 is selected in FIG. 9, the synchronous clock DC1 is selected in FIG.
In FIG. 9, when the timing condition is such that the synchronous clock DC2 is selected, the synchronous clock DC1 in FIG.
is selected. In this way, the delayed clock output from the synchronous clock output terminal 3 as the synchronous clock S3 is
It can be made to fall. In this manner, by changing the connection relationship between the delayed clock and the switch, a desired delayed clock can be output from the synchronous clock output terminal as the synchronous clock S3.

Note that in the configuration of FIG. 9, the first delay element 2
In the configuration of FIG. 11, the delayed clock DC1 from 11 is not selected as the synchronous clock S3.
The configuration is such that the delayed clock output from the last delay element is not selected as the synchronization clock S3. However, in FIG. 9, if the number of delay elements is prepared so that the reference clock S1 can be delayed by one period or more, the delayed clock D
Since a delayed clock having the same phase as C1 appears after the delayed clock DC5, the delayed clock having the same phase as the delayed clock DC1 can be selected as the synchronous clock S3. Also in FIG. 11, the number of delay elements is set to the reference clock S1.
If it is prepared so that it can be delayed by one cycle or more, a delayed clock that is in phase with the delayed clock output by the last delay element will appear before the delayed clock output by the last delay element, so the delay output by the last delay element will be delayed. A delayed clock that is in phase with the clock can be selected as the synchronous clock S3.

Furthermore, in this embodiment, the flip-flop 20
Although the valid edges of the clock input terminals CK 1 to 205 are negative edges, they may be positive edges.

Furthermore, the connection relationship between the delayed clock and the switch is not limited to that shown in FIGS. 9 and 11.

Furthermore, in this embodiment, the synchronous clock is selected based on the delayed clock whose edge is closest in time to the edge of the asynchronous signal S2 applied from the asynchronous signal input terminal 2. , the synchronous clock may be selected based on the delayed clock whose edge is temporally previous and closest to the edge of the asynchronous signal S2, or the synchronous clock may be selected based on the delayed clock whose edge is temporally closest to the edge of the asynchronous signal S2. You may also select a synchronous clock.

Furthermore, in this embodiment, the reset signal S4 from the reset signal input terminal 4 is input to the flip-flop 20.
However, a set signal input terminal is provided in place of the reset signal input terminal 4, and the set signal from this terminal is applied to the flip-flop 201.
It may be applied to the set input terminals 205 to 205, and the same effects as in the above embodiment can be obtained in this case as well.

[0055]

As described above, according to the first aspect of the invention, in a synchronous clock generation circuit that generates a synchronous clock synchronized with an asynchronous input signal, a plurality of delay elements are connected in series. A delay clock generation circuit generates multiple delayed clocks by sequentially delaying a reference clock using a delay element, and is activated in response to an asynchronous input signal and controls each of the multiple delayed clocks.
A memory circuit consisting of a plurality of memory elements that stores a predetermined value, and a clock that uses the outputs of the plurality of memory elements as a control signal, and has an edge temporally closest to the edge of the asynchronous input signal from among the plurality of delayed clocks. A clock selection circuit is provided that detects the delay clock, selects a desired delay clock from among multiple delay clocks according to the detection result, and outputs it as a synchronization clock, eliminating the need for a high-frequency clock generation circuit and achieving synchronization. This has the effect of providing a highly accurate synchronous clock generation circuit.

According to the second aspect of the invention, in the synchronous clock generation circuit that generates a synchronous clock synchronized with an asynchronous input signal, the synchronous clock generation circuit is configured by connecting a plurality of delay elements in series, and the reference clock is connected to the delay element. A delay clock generation circuit that generates multiple delayed clocks by sequentially delaying them with As a control signal, the one whose edge is temporally closest to the edge of the asynchronous input signal is detected from among multiple delayed clocks, and a desired delayed clock is selected from among the multiple delayed clocks according to the detection result. However, since a clock selection circuit for outputting this as a synchronization clock is provided, a high frequency clock generation circuit is not required and a synchronization clock generation circuit with high synchronization accuracy can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a synchronous clock generation circuit showing a first embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the circuit shown in FIG. 1;

FIG. 3 is a circuit diagram of a synchronous clock generation circuit showing a second embodiment of the invention.

FIG. 4 is a circuit diagram showing a configuration example of the clock selection circuit of FIGS. 1 and 3;

5 is a circuit diagram showing a configuration example of a flip-flop output change point detection circuit which is a component of the clock selection circuit shown in FIG. 4; FIG.

FIG. 6 is a circuit diagram showing another configuration example of the clock selection circuit shown in FIG. 3;

FIG. 7 is a circuit diagram of a synchronous clock generation circuit showing a third embodiment of the invention.

FIG. 8 is a timing chart showing the operation of the circuit in FIG. 7;

9 is a circuit diagram showing a configuration example of the clock selection circuit of FIG. 7; FIG.

10 is a circuit diagram showing a configuration example of a flip-flop output change point detection circuit which is a component of the clock selection circuit of FIG. 9; FIG.

FIG. 11 is a circuit diagram showing another configuration example of the clock selection circuit of FIG. 9;

FIG. 12 is a circuit diagram showing a conventional synchronous clock generation circuit.

13 is a timing chart showing the operation of the circuit shown in FIG. 12. FIG.

[Explanation of symbols]

1 Reference clock input terminal 2 Asynchronous signal input terminal 3 Synchronous clock output terminal 4 Reset signal input terminals 201 to 205 Flip-flops 211 to 215 Delay element 221 Clock selection circuit 301 Flip-flop output change point detection circuit 311
~315 Switch 321 Multi-input OR circuit 401-405 NAND circuit with one input inverted 501-505 NAND circuit

Claims (2)

[Claims] 1. A synchronous clock generation circuit that generates a synchronous clock synchronized with an asynchronous input signal, comprising a plurality of delay elements connected in series, and by sequentially delaying a reference clock with the delay elements. a delayed clock generation circuit that generates a delayed clock; a storage circuit that is activated in response to the asynchronous input signal and that stores a predetermined value under the control of each of the plurality of delay clocks; Using the outputs of the plurality of storage elements as a control signal, one of the plurality of delayed clocks having an edge temporally closest to the edge of the asynchronous input signal is detected, and the plurality of delayed clocks are controlled according to the detection result. A synchronous clock generation circuit comprising: a clock selection circuit that selects a desired delayed clock from among delayed clocks and outputs it as the synchronous clock. 2. A synchronous clock generation circuit that generates a synchronous clock synchronized with an asynchronous input signal, comprising a plurality of delay elements connected in series, and by sequentially delaying a reference clock with the delay elements. a delayed clock generation circuit that generates a delayed clock; a storage circuit including a plurality of storage elements that respectively store the plurality of delayed clocks under the control of the asynchronous input signal; and an output of the plurality of storage elements as a control signal; Among the plurality of delayed clocks, one having an edge temporally closest to an edge of the asynchronous input signal is detected, and a desired delayed clock is selected from among the plurality of delayed clocks according to the detection result. , and a clock selection circuit that outputs this as the synchronous clock.