JPH03282805A - Clock signal switching circuit - Google Patents

Abstract

PURPOSE:To switch and output even clock signals of less period difference without spike generation by detecting that the high level period of the first clock signal is included in that of the second clock signal to synchronize a clock switching signal. CONSTITUTION:When the high level period of a first clock signal CK1 is included in that of a second clock signal CK2, clock signal switching is performed at the time of fall of the first lock signal CK1. A non-inverted output signal (f) of an RS flip flop 8 is made active at the time of fall of the first clock signal CK1, and a non-inverted output signal (clock switching synchronizing signal) (g) of a latch 10 is made active, and the output of a delay circuit 11 and that of a delay circuit 12 are switched by a selector 13. Thus, even two clocks CK1 and CK2 of less period difference are switched and outputted without spike generation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a clock signal switching circuit that selects and outputs one of two clock signals.

[Conventional technology]

FIG. 3 is a circuit diagram of a conventional example of this type of clock signal switching circuit.

The latch 21 uses the first clock signal CKI as a latch signal and latches a second clock signal CK2 having a longer cycle than the first clock signal CKI. The latch 22 is
The inverted output signal of the latch 21 is latched using the inverted signal of the first clock signal CK1 as a latch signal. The latch 23 latches the inverted output signal i of the latch 22 using the first clock signal CKI as a latch signal. The NOR gate 24 inputs the inverted output signal i of the latch 22 and the inverted output signal j of the latch 23, and outputs the signal k. latch 2
5 latches the clock switching signal SEL using the output signal k of the NOR gate 24 as a latch signal. The non-inverted output of latch 25 becomes clock switching synchronization signal l. The selector 26 selects the first clock signal CKI or the second clock signal CK2 according to the clock switching synchronization signal 1 and outputs the clock output signal CKO. For example, when the clock switching synchronization signal 1 is at a high level, the clock The first clock signal CK1 is output as the output signal CKO, and the second clock signal CK2 is output when it is at a low level.

FIG. 4 shows the second clock signal C in the circuit of FIG.
This is a time chart when the period of K2 is sufficiently long (twice or more) compared to the period of the first clock signal CKI.

The output signal of the NOR gate 24 receives the inverted output signal h of the latch 21, the inverted output signal i of the latch 22, the inverted output signal J of the latch 23, the inverted output signal i of the latch 22, and the inverted output signal j of the latch 23. are respectively shown in Figure 4 (3
), (4), (5), and (6), and when the clock switching signal SEL is given as shown in FIG. 4 (7), the clock switching signal SEL is the output signal of the NOR gate 24. The clock switching synchronization signal l becomes as shown in FIG. 4(8). The clock switching synchronization signal 1 becomes a select signal, and while the clock switching synchronization signal 1 is at high level, the first clock signal CKI is output as the clock output signal CKO, and while the clock switching synchronization signal 1 is at low level, the second clock signal CK2 is output. Output.

As described above, the period of the second clock signal CK2 is the first
If the period of the first clock signal CKI is sufficiently long compared to the period of the first clock signal CKI, the first clock signal C
It is possible to select and output KI and the second clock signal GK2.

However, when trying to switch between the first clock signal CK1 and the second clock signal CK2 whose cycle widths have a small difference (within twice) using the circuit shown in Figure 3, a spike occurs in the clock output signal CKO. do. FIG. 5 is a timing chart in this case.

The output signal of the NOR gate 24 receives the inverted output signal h of the latch 21, the inverted output signal i of the latch 22, the inverted output signal j of the latch 23, the inverted output signal i of the latch 22, and the inverted output signal J of the latch 23. are respectively shown in Figure 5 (3
), (4), (5), (6), and the clock switching signal CKO is the same as described above.

In this case, a spike 27 occurs in the clock output signal CKO when switching from the first clock signal CKI to the second clock signal CK2. This spike 2
7 is narrower than the pulse width of the clock signal CKI with the shorter period, which causes malfunction in the circuit using the clock output signal CKO of this circuit.

[Problem to be Solved by the Invention 1] The conventional clock signal switching circuit described above has the drawback of generating spikes when switching and outputting two clock signals whose period widths are not much different (within 2 times). .

An object of the present invention is to provide a clock switching circuit that can switch and output two clock signals with a small period difference without generating spikes.

[Means to solve the problem]

In the clock signal switching circuit of the present invention, the first logic level period of the first clock signal is included in the second logic level period of the second clock signal, which has a longer cycle than the first clock signal. means for detecting the clock switching synchronization signal to generate a detection signal; means for synchronizing the clock switching signal with the detection signal to generate a clock switching synchronization signal; and means for selecting and outputting.

[Function] High level (or low level) of the first clock signal
Since the clock switching synchronization signal is output by detecting that the period is included in the high level (the master is low level) period of the second clock signal, no spike occurs when the clock signal is switched.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a clock switching circuit according to an embodiment of the present invention.

The rising edge detection circuit 1 detects the rising edge of the first clock signal CKI and outputs an active high pulse. The falling edge detection circuit 2 receives the first clock signal C.
It detects the falling edge of KI and outputs an active high pulse. AND gate 3 is the rising edge detection circuit 1
and a second clock signal CK2 having a cycle width longer than that of the first clock signal CKI.
Output. AND gate 4 is the falling edge detection circuit 2
and the second clock signal CK2, and outputs the signal S. NOR gate 5 receives first clock signal CKI
and the output signal S of the AND gate 4 are input, and a signal C is output. The RS flip-flop 6 uses the output signal a of the AND gate 3 as an S input, the output signal C of the NOR gate 5 as an R input, and outputs a non-inverted output d. AND gate 7 is AN
The output signal S of the D gate 4 is inputted with the non-inverted output d of the RS flip-flop 6, and a signal e is output. The RS flip-flop 8 receives the output signal e of the AND gate 7 as its S input, and receives the first clock signal CK1 as its R input. The non-inverted output f of the RS flip-flop 8 is the first clock signal CK.
This is a detection signal when the high level period of I is included in the high level period of the second clock signal CK2.

The latch 9 latches the clock switching signal SEL using the inverted output of the RS flip-flop 8 as a latch signal. The latch 10 latches the non-inverted output of the latch 9 using the non-inverted output f of the RS flip-flop 8 as a latch signal. The non-inverted output g of latch 10 becomes the clock switching synchronization signal. The first clock signal CKI is supplied to the delay circuit 11
The second clock signal CK2 is input to the delay circuit 12. The selector 13 is the second latch 1o
The output signal of the delay circuit 11 by the non-inverted output g of
The output signal of the delay circuit 12 is switched and outputted as a clock output signal CKO.

FIG. 2 is a timing chart of the circuit of FIG.

Output a of AND gate 3, output S of AND gate 4, N
The output c of the OR gate 5, the non-inverting output d of the RS flip-flop 6, and the output e% of the AND gate 7, the non-inverting output f of the RS flip-flop 8, are as shown in FIG. 2 (3), respectively.
(4) , (5) , (6) , (7) , (
The timing will be similar to 8). Clock switching signal SE
When L is inputted as shown in FIG. 2, it is synchronized by the non-inverted output f of the RS flip-flop 8, and the non-inverted output g of the latch 10 becomes the clock switching synchronization signal. When this clock switching synchronization signal is at a high level, the clock output signal CKO is the output of the delay circuit 11, that is, the first
When the clock signal CK1 is output and is at low level, the output of the delay circuit 12, that is, the second clock signal G
K2 is output. No spikes occur in the clock output signal CKO.

In the clock signal switching circuit of this embodiment, the high level period of the first clock signal CK1 is the period of the second clock signal CK1.
The clock signal is switched at the falling edge of the first clock signal CKI during the second high level period. At the falling edge of the first clock signal CKI, the non-inverted output signal f of the RS flip-flop 8 becomes active, and therefore the non-inverted output signal f of the latch 10 (
The clock switching synchronization signal)g becomes active, and the selector 13 selects the output of the delay circuit 11 and the output of the delay circuit 12.
Switch between the output and The delay values of the delay circuit 11 and the delay circuit 12 only need to be set for a period from the falling point of the first clock signal CKI until the switching operation of the selector 13 is completed.

In FIG. 1, a rising edge detection circuit 1 and a falling edge detection circuit are used as circuits for detecting that the high level period of the first clock signal CKI is included in the high level period of the second clock signal CK2. 2. Although an RS flip-flop 6.8 or the like is used, other circuit configurations can also be used.

〔Effect of the invention〕

As explained above, the present invention provides a clock signal switching circuit that switches between a first clock signal and a second clock signal whose period is longer than that of the first clock signal. Low level) period is the high level (or low level) of the second clock signal
By detecting that it is included in the period and synchronizing the clock switching signal, it is possible to switch and output even two clock signals with a small difference in period width without generating spikes. be.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a clock signal switching circuit according to an embodiment of the present invention, FIG. 2 is a timing chart of the circuit of FIG. 1, FIG. 3 is a block diagram of a conventional example of a clock signal switching circuit, and FIG. 4 is an operation timing chart of the conventional example shown in FIG. 3 when the difference in the period width of the two clock signals to be switched is sufficiently large (more than double), and FIG. 3rd case (less than 2 times)
3 is an operation timing chart of the conventional example shown in FIG. 1... Rising edge detection circuit, 2...
Falling edge detection circuit, 3, 4.7...-AN
D gate, 5 - NOR gate, 6
．． 8-・・・・・・RS flip-flop, 9.1
0...Latch, 11,'12...Delay circuit, 13...
......Selector, 21.22.23.25-
・・・・・・Latch, 24・・・・・・・・・・・・NO
R gate, 26------...Selector, 2
7---------Spike, CKI...
...First clock signal, CK 2-...Second clock signal, SEL...Clock switching signal,
CKO...Clock output signal.

Claims (1)

[Claims] 1. A clock signal switching circuit that switches and outputs a first clock signal and a second clock signal having a longer period than the first clock signal, the circuit comprising: means for generating a detection signal by detecting that the first logic level period is included in the first logic level period of the second clock signal; and clock switching synchronization by synchronizing the clock switching signal with the detection signal. 1. A clock signal switching circuit comprising means for generating a synchronization signal, and means for selecting and outputting a first clock signal or a second clock signal based on the clock switching synchronization signal.