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JPS61224344A - Package for high-frequency integrated device - Google Patents

Package for high-frequency integrated device

Info

Publication number
JPS61224344A
JPS61224344A JP60064672A JP6467285A JPS61224344A JP S61224344 A JPS61224344 A JP S61224344A JP 60064672 A JP60064672 A JP 60064672A JP 6467285 A JP6467285 A JP 6467285A JP S61224344 A JPS61224344 A JP S61224344A
Authority
JP
Japan
Prior art keywords
package
circuit board
main part
integrated device
frequency integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60064672A
Other languages
Japanese (ja)
Inventor
Yoshimitsu Yamazoe
山添　良光
Shinichi Iguchi
井口　信一
Akira Otsuka
昭 大塚
Mitsuaki Nishie
光昭 西江
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP60064672A priority Critical patent/JPS61224344A/en
Publication of JPS61224344A publication Critical patent/JPS61224344A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32153—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/32175—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
    • H01L2224/32188—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic the layer connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4823—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a pin of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 （産業上の利用分野） 本発明は高周波集積デバイス用パッケージに関し、より
特別にはＩｎＰ、ＧａＡｓ等化合物半導体を用いた高周
波集積デバイス用のパッケージの改良に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a package for a high frequency integrated device, and more particularly to an improvement of a package for a high frequency integrated device using a compound semiconductor such as InP or GaAs.

（従来の技術） 従来、高周波集積デバイス用のパッケージとして、第３
図（ａ）　、　（ｄに示すように、）ξツケージ主要部
（ステム）１上に、アルミナ、ベリリア等のセラミック
やエポキシグラス等の高周波用の絶縁性基板の上に回路
網を形成した回路基板３を貼り付け、これをパッケージ
主要部１上に一体形成したステー：）５上に装着したＩ
ｎＰやＧａＡｓ等の化合物半導体よりなる素子７，９お
よびガラス１１封止したリード線１３にワイヤ１５接続
し、該ノツケージ主要部上をキャップ（図示せず）にて
カバーしてなる構造のパッケージは公知である。(Prior art) Conventionally, as a package for high frequency integrated devices, the third
As shown in Figures (a) and (d), a circuit in which a circuit network is formed on the main part (stem) 1 of the ξ cage and on an insulating substrate for high frequency use such as ceramic such as alumina or beryllia or epoxy glass. I attached the board 3 and mounted on the stay :) 5 which was integrally formed on the main part 1 of the package.
A package has a structure in which wires 15 are connected to elements 7 and 9 made of compound semiconductors such as nP or GaAs, lead wires 13 sealed with glass 11, and the main part of the cage is covered with a cap (not shown). It is publicly known.

（発明が解決しようとする問題点） しかしながら、上記従来のパッケージ構造では、回路基
板３が単にパッケージ主要部１上面に貼り付ける構造と
なっているため、回路基板の装着に際しては該回路基板
３とステージ５との間の精密な位置合わせを行うべく特
別な位置合わせ治具を用いた作業を必要とし、組立てが
面倒であった。(Problems to be Solved by the Invention) However, in the conventional package structure described above, the circuit board 3 is simply attached to the top surface of the main part 1 of the package. In order to perform precise positioning with the stage 5, it was necessary to use a special positioning jig, and assembly was troublesome.

すなわち、組立中に接合用の樹脂やロウ剤が溶解した時
点で回路基板が移動したり、該移動に伴って接合剤が回
路基板の側面や上面へ回り込むなどして位置ずれや短絡
不良を引き起し易い欠点がある。高同波回路において位
置ずれが生じた場合には、余分な寄生容量や寄生インダ
クタンス等の発生を伴うため、設計された回路の整合条
件がくずれてしまう。このため、高周波信号の反射損や
半導体素子の効率低下を引き起し、はなはだしい場合に
はこれらの損失電力により半導体素子が破壊されること
Ｋもなる。In other words, the circuit board may move when the bonding resin or brazing agent melts during assembly, or the bonding agent may wrap around the sides or top of the circuit board due to such movement, causing misalignment or short circuits. There are drawbacks that can easily occur. When a positional shift occurs in a high-frequency same-wave circuit, extra parasitic capacitance, parasitic inductance, etc. are generated, and the matching conditions of the designed circuit are disrupted. This causes a reflection loss of the high frequency signal and a reduction in the efficiency of the semiconductor element, and in extreme cases, the semiconductor element may be destroyed by these power losses.

（゛問題点を解決するための手段） 本発明は上記従来の欠点を除去すべくなされ、たもので
あって、このため本発明はパッケージ主要部上に絶縁性
回路基板を装着してなる高周波集積デバイス用のパッケ
ージにおいて、パッケージ主要部の上面に予め回路基板
を埋設するための凹部を形成しておき、該凹部内に回路
基板を嵌込み接合することにより回路基板を装着するこ
とを特徴とする。(Means for Solving the Problems) The present invention has been made to eliminate the above-mentioned conventional drawbacks, and for this reason, the present invention provides a high frequency In a package for an integrated device, a recess for embedding a circuit board is formed in advance on the upper surface of the main part of the package, and the circuit board is mounted by fitting and bonding the circuit board into the recess. do.

（作　用） パッケージ主要部には予め凹部が形成されてい、るため
、所定寸法の回路基板を嵌込めばそのまま位置合わせが
完了する。また、パッケージ主要部に形成された凹部は
回路基板を全周囲より固定するため組立治具としての機
能を果す。従って組立時の精密な位置調整が不要となる
。しかも凹部の側壁部分により接合剤の流れが押えられ
るため接合材料、例えば樹脂やロウ剤が回路基板の表面
へ回り込むことも防とできる。　　　　。(Function) Since a recess is pre-formed in the main part of the package, alignment is completed as soon as a circuit board of a predetermined size is inserted. Furthermore, the recess formed in the main part of the package functions as an assembly jig to secure the circuit board from all around. Therefore, precise position adjustment during assembly becomes unnecessary. Moreover, since the flow of the bonding agent is suppressed by the side wall portion of the recess, it is possible to prevent the bonding material, such as resin or brazing agent, from going around to the surface of the circuit board. .

（実施例） 以下、本発明の好適な実施例を添附図に沿って説明する
。第１図（ａ）、　（ｂ）は本発明の一実施例を示す。(Embodiments) Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. FIGS. 1(a) and 1(b) show an embodiment of the present invention.

該実施例では、まずパッケージ主要部１を銅−タングス
テン合金により作製した。該合金材料はタングステンに
銅を重量比で１８％の割合で含有させ、溶浸法によって
形成した。この合金の線膨張率は６．８　Ｘｌ０−’６
ｃ＋ｎ／ｃｒＩＬ’ｃとＧａＡ、、の線膨張率とほぼ一
致させてあり、また熱伝導率は０．６５　ｃａ３；Ｐａ
ｄｅｇと従来一般使用のコバールと比較して約１０倍で
あった。次いで、この合金母材を研削加工により第１図
のパッケージ主要部１の形状に形成した。In this example, first, the main part 1 of the package was made of a copper-tungsten alloy. The alloy material contained tungsten and copper at a weight ratio of 18%, and was formed by an infiltration method. The coefficient of linear expansion of this alloy is 6.8 Xl0-'6
The linear expansion coefficient of c+n/crIL'c and GaA is almost the same, and the thermal conductivity is 0.65 ca3; Pa.
deg was approximately 10 times higher than that of Kovar, which has been commonly used. Next, this alloy base material was formed into the shape of the main part 1 of the package shown in FIG. 1 by grinding.

すなわち、半導体素子７，９を装着するステージ５と、
回路基板３を埋設する凹部ｌＯと、リード線１３を挿通
する穴とを設けた。該主要部に鉄ニツケルメッキを約２
μｍはどこした後、融着用ガラス１１を介して鉄ニツケ
ル合金からなるリード線１３を融着した。さらに金メッ
キを約１μｍはどこし、これで主要部１を完成した〇 次に、アルミナセラミックの回路基板３の裏面全体をメ
タライズし、表面には増幅回路のパターン４をスクリー
ン印刷法により形成した。このように形成した回路基板
３を主要部１の凹部１０にロウ付けによって接合した。That is, a stage 5 on which semiconductor elements 7 and 9 are mounted,
A recess lO in which the circuit board 3 is buried and a hole through which the lead wire 13 is inserted are provided. Approximately 2 pieces of iron-nickel plating is applied to the main part.
After adjusting the diameter of μm, a lead wire 13 made of an iron-nickel alloy was fused through the fusion glass 11. Further, gold plating was applied to a thickness of about 1 μm to complete the main part 1.Next, the entire back surface of the alumina ceramic circuit board 3 was metallized, and an amplifier circuit pattern 4 was formed on the surface by screen printing. The circuit board 3 thus formed was joined to the recess 10 of the main portion 1 by brazing.

回路基板３の位置合わせは予め、Ｒツケージ主要部１に
形成された凹部ｌＯに嵌込むだけであるので非常に簡単
であった。また、回路基板３の位置ずれや接合剤の回り
込みなどの現象は見られなかった。The positioning of the circuit board 3 was very simple since it was only necessary to fit it into the recess 10 formed in the main part 1 of the R-shaped cage in advance. Furthermore, no phenomena such as misalignment of the circuit board 3 or wraparound of the bonding agent were observed.

この後、ＧａＡｓからなる高周波増幅用のＦＥＴチップ
７．９をステージ５上に装着し、金のワイヤ１５を用い
で回路基板３上の所定の接合ノツｒとの結線および！７
−　）’［１３との接続を行った。このとき、回路基板
３とパッケージ主要部１との位置合わせの精度が高いた
め、ワイヤ１５の長さの設計値との差は関μｍ以内であ
り、寄生容量および寄生インダクタンスを減少させるこ
とができた。次に、回路基板３上にチップ抵抗、チップ
容量を乗せてはんだ付けすることにより回路網を完成し
た。Thereafter, a FET chip 7.9 for high frequency amplification made of GaAs is mounted on the stage 5, and connected to a predetermined bonding hole r on the circuit board 3 using a gold wire 15. 7
- )' [Connected with 13. At this time, since the alignment between the circuit board 3 and the main part 1 of the package is highly accurate, the difference between the length of the wire 15 and the designed length is within 10 μm, and the parasitic capacitance and inductance can be reduced. Ta. Next, a chip resistor and a chip capacitor were placed on the circuit board 3 and soldered to complete the circuit network.

最後に、パッケージ主要部１上にキャップ（図示せず）
を取付けることにより、高周波集積ジノζイスの一つで
ある高周波増幅器を完成した。Finally, a cap (not shown) is placed on the main part 1 of the package.
By installing this, we completed a high-frequency amplifier, which is one of the high-frequency integrated technology chairs.

このようにして作製された増幅器は、部品配置並に配線
の精度が改良されたことにより容量やインダクタンスの
寄生成分が減少した結果、設計通りのインピーダンス整
合を容易に実現することができた。このため、従来必要
であったデバイス作製後のトリミング作業を大巾に短縮
することができ、また回路効率および雑音特性を改善す
ることもできた。In the amplifier manufactured in this way, the parasitic components of capacitance and inductance were reduced by improving the precision of component placement and wiring, and as a result, it was possible to easily achieve impedance matching as designed. Therefore, the trimming work required in the past after device fabrication can be greatly shortened, and circuit efficiency and noise characteristics can also be improved.

また、ノッケージ主要部ＩＫ銅−タングステン合金を用
いることＫよって、Ｇ？！ＬＡｓ等の半導体素子７，９
とステージ５との線膨張率差による応力の発生を阻止す
ることができ、また放熱特性を改善することができるた
め、電力容量を増大することができる。本発明の一実施
例によれば、従来半導体チップ当りの消費電力の上限が
１００ｍｗ程であったものが１５０ｍｖｒ程度まで耐え
られるようになった。また、素子寿命は加速劣化試験デ
ータを用いて推定したところ、従来の１０倍以上の寿命
が得られることがわかった。なお、パッケージ主要部１
の材料としては、上記材料の他にタングステン、モリブ
デンまたはタングステン・モリブデン合金に均一に銅を
含有させた合金であって、４、ＯＸｌ０−　Ｌｌａｎ／
ｃＩｒＬ２℃乃至７．ＯＸｌ０−　’ｃｍ／ｃｗｔ　’
Ｃの線膨張率をもつ合金を使用することによっても同様
な効果を得ることができる。Also, since the main part of the knockage is made of IK copper-tungsten alloy, G? ! Semiconductor elements 7, 9 such as LAs
It is possible to prevent the generation of stress due to the difference in coefficient of linear expansion between the stage 5 and the stage 5, and it is also possible to improve the heat dissipation characteristics, so that the power capacity can be increased. According to an embodiment of the present invention, the upper limit of power consumption per semiconductor chip, which was conventionally about 100 mW, can now withstand up to about 150 mvr. Furthermore, when the element life was estimated using accelerated deterioration test data, it was found that the life of the element was ten times longer than that of the conventional device. In addition, the main part of the package 1
In addition to the above materials, the material may be tungsten, molybdenum, or an alloy of tungsten-molybdenum alloy containing copper uniformly, such as 4, OXl0-Llan/
cIrL2°C to 7. OXl0-'cm/cwt'
A similar effect can be obtained by using an alloy having a coefficient of linear expansion of C.

第２図は本発明の他の実施例を示すもので、該★施例の
ものは先の実施例のように回路基板３をパッケージ主要
部１内に完全に埋設させず、回路基板３０表面がＧａＡ
ｓ等からなるＦＥＴチップ７゜９の表面とほぼ同一高さ
となるように、回路基板３をパッケージ主要部１内に部
分的に埋設したものである。本実施例のものは先の実施
例のものと同様の効果が得られるばかりではなく、結線
用ワイヤ１５の長さを第１図の場合よりさらに短縮する
ことができるため、容量、インダクタンスの寄生成分を
いっそう減少させることができる。FIG. 2 shows another embodiment of the present invention, in which the circuit board 3 is not completely embedded in the main part 1 of the package as in the previous embodiment, but the surface of the circuit board 30 is is GaA
The circuit board 3 is partially buried within the main part 1 of the package so that it is approximately at the same height as the surface of the FET chip 7. In this embodiment, not only the same effect as the previous embodiment can be obtained, but also the length of the connecting wire 15 can be further shortened than in the case of FIG. components can be further reduced.

（発明の効果） 以上のように、本発明によれば高周波集積デバイス用パ
ッケージにおいて、回路基板の高精度り位置合わせを容
易に行うことができ、このためデバイスの設計および組
立作業の能率を向上させることができ、しかも出来上っ
たデバイスの効率や回路性能を改善することができる。(Effects of the Invention) As described above, according to the present invention, it is possible to easily align the circuit board with high precision in a package for a high-frequency integrated device, thereby improving the efficiency of device design and assembly work. Moreover, the efficiency and circuit performance of the resulting device can be improved.

それ故、高周波を扱う通信機器や測定機器等において装
置の高性能化、小型化、低価格化を実現することができ
る。Therefore, it is possible to realize higher performance, smaller size, and lower cost of communication equipment, measuring equipment, etc. that handle high frequencies.

【図面の簡単な説明】[Brief explanation of drawings]

第１図（ａ）および（ｂ）はそれぞれ本発明の一実施例
を示す上面図および中央断面図、第２図は本発明の他の
実施例を示す中央断面図、第３図（ａ）および（１：）
はそれぞれ従来の高周波集積デバイス用ノッヶージの構
造を示す上面図および中央断面図である。 １・・・パッケージ主要部、３・・・回路基板７．９・
・・半導体素子、　　１０・・・凹部第１図 第２図 １　：パッケージ主要部 ３　；旧跨纂」艮 ７９：半導体米子 曾 １０：凹卸1(a) and (b) are a top view and a central sectional view showing one embodiment of the present invention, respectively, FIG. 2 is a central sectional view showing another embodiment of the present invention, and FIG. 3(a) and (1:)
1A and 1B are a top view and a central cross-sectional view, respectively, showing the structure of a conventional notch for a high-frequency integrated device. 1...Package main part, 3...Circuit board 7.9.
...Semiconductor element, 10...Recessed part Fig. 1 Fig. 2 Fig. 1: Main part of package 3;

Claims (5)

【特許請求の範囲】[Claims] （１）パッケージ主要部上に絶縁性回路基板を装着して
なる高周波集積デバイス用のパッケージにおいて、パッ
ケージ主要部の上面に予め回路基板を埋設するための凹
部を形成しておき、該凹部内に回路基板を嵌込み接合す
ることにより回路基板を装着することを特徴とする高周
波集積デバイス用パッケージ。(1) In a package for a high-frequency integrated device in which an insulating circuit board is mounted on the main part of the package, a recess for embedding the circuit board is formed in advance on the upper surface of the main part of the package, and the recess is inserted into the recess. A high-frequency integrated device package characterized in that a circuit board is attached by fitting and bonding the circuit board. （２）前記回路基板はパッケージ主要部に完全に埋設さ
れてなる特許請求の範囲第１項の高周波集積デバイス用
パッケージ。(2) The package for a high frequency integrated device according to claim 1, wherein the circuit board is completely embedded in the main part of the package. （３）前記回路基板はパッケージ主要部に部分的に埋設
されてなる特許請求の範囲第１項の高周波集積デバイス
用パッケージ。(3) The package for a high frequency integrated device according to claim 1, wherein the circuit board is partially embedded in the main part of the package. （４）前記パッケージ主要部が導電性材料よりなる特許
請求の範囲第１項乃至第３項のいずれかによる高周波集
積デバイス用パッケージ。(4) A package for a high frequency integrated device according to any one of claims 1 to 3, wherein the main part of the package is made of a conductive material. （５）前記導電性材料がタングステン、モリブデンまた
はタングステン・モリブデン合金に均一に銅を含有させ
た合金であつて、かつ４．０×１０＾−＾６ｃｍ／ｃｍ
℃乃至７．０×１０＾−＾６ｃｍ／ｃｍ℃の線膨張率を
もつ合金よりなる特許請求の範囲第４項の高周波集積デ
バイス用パッケージ。(5) The conductive material is tungsten, molybdenum, or a tungsten-molybdenum alloy containing copper uniformly, and the conductive material is 4.0 x 10^-^6 cm/cm.
The package for a high frequency integrated device according to claim 4, which is made of an alloy having a linear expansion coefficient of 7.0 x 10^-^6 cm/cm °C.
JP60064672A 1985-03-28 1985-03-28 Package for high-frequency integrated device Pending JPS61224344A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60064672A JPS61224344A (en) 1985-03-28 1985-03-28 Package for high-frequency integrated device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60064672A JPS61224344A (en) 1985-03-28 1985-03-28 Package for high-frequency integrated device

Publications (1)

Publication Number Publication Date
JPS61224344A true JPS61224344A (en) 1986-10-06

Family

ID=13264901

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60064672A Pending JPS61224344A (en) 1985-03-28 1985-03-28 Package for high-frequency integrated device

Country Status (1)

Country Link
JP (1) JPS61224344A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994022168A1 (en) * 1993-03-19 1994-09-29 Olin Corporation Ball grid array electronic package
EP1357591A2 (en) * 2002-04-22 2003-10-29 Alcatel Method of mounting electrical components on a base plate in a radio frequency terminal unit
US9668338B2 (en) 2013-03-27 2017-05-30 Panasonic Intellectual Property Management Co., Ltd. Semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994022168A1 (en) * 1993-03-19 1994-09-29 Olin Corporation Ball grid array electronic package
US6262477B1 (en) * 1993-03-19 2001-07-17 Advanced Interconnect Technologies Ball grid array electronic package
EP1357591A2 (en) * 2002-04-22 2003-10-29 Alcatel Method of mounting electrical components on a base plate in a radio frequency terminal unit
EP1357591A3 (en) * 2002-04-22 2012-03-07 Alcatel Lucent Method of mounting electrical components on a base plate in a radio frequency terminal unit
US9668338B2 (en) 2013-03-27 2017-05-30 Panasonic Intellectual Property Management Co., Ltd. Semiconductor device

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