JP7427927B2 - semiconductor equipment - Google Patents

Description

The present invention relates to a semiconductor device (semiconductor module) equipped with a power semiconductor element and the like.

A conventional general semiconductor module has a semiconductor chip mounted on one side of a ceramic insulating substrate, and is internally wired by wire bonding, ribbon bonding, or lead frame connection (see FIG. 15 of Patent Document 1). The ceramic insulating substrate is mounted on a metal base with a heat diffusion function, and is covered with a mainly resin case.The inside of the case is filled with gel to improve insulation. Although FIG. 15 of Patent Document 1 schematically shows one semiconductor chip, a plurality of semiconductor chips may be mounted in parallel. Although FIG. 15 of Patent Document 1 only shows one circuit, if necessary, a so-called 2-in-1 configuration containing semiconductor elements for two circuits, or a 6-in-1 configuration containing semiconductor elements for six circuits may be used. etc.

On the other hand, among the semiconductors constituting the semiconductor chip mounted on _the semiconductor device _shown in FIG. Bandgap semiconductors have characteristics such as high speed operation, low loss, and high heat resistance compared to silicon (Si). However, wide bandgap semiconductors are generally small because they have many crystal defects and increasing the size of the chip lowers the yield and increases the cost. For this reason, wide bandgap semiconductors have small connection pads, making it difficult to perform ribbon bonding, lead frames, or even thick wire bonding, which necessitates the use of thin wires that are not commensurate with the switching current (rated current).

In some cases, manufacturing costs are increased to increase the size of wide bandgap semiconductor chips, ensure pad size, and perform ribbon bonding or lead frame connections. However, when the connection area is increased and power cycles or heat cycles are applied over a wide temperature range by taking advantage of its high heat resistance, the difference in thermal expansion between the chip and wiring material increases, causing chip electrodes, solder, etc. Cracks are likely to occur at the connections. Therefore, even if the chip is made larger, it cannot be used in a wider temperature range than Si, that is, at high temperatures, and it may still be difficult to take advantage of its original performance. Therefore, there is an example in which a large number of small chips are aggregated and minute pins are connected to the pads of the semiconductor chips, as shown in Patent Document 1.

Patent Document 1 discloses a plurality of conductive pattern members on which a plurality of power semiconductor chips are mounted, and a plurality of rod-shaped conductive connection members that are connected to the power semiconductor chips and the conductive pattern members, respectively, on a surface facing the conductive pattern members. A semiconductor device including a printed circuit board is described. Patent Document 2 discloses an insulating substrate, a metal block fixed to the insulating substrate, a plurality of semiconductor elements using a wide bandgap semiconductor fixed to the metal block, and a plurality of implant pins fixed to the semiconductor element. , a semiconductor device is described that includes a printed circuit board fixed to an implant pin and disposed facing a semiconductor element, and a sealing material disposed between the semiconductor element and the printed circuit board. Furthermore, in Patent Document 3, a first common main power supply board is electrically connected to a first main electrode of a plurality of semiconductor elements, and a second common main power supply board is electrically connected to a second main electrode of a plurality of semiconductor elements. However, a press-contact type semiconductor device is described in which a plurality of semiconductor elements are housed in a press-contact state. Patent Document 4 describes an output electrode connection body in which a plurality of semiconductor elements are connected in parallel, a plurality of output electrodes of the semiconductor elements are connected to each other, and a common electrode connection body in which a plurality of common electrodes of the semiconductor elements are connected to each other. A semiconductor integrated circuit comprising the following is described. Patent Document 5 discloses a flat semiconductor device including first and second electrode conductors connected to first and second main circuit electrodes of a semiconductor device, and in which the semiconductor device is a combination of a plurality of semiconductor elements. The equipment is described. Non-Patent Document 1 describes a power module in which a power chip is mounted on a heat dissipation board made by bonding a thick copper plate to a ceramic board, and the power chip is connected to the power board with copper pins.

International Publication No. 2014/061211 Japanese Patent Application Publication No. 2012-191010 Japanese Patent Application Publication No. 2001-298152 Japanese Patent Application Publication No. 6-349845 Japanese Unexamined Patent Publication No. 1-122146

Norihiro Nashida, Yuichiro Hinata, and Masashi Horio, “All-SiC Module Technology,” Fuji Electric Technical Report, 2012, vol. 85, no. 6, p. 403-407

The configuration shown in FIG. 15 of Patent Document 1 is such that the semiconductor module manufacturer combines semiconductor chips to achieve the required capacity and circuit configuration, performs connections such as wire bonding, and exposes the terminals to the outside of the package. , the user does not need to handle the minute semiconductor chip itself, and only needs to mechanically attach wiring such as bus bars to the terminals of the package. However, since the semiconductor device shown in FIG. 15 of Patent Document 1 is manufactured for general purpose, the volume is overwhelmingly large compared to the size of the semiconductor chip itself, and the internal wiring becomes long.

On the other hand, in order to respond to the recent appearance of wide bandgap semiconductors and high-speed switching that takes advantage of their characteristics, there is a need to shorten wiring with the aim of lowering inductance. Furthermore, with the spread of electric vehicles and the like, there is a trend toward miniaturization of devices such as inverters. For this reason, there are an increasing number of cases in which modules dedicated to wide bandgap semiconductors are assembled without using general-purpose semiconductor modules. , the trend is for high-density packaging on the user side to shorten wiring and downsize the entire device.

However, as mentioned above, small chips such as semiconductor chips using wide bandgap semiconductors have small connection pads, and are not suitable for users who build dedicated modules with general Si chips or general users who assemble electronic components. Therefore, there is a problem that it is difficult to perform wiring freely.

In view of the above-mentioned problems, an object of the present invention is to provide a semiconductor device that can realize a chip-sized package that is easy to handle while allowing the same level of integration as a combination of individual semiconductor chips.

One aspect of the present invention provides (a) a plurality of semiconductor chips each having a first main electrode, a second main electrode, and a control electrode on mutually opposing main surfaces; (c) a printed circuit board having one main surface opposite to one main surface of the first common electrode; and (d) the other main surface of the printed circuit board. (e) a second common electrode having one main surface facing the main surface; and (e) sealing a plurality of semiconductor chips and a printed circuit board, and the other main surface of the second common electrode and the other of the first common electrode. (f) a plurality of control pins inserted into the printed circuit board, one end of which is connected to each control electrode of the plurality of semiconductor chips, and the other end of which is spaced apart from the second common electrode; (g) a plurality of main current pins inserted into the printed circuit board, one end of which is connected to the second main electrode of each of the plurality of semiconductor chips, and the other end of which is connected to the second common electrode; and (h) inserted into the printed circuit board. and an external connection pin whose one end is electrically connected to the plurality of control pins via the printed circuit board and whose other end is exposed from the sealing member.

According to the present invention, it is possible to provide a semiconductor device that can achieve the same level of integration as a combination of individual semiconductor chips, and yet can realize a chip size package that is easy to handle.

1 is a perspective view of a semiconductor device according to an embodiment of the present invention. FIG. 3 is another perspective view of the semiconductor device according to the embodiment of the present invention. 1 is a perspective view of an internal structure of a semiconductor device according to an embodiment of the present invention. FIG. 1 is an exploded perspective view of the internal structure of a semiconductor device according to an embodiment of the present invention. FIG. 3 is another exploded perspective view of the internal structure of the semiconductor device according to the embodiment of the present invention. 1 is a side view of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a plan view of a first common electrode and a semiconductor chip of a semiconductor device according to an embodiment of the present invention. 1 is a plan view of a printed circuit board of a semiconductor device according to an embodiment of the present invention, with wiring layers omitted; FIG. 1 is a plan view of a printed circuit board of a semiconductor device according to an embodiment of the present invention. FIG. 3 is a plan view of a second common electrode of a semiconductor device according to an embodiment of the present invention. 1 is a side view of an application example of a semiconductor device according to an embodiment of the present invention. FIG. 3 is a cross-sectional view of a semiconductor device according to a first comparative example. FIG. 3 is a cross-sectional view of a semiconductor device according to a second comparative example. FIG. 7 is a side view of a semiconductor device according to a first modification of the embodiment of the present invention. FIG. 7 is a side view of a semiconductor device according to a second modification of the embodiment of the present invention. FIG. 7 is a plan view of a second common electrode of a semiconductor device according to a third modification of the embodiment of the present invention. 17 is a sectional view taken along the line AA in FIG. 16. FIG.

Embodiments will be described below with reference to the drawings. In the description of the drawings referred to in the following description, the same or similar parts are denoted by the same or similar symbols. However, it should be noted that the drawings are schematic and the relationship between thickness and planar dimensions, the ratio of the thickness of each layer, etc. are different from reality. Therefore, the specific thickness and dimensions should be determined with reference to the following explanation. Furthermore, it goes without saying that the drawings include portions with different dimensional relationships and ratios.

In addition, in this specification, the "first main electrode" of a semiconductor chip (semiconductor element) refers to a source electrode or a drain electrode when the semiconductor chip is a field effect transistor (FET) or a static induction transistor (SIT). means an electrode into which the main current flows or flows out. The "first main electrode" of a semiconductor chip means an electrode through which a main current flows into or out of the semiconductor chip. For example, when the semiconductor chip is an insulated gate bipolar transistor (IGBT), the "first main electrode" corresponds to an electrode that is either an emitter electrode or a collector electrode. When the semiconductor chip is a static induction (SI) thyristor or a gate turn-off (GTO) thyristor, the "first main electrode" means an electrode that becomes either an anode electrode or a cathode electrode. Moreover, the "second main electrode" of a semiconductor chip means an electrode that becomes either a source electrode or a drain electrode, but does not become the first main electrode, if the semiconductor chip is an FET or SIT. In an IGBT, a "second main electrode" means an electrode that does not become the first main electrode but becomes either an emitter electrode or a collector electrode. In an SI thyristor or a GTO thyristor, the "second main electrode" means an electrode that does not become the first main electrode but becomes either an anode electrode or a cathode electrode. In this way, if the "first main electrode" of the semiconductor chip is the source electrode, the "second main electrode" means the drain electrode. If the "first main electrode" of a semiconductor chip is an emitter electrode, the "second main electrode" means a collector electrode. If the "first main electrode" of a semiconductor chip is an anode electrode, the "second main electrode" means a cathode electrode. In the case of a semiconductor chip with a symmetrical structure such as a MISFET, the functions of the "first main electrode" and "second main electrode" may be interchangeable by exchanging the bias relationship.

<Configuration of semiconductor device>
As shown in FIG. 1, the semiconductor device (semiconductor module) according to the embodiment of the present invention has a substantially rectangular parallelepiped shape entirely covered with a sealing member 10. The second common electrode 9 and the external connection pin 8 are exposed from the sealing member 10 on the same surface of the substantially rectangular parallelepiped shape of the semiconductor device according to the embodiment of the present invention. In the following, the normal direction of the surface where the second common electrode 9 and the external connection pin 8 of the semiconductor device according to the embodiment of the present invention are exposed is taken as the Z-axis direction, and the second common electrode 9 and the external connection pin 8 are exposed. The normal direction of a surface that is continuous with and perpendicular to the surface is defined as the X-axis direction, and the direction orthogonal to the X-axis direction and the Z-axis direction is defined as the Y-axis direction.

As shown in FIG. 2, the sealing member 10 connects the first common electrode to the surface opposite to the surface where the substantially rectangular parallelepiped-shaped second common electrode 9 and external connection pin 8 of the semiconductor device according to the embodiment of the present invention are exposed. 1 is exposed.

FIG. 3 is a perspective view of the internal structure of the semiconductor device according to the embodiment of the present invention shown in FIG. 1, with illustration of the sealing member 10 omitted and only the outer shape of the sealing member 10 shown by broken lines. . FIG. 4 shows an exploded perspective view of the internal structure of the semiconductor device according to the embodiment of the present invention shown in FIG. Shown in Figure 5.

As shown in FIGS. 4 and 5, one main surface (element mounting surface) of the first common electrode 1 is connected to one main surface of a plurality of semiconductor chips (semiconductor elements) 3 via a plurality of bonding materials 2. The first main electrode 33 on the surface (non-element surface) is bonded. As the material of the bonding material 2, for example, solder or a silver (Ag) or copper (Cu) based sintered material can be used. One main surface (element facing surface) of the printed circuit board 5 is arranged to face the other main surface (element surface) of the plurality of semiconductor chips 3 .

A plurality of control pins 6, a plurality of main current pins 7, and external connection pins 8 are inserted into the printed circuit board 5, forming an implant board 11. One ends of the plurality of control pins 6 and the plurality of main current pins 7 are connected to the control electrode 31 and second main electrode 32 on the other main surface (element surface) of the plurality of semiconductor chips 3 via the plurality of bonding materials 4. each connected. As the material for the bonding material 4, for example, solder or a silver (Ag) or copper (Cu) based sintered material can be used. One main surface (element facing surface) of the second common electrode 9 is arranged on the other main surface (non-element facing surface) of the printed circuit board 5 .

Next, a more detailed configuration of the semiconductor device according to the embodiment of the present invention will be described. As shown in FIGS. 6 and 7, the semiconductor device according to the embodiment of the present invention includes a plurality of semiconductor chips 3a, 3b, 3c, and 3d, and a plurality of semiconductor chips 3a to 3d bonded together through bonding materials 2a, 2b, etc. A first common electrode 1 is provided. The bonding materials 2a and 2b are included in the bonding material 2 shown in FIGS. 4 and 5. The plurality of semiconductor chips 3a to 3d correspond to the plurality of semiconductor chips 3 shown in FIGS. 4 and 5.

As the semiconductor chips 3a to 3d, for example, IGBTs, MOS transistors, SI thyristors, GTO thyristors, etc. can be employed, but here, a case where the semiconductor chips 3a to 3d are IGBTs will be exemplified. The semiconductor chips 3a to 3d may be configured with a wide bandgap semiconductor substrate such as silicon carbide (SiC), gallium nitride (GaN), or gallium oxide (Ga ₂ O ₃ ), or may be configured with a silicon (Si) substrate. You may.

As shown in FIG. 7, each of the semiconductor chips 3a to 3d has control electrodes (gate electrodes) 31a, 31b, 31c, 31d and second main electrodes (emitter electrodes) 32a, 32b, 32c, and 32d. Although not shown in FIG. 7, each of the semiconductor chips 3a to 3d has a first main electrode (collector electrode) on one main surface (non-element surface) side.

The respective control electrodes 31a to 31d of the semiconductor chips 3a to 3d are connected to the second main electrodes 32a to 32d and the first main electrodes of the semiconductor chips 3a to 3d, respectively, according to a predetermined control signal applied to the control electrodes 31a to 31d. Controls the main current flowing between the main electrodes.

As shown in FIG. 7, the semiconductor chips 3a to 3d are arranged such that the control electrodes 31a to 31d of the semiconductor chips 3a to 3d are close to each other. In the Y-axis direction, the semiconductor chips 3a and 3b are arranged adjacent to each other with control electrodes 31a and 31b of the semiconductor chips 3a and 3b facing each other. Further, the semiconductor chips 3c and 3d are arranged adjacent to each other with the control electrodes 31c and 31d of the semiconductor chips 3c and 3d facing each other. In the X-axis direction, semiconductor chips 3a and 3c are arranged adjacent to each other in the same direction. Moreover, the semiconductor chips 3b and 3d are arranged adjacently in the same direction.

Note that the arrangement positions of the semiconductor chips 3a to 3d are not limited to the arrangement positions shown in FIG. Furthermore, although four semiconductor chips 3a to 3d are illustrated in FIG. 7, the number of semiconductor chips is not limited. For example, it may have three or less semiconductor chips, or it may have five or more semiconductor chips.

The first main electrode (collector electrode) on one main surface (non-element surface) side of each of the semiconductor chips 3a to 3d is connected to one main surface (element surface) of the first common electrode 1 via bonding materials 2a, 2d, etc. mounted on the mounting surface). The first common electrode 1 is made of a plate-shaped conductive member. As the material of the first common electrode 1, for example, metal such as copper (Cu) can be used. As shown in FIG. 7, the first common electrode 1 has, for example, a substantially rectangular plane pattern. As shown in FIGS. 2 and 6, the other main surface (non-element mounting surface) of the first common electrode 1 is exposed from the sealing member 10 and serves as the first main electrode (collector electrode) of the semiconductor chips 3a to 3d. ) constitute a common electrode pad.

As shown in FIG. 6, the printed circuit board 5 includes an insulating layer 51, a wiring layer (53a, 53b) disposed on one main surface (element facing surface) of the insulating layer 51, and Wiring layers (52a, 52b) arranged on the surface (non-element facing surface). The insulating layer 51 can be made of an insulating material such as ceramics or resin whose main component is, for example, alumina (Al ₂ O ₃ ), aluminum nitride (AlN), silicon nitride (Si ₃ N ₄ ), or the like. The insulating layer 51 may be a resin substrate made of a combination of glass fiber and epoxy resin. The wiring layers (52a, 52b) and the wiring layers (53a, 53b) may be made by laminating Cu plates or Al plates, or may be plated with Cu, nickel (Ni), tin (Sn), or the like.

FIG. 8 is a plan view of the printed circuit board 5 with the wiring layers (52a, 52b) on one main surface (element facing surface) side of the insulating layer 51 omitted. As schematically shown by broken lines in FIG. 8, the wiring layer (53a, 53b) has a control wiring region 53a and a main wiring region 53b spaced apart from the control wiring region 53a. The control wiring region 53a has a substantially rectangular planar pattern. The main wiring area 53b has a U-shaped planar pattern surrounding the control wiring area 53a.

FIG. 9 is a plan view of the printed circuit board 5 viewed from the wiring layer (52a, 52b) side. As shown in FIG. 9, the wiring layer (52a, 52b) has a control wiring region 52a and a main wiring region 52b spaced apart from the control wiring region 52a. The control wiring area 52a has a substantially rectangular planar pattern similar to the control wiring area 53a, and is arranged to face the control wiring area 53a. The main wiring area 52b has a U-shaped planar pattern similar to the main wiring area 53b, and is arranged to face the main wiring area 53b.

As shown in FIGS. 6, 8, and 9, the printed circuit board 5 has a plurality of through holes that penetrate the insulating layer 51, the wiring layers (53a, 53b), and the wiring layers (52a, 52b). It is provided. Each of the plurality of through holes of the printed circuit board 5 includes a plurality of main current pins 7a, 7b, 7c, 7d, 7e, 7f, 7g, 7h, a plurality of control pins 6a, 6b, 6c, 6d, and an external connection pin 8. are respectively inserted and bonded to the printed circuit board 5. The plurality of main current pins 7a to 7h correspond to the plurality of main current pins 7 shown in FIGS. 4 and 5. The plurality of control pins 6a to 6d correspond to the plurality of control pins 6 shown in FIGS. 4 and 5.

The main current pins 7a to 7h shown in FIGS. 6, 8, and 9 are arranged to extend in the Z-axis direction. Two ends of each of the main current pins 7a to 7h are connected to second main electrodes 32a to 32d of the semiconductor chips 3a to 3d shown in FIG. 7, respectively, via bonding materials 4a, 4d, etc. There is. Note that the number of main current pins connected to each of the second main electrodes 32a to 32d is not particularly limited. Each of the main current pins 7a to 7h is electrically connected to the main wiring areas 52b and 53b of the printed circuit board 5, and the main wiring areas 52b and 53b are at the same potential. The other ends of each of the main current pins 7a to 7h are connected to one main surface (element facing surface) of the second common electrode 9 shown in FIG.

As the material for the main current pins 7a to 7h, conductive materials such as copper (Cu) and aluminum (Al) can be used. The shape of the main current pins 7a to 7h is exemplified here as being cylindrical (bar-shaped), but may be in other shapes such as a prismatic shape, a plate shape, or a block shape.

The control pins 6a to 6d shown in FIGS. 6, 8, and 9 are arranged to extend in the Z-axis direction. One end of each of the control pins 6a to 6d is connected to each of the control electrodes 31a to 31d of the semiconductor chips 3a to 3d shown in FIG. 7 via bonding materials 4b and 4c, respectively. Each of the control pins 6a to 6d is electrically connected to control wiring areas 52a and 53a of the printed circuit board 5, and the control wiring areas 52a and 53a are at the same potential. The other ends of each of the control pins 6a to 6d are spaced apart from one main surface (element facing surface) of the second common electrode 9 shown in FIG.

As the material for the control pins 6a to 6d, conductive materials such as copper (Cu) and aluminum (Al) can be used. Although the shape of the control pins 6a to 6d is exemplified here as being cylindrical (rod-like), it may be in other shapes such as a prismatic shape, a plate shape, or a block shape.

The control pins 6a to 6d have, for example, the same thickness (diameter) as the main current pins 7a to 7h. The control pins 6a to 6d may be thicker than the main current pins 7a to 7h, or may be thinner than the main current pins 7a to 7h. Here, in order to prevent contact between the control pins 6a to 6d and one main surface (element facing surface) of the second common electrode 9, the lengths of the control pins 6a to 6d are the same as the lengths of the main current pins 7a to 7h. This example shows a case where the length is shorter than .

The external connection pins 8 shown in FIGS. 6, 8, and 9 are arranged to extend in the Z-axis direction. One end of the external connection pin 8 on the side of the semiconductor chips 3a to 3d is separated from the semiconductor chips 3a to 3d. External connection pin 8 is electrically connected to control wiring areas 52a and 53a. That is, the external connection pin 8 is electrically connected to the control electrodes 31a to 31d of the semiconductor chips 3a to 3d, respectively, via the control wiring regions 52a and 53a and the control pins 6a to 6d.

The other end of the external connection pin 8 is exposed from the sealing member 10 and constitutes a common electrode pad for the control electrodes 31a to 31d of the semiconductor chips 3a to 3d, respectively. The other end of the external connection pin 8 is arranged flush with the other main surface (non-element facing surface) of the second common electrode 9. Note that the external connection pin 8 may protrude from the other main surface (non-element facing surface) of the second common electrode 9.

As the material for the external connection pin 8, conductive materials such as copper (Cu) and aluminum (Al) can be used. Although the shape of the external connection pin 8 is exemplified here as being cylindrical (rod-like), it may be in other shapes such as a prismatic shape, a plate shape, or a block shape.

For example, the external connection pin 8 is thicker than each of the control pins 6a to 6d and the main current pins 7a to 7h so that wire bonding or ribbon bonding can be performed on one end of the external connection pin 8 exposed from the sealing member 10. It is preferable. Note that the external connection pin 8 may have the same thickness as the control pins 6a to 6d or the main current pins 7a to 7h, or may be thinner than the control pins 6a to 6d or the main current pins 7a to 7h.

Note that the printed circuit board 5 may have only one of the wiring layers (53a, 53b) and the wiring layers (52a, 52b). For example, the printed circuit board 5 may be composed only of the insulating layer 51 and the wiring layers (53a, 53b), or may be composed only of the insulating layer 51 and the wiring layers (52a, 52b). Further, the wiring layer (53a, 53b) may be composed only of the control wiring region 53a electrically connected to the control pins 6a to 6d and the external connection pin 8. Similarly, the wiring layer (52a, 52b) may be composed only of the control wiring region 52a electrically connected to the control pins 6a to 6d and the external connection pin 8.

As shown in FIGS. 6 and 10, one main surface (element facing surface) of the second common electrode 9 is arranged to face the other main surface (non-element facing surface) of the printed circuit board 5. The second common electrode 9 is made of a plate-shaped conductive member. As the material of the second common electrode 9, for example, metal such as copper (Cu) can be used. The first common electrode 1 and the second common electrode 9 may be made of the same material, or may be made of different materials.

As schematically shown by broken lines in FIG. 10, one main surface (element facing surface) of the second common electrode 9 has a plurality of grooves (recesses) 9a, 9b, 9c, 9d, 9e, 9f, 9g, 9h is provided. The other ends of the main current pins 7a to 7h shown in FIGS. 6, 8, and 9 are press-fitted and joined to the plurality of grooves 9a to 9h. Note that the plurality of grooves 9a to 9h do not necessarily have to be provided, and the other ends of the main current pins 7a to 7h are connected to one main surface (element facing surface) of the second common electrode 9 via a bonding material. They may be joined.

The second common electrode 9 is electrically connected to the second main electrodes 32a to 32d of the semiconductor chips 3a to 3d, respectively, via the main current pins 7a to 7h. As shown in FIGS. 1 and 6, the other main surface (non-element facing surface) of the second common electrode 9 is exposed from the sealing member 10, and the second main electrodes 32a to 32a of the semiconductor chips 3a to 3d, respectively, are exposed from the sealing member 10. 32d constitutes a common electrode pad.

As shown in FIG. 10, the planar pattern of the second common electrode 9 is provided with a notch (recess) 9x. The external connection pin 8 shown in FIG. 6 passes through the notch 9x in the Z-axis direction and is arranged so as to be spaced apart from the second common electrode 9. Note that the cutout portion 9x does not necessarily have to be provided in the planar pattern of the second common electrode 9, and any shape or positional relationship such that the external connection pin 8 is spaced apart from the second common electrode 9 may be used.

As shown in FIGS. 1, 2, and 6, the sealing member 10 has a substantially rectangular parallelepiped shape. The sealing member 10 is arranged to surround the first common electrode 1, the semiconductor chips 3a to 3d, the printed circuit board 5, and the second common electrode 9, and seals at least the semiconductor chips 3a to 3d and the printed circuit board 5. . The sealing member 10 exposes the other main surface (non-element facing surface) of the second common electrode 9, the other end of the external connection pin 8, and the other main surface (non-element mounting surface) of the first common electrode 1. do.

As shown in FIGS. 1 and 2, some of the corners of the substantially rectangular parallelepiped shape of the sealing member 10 are chamfered, and chamfered portions 10a to 10d are provided. Note that the sealing member 10 does not necessarily need to be provided with the chamfered portions 10a to 10d, or other corner portions of the substantially rectangular parallelepiped shape of the sealing member 10 may be chamfered.

As the sealing member 10, a resin material such as a hard thermosetting resin with high heat resistance can be used, and specifically, epoxy resin, maleimide resin, cyanate resin, etc. can be used. The average linear expansion coefficient of the sealing member 10 from the curing temperature to room temperature is the same as the average linear expansion coefficient of the semiconductor material of the semiconductor chips 3a to 3d and the average linear expansion coefficient of the first common electrode 1 and the second common electrode 9. It is preferable to select the materials of the sealing member 10, the semiconductor chips 3a to 3d, the first common electrode 1, and the second common electrode 9 such that the distance between the two is the same. Thereby, peeling of the sealing member 10, distortion of the bonding materials 2 and 4, etc. can be suppressed.

<Assembling method of semiconductor device>
Next, an example of a method for assembling a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 4 and 5. First, the first main electrode 33 of one main surface (non-element surface) of a plurality of semiconductor chips 3 is mounted on one main surface (element mounting surface) of the first common electrode 1 via the bonding material 2. .

On the other hand, an implant board 11 in which a plurality of control pins 6, a plurality of main current pins 7, and an external connection pin 8 are inserted into a printed circuit board 5 is prepared. Then, by press-fitting one end of the plurality of main current pins 7 of the implant substrate 11 into the plurality of grooves provided in one main surface (element facing surface) of the second common electrode 9, the second common electrode 9 and the implant substrate 11 to form a bonded body.

Next, the bonding material 4 is mounted on the control electrode 31 and the second main electrode 32 on the other main surface (device surface) of each of the plurality of semiconductor chips 3. Then, one ends of the plurality of control pins 6 and the plurality of main current pins 7 of the joined body of the second common electrode 9 and the implant substrate 11 are connected to the other main current pins of each of the plurality of semiconductor chips 3 via the bonding material 4. The control electrode 31 and the second main electrode 32 on the surface (device surface) are mounted on the bonding material 4, respectively. Thereafter, the whole is joined by applying pressure or heating as necessary.

The above bonded structure is set in a mold and molded with resin to avoid voids. Thereafter, the other main surface (non-element mounting surface) side of the first common electrode 1 and the other main surface (non-element facing surface) of the second common electrode 9 are polished using a laser or mechanical polishing device as necessary. The sealing member 10 is formed by polishing the resin on the side, and the other main surface (non-element mounting surface) of the first common electrode 1, the other main surface of the external connection pin 8 and the second common electrode 9 ( The non-element facing surface) is exposed from the sealing member 10 and used as an electrode pad. As a result, a semiconductor device according to an embodiment of the present invention is completed.

<Application example>
Next, an application example of the semiconductor device 100 according to the embodiment of the present invention is shown in FIG. The first common electrode 1 of the semiconductor device 100 according to the embodiment of the present invention is bonded to an insulated circuit board 20 via a bonding material 24. The second common electrode 9 of the semiconductor device 100 according to the embodiment of the present invention is connected to a lead frame 26 via a bonding material 25. A plurality of semiconductor devices having the same configuration as the semiconductor device 100 according to the embodiment of the present invention may be mounted on the insulated circuit board 20.

The insulated circuit board 20 may be, for example, a direct copper bond (DCB) board, an active brazing (AMD) board, or the like. The insulated circuit board 20 includes an insulated substrate 21 , a wiring layer 22 arranged on one main surface of the insulated substrate 21 , and a wiring layer 23 arranged on the other main surface of the insulated substrate 21 . The insulating substrate 21 can be made of a ceramic substrate made of, for example, aluminum oxide (Al ₂ O ₃ ), aluminum nitride (AlN), silicon nitride (Si ₃ N ₄ ), or the like. As the material for the wiring layer 23 and the wiring layer 22, for example, conductive foil such as copper (Cu) or aluminum (Al) can be used.

Note that the entire semiconductor device 100 according to the embodiment of the present invention shown in FIG. 11 including the lead frame 26 and the insulated circuit board 20 may be used as the semiconductor device according to the embodiment of the present invention.

<Comparative example>
Next, semiconductor devices according to first and second comparative examples will be described. In the semiconductor device according to the first comparative example, as shown in FIG. 12, one or more semiconductor chips 103 are mounted on one main surface of an insulated circuit board 102 via a bonding material 108. The other main surface of the insulated circuit board 102 is mounted on a metal base 101 having a heat diffusion function. The periphery of the insulated circuit board 102 and the semiconductor chip 103 is covered with a resin case 104. The inside of the resin case 104 is filled with silicone gel 107 to improve insulation. The semiconductor chip 103 and the insulated circuit board 102 are electrically connected to external connection terminals 105 and 106 protruding from the resin case 104 via bonding wires 110 and 111 and a bonding ribbon.

As shown in FIG. 13, the semiconductor device according to the second comparative example is different from the semiconductor device according to the first comparative example shown in FIG. different from the equipment.

In the semiconductor devices according to the first and second comparative examples shown in FIGS. 12 and 13, the semiconductor module manufacturer combines the semiconductor chips 103 to obtain the required capacity and circuit configuration, and performs connections such as wire bonding. , the external connection terminals 105 and 106 are exposed to the outside. Therefore, the user does not have to handle the minute semiconductor chip 103 itself, and only needs to mechanically attach wiring such as a bus bar to the external connection terminals 105 and 106. However, since the semiconductor devices according to the first and second comparative examples shown in FIGS. 12 and 13 are manufactured for general purpose, they are overwhelmingly large compared to the size of the semiconductor chip 103 itself. The volume is large, and the internal wiring such as bonding wires 110 and 111 becomes long.

<Effect>
On the other hand, according to the semiconductor device according to the embodiment of the present invention, it is possible to integrate the plurality of semiconductor chips 3a to 3d while maintaining the same size as the plurality of semiconductor chips 3a to 3d. For this reason, the rating can be expanded by integrating multiple small chips in parallel, such as semiconductor chips using wide bandgap semiconductors such as SiC, Gan, _{Ga2O3 ,} etc., compared to making large chips with the same rating. , it is possible to achieve an overwhelmingly low cost in terms of yield.

Further, the electrode pads each constituted by the first common electrode 1, the second common electrode 9, and the external connection pin 8 are connected to the control electrode, the first main electrode, and the second main electrode of each of the plurality of semiconductor chips 3a to 3d. The pad size is also large. Therefore, various high current connection methods such as thick wire bonding, ribbon bonding, and lead frame connection can be employed even for small chips such as semiconductor chips using wide bandgap semiconductors. Therefore, for a general user who assembles a module using the semiconductor device according to the embodiment of the present invention, the degree of freedom in wiring is improved and handling becomes easy.

Furthermore, mechanical reliability is improved by molding the sealing member 10 around the connection portions between the plurality of semiconductor chips 3a to 3d, control pins 31a to 31d, and main current pins 4a to 4h. For example, in a small chip such as a semiconductor chip using a wide bandgap semiconductor, the bonding area on the element surface is small, and the thermal stress at the bonding portion is small. Therefore, the joint portion can be mechanically suppressed by sealing with the sealing resin 10. Since the control pins 6a to 6d and the main current pins 7a to 7h are small, peeling of the resin is unlikely to occur, and even if peeling occurs, the effect on the element surface is small. Therefore, even if the module assembled by the user is gel-sealed, the heat cycle durability and power cycle durability around the semiconductor chips 3a to 3d can be improved.

Furthermore, since the semiconductor chips 3a to 3d are spaced apart from the second common electrode 9 constituting the electrode pad and are molded with the sealing member 10, the lead frame 26 etc. on the user side as shown in FIG. Even when connecting external wiring, direct stress is less likely to be applied to the semiconductor chips 3a to 3d.

Furthermore, by using the second common electrode 9 as an electrode pad instead of using the control electrodes and second main electrodes of the semiconductor chips 3a to 3d using semiconductors with a low coefficient of linear expansion as electrode pads, it is possible to connect the second common electrode 9 with an external metal. Even when wiring is connected, there is little difference in linear expansion coefficient, and the connection part is unlikely to crack due to temperature changes. For example, if the wiring material on the user side is the same material as the second common electrode 9 (for example, Cu), compared to the case where the wiring on the user side is directly connected to the control electrodes and second main electrodes of the semiconductor chips 3a to 3d. As a result, thermal stress can be reduced and life can be extended. Therefore, a small, low-loss, long-life semiconductor device can be realized at low cost.

<First modification example>
As shown in FIG. 14, the semiconductor device according to the first modification of the embodiment of the present invention has the same features as shown in FIG. This is different from the configuration of the semiconductor device according to the embodiment of the present invention. As the semiconductor chips 3a, 3b become smaller, the control electrodes and second main electrodes of the semiconductor chips 3a, 3b become smaller. This makes connection with one end of the current pins 7a and 7c difficult.

According to the semiconductor device according to the first modification of the embodiment of the present invention, even when the semiconductor chips 3a, 3b are downsized, one end of the control pins 6a, 6b and the main current pins 7a, 7c can be tapered. , one ends of the control pins 6a, 6b and the main current pins 7a, 7c can be easily connected to the control electrodes and second main electrodes of the semiconductor chips 3a, 3b via the bonding materials 4a to 4d.

<Second modification example>
As shown in FIG. 15, the semiconductor device according to the second modification of the embodiment of the present invention has the following points: the first common electrode 1 and the second common electrode 9 extend in the lateral direction (Y-axis direction). This is different from the configuration of the semiconductor device according to the embodiment of the present invention shown in FIG.

The sealing member 10 is arranged only between the first common electrode 1 and the second common electrode 9. A portion of each side surface of the first common electrode 1 and the second common electrode 9 is exposed from the sealing member 10 . Grooves 1a and 1b are provided on one main surface (element mounting surface) of the first common electrode 1, and are filled with a sealing member 10. Grooves 9i and 9j are provided on one main surface (element facing surface) of the second common electrode 9, and are filled with a sealing member 10. Since the first common electrode 1 has the grooves 1a and 1b and the second common electrode 9 has the grooves 9i and 9j, separation of the sealing member 10 from the first common electrode 1 and the second common electrode 9 is prevented. Can be suppressed.

According to the semiconductor device according to the second modification of the embodiment of the present invention, by expanding the first common electrode 1 and the second common electrode 9 in the lateral direction, the first common electrode 1 and the second common electrode 9 are expanded. Since the area exposed from the sealing member 10 becomes larger, heat dissipation can be improved. Note that instead of both the first common electrode 1 and the second common electrode 9, only one of the first common electrode 1 and the second common electrode 9 may be expanded in the horizontal direction (Y-axis direction).

<Third modification example>
In the semiconductor device according to the third modification of the embodiment of the present invention, as shown in FIGS. 16 and 17, a groove (recess) 9y is provided in one main surface (element facing surface) of the second common electrode 9. This is different from the configuration of the semiconductor device according to the embodiment of the present invention shown in FIG.

The depth d2 of the groove 9y is deeper than the depth d1 of the grooves 9a to 9h. One end of each of the plurality of control pins 6a to 6d is arranged in the groove 9y. Instead of providing one groove 9y in which the plurality of control pins 6a to 6d are arranged all at once, a plurality of grooves may be provided in which the plurality of control pins 6a to 6d are respectively arranged. When the lengths of the main current pins 7a to 7h and the control pins 6a to 6d are the same, as shown in FIG. 17, one ends of the main current pins 7b and 7d are press-fitted into the grooves 9b and 9d. On the other hand, one ends of the control pins 6a and 6b are arranged in the groove 9y, and can be prevented from coming into contact with the second common electrode 9.

According to the semiconductor device according to the third modification of the embodiment of the present invention, a groove 9y is provided in one main surface (element facing surface) of the second common electrode 9, in which one end of the control pins 6a to 6d is disposed. This makes it possible to prevent short circuits between one ends of the control pins 6a to 6d and the second common electrode 9. Therefore, main current pins 7a to 7h and control pins 6a to 6d of the same length can be used, and manufacturing costs can be reduced.

(Other embodiments)
As described above, the present invention has been described by way of embodiments, but the statements and drawings that form part of this disclosure should not be understood as limiting the present invention. Various alternative embodiments, implementations, and operational techniques will be apparent to those skilled in the art from this disclosure.

For example, in the semiconductor device according to the embodiment of the present invention, the semiconductor chips 3a to 3d have a vertical structure, but the present invention can also be applied to a case where a plurality of semiconductor chips have a horizontal structure. It is also possible to convert a plurality of semiconductor chips with a horizontal structure into a semiconductor device with a vertical structure, or to convert a plurality of semiconductor chips with a vertical structure into a semiconductor device with a horizontal structure. Further, the external connection terminal 8 may be taken out from the other main surface (non-element mounting surface) side of the first common electrode 1, or the external connection terminal 8 may be taken out from the other main surface (non-element mounting surface) side of the first common electrode 1. It may be taken out from both the main surface (non-element facing surface) side of the second common electrode 9. That is, a plurality of semiconductor chips and an implant substrate are connected, the plurality of semiconductor chips and the implant substrate are sealed with a sealing member, and an enlarged electrode common to the plurality of semiconductor chips is exposed from the sealing member and exposed to the outside. The configuration of the chip size package (CSP) to be taken out is all within the scope of the present invention.

Thus, it goes without saying that the present invention includes various embodiments not described here. Therefore, the technical scope of the present invention is determined only by the matters specifying the invention in the claims that are reasonable from the above description.

1...First common electrode 1a, 1b, 9y, 9a to 9j...Groove (concave)
2, 2a, 2b, 4, 4a to 4d, 24, 25, 108, 109, 112... Bonding material 3, 3a to 3d, 103... Semiconductor chip 5... Printed circuit board 6, 6a to 6d... Control pin 7, 7a ~7h...Main current pin 8...External connection pin 9...Second common electrode 9x...Notch (recess)
11... Implant board 20, 102... Insulated circuit board 21... Insulating substrate 22, 23... Wiring layer 26, 113... Lead frame 31, 31a to 31d... Control electrode 32, 32a to 32d... Second main electrode 33... First main Electrode 51...Insulating layer 52a, 53a...Control wiring area 52b, 53b...Main wiring area 100...Semiconductor device 101...Metal base 104...Resin case 105, 106...External connection terminal 107...Silicon gel 111...Bonding wire

Claims (15)

a plurality of semiconductor chips each having a first main electrode, a second main electrode and a control electrode on mutually opposing main surfaces;
a first common electrode having the first main electrode of each of the plurality of semiconductor chips mounted on one main surface;
a printed circuit board having one main surface opposite to the one main surface of the first common electrode;
a second common electrode having one main surface opposite to the other main surface of the printed circuit board;
a sealing member that seals the plurality of semiconductor chips and the printed circuit board and exposes the other main surface of the second common electrode and the other main surface of the first common electrode;
a plurality of control pins inserted into the printed circuit board, one end connected to the control electrode of each of the plurality of semiconductor chips, and the other end spaced apart from the second common electrode;
a plurality of main current pins inserted into the printed circuit board, one end of which is connected to the second main electrode of each of the plurality of semiconductor chips, and the other end of which is connected to the second common electrode;
an external connection pin inserted into the printed circuit board, one end electrically connected to the plurality of control pins via the printed circuit board, and the other end exposed from the sealing member;
A semiconductor device comprising: A notch is provided in the planar pattern of the second common electrode,
The semiconductor device according to claim 1, wherein the external connection pin passes through the notch. 3. The semiconductor device according to claim 1, wherein the other end of the external connection pin is arranged flush with the other main surface of the second common electrode. 4. The semiconductor device according to claim 1, wherein the one end of each of the plurality of control pins and the plurality of main current pins has a tapered shape. 5. The semiconductor device according to claim 1, wherein the external connection pin is thicker than each of the plurality of control pins and the plurality of main current pins. The printed circuit board is
an insulating layer;
a first wiring layer provided on one main surface of the insulating layer and electrically connected to the plurality of control pins and the external connection pin;
The semiconductor device according to any one of claims 1 to 5, characterized in that the semiconductor device has: 7. The printed circuit board further includes a second wiring layer provided on the other main surface of the insulating layer and electrically connected to the plurality of control pins and the external connection pins. The semiconductor device described. The first wiring layer is
a first control wiring region electrically connected to the control pin and the external connection pin;
a first main wiring area separated from the first control wiring area and electrically connected to the main current pin;
8. The semiconductor device according to claim 7, comprising: The second wiring layer is
a second control wiring region electrically connected to the plurality of control pins and the external connection pin;
a second main wiring area separated from the second control wiring area and electrically connected to the plurality of main current pins;
9. The semiconductor device according to claim 8, comprising: 10. The semiconductor device according to claim 1, wherein the plurality of semiconductor chips are arranged such that the control electrodes of each of the plurality of semiconductor chips are close to each other. a plurality of first grooves are provided on the one main surface of the second common electrode,
11. The semiconductor device according to claim 1, wherein the other end of each of the plurality of main current pins is press-fitted into each of the plurality of first grooves. 12. The semiconductor device according to claim 1, wherein the plurality of main current pins are longer than the plurality of control pins. A second groove portion deeper than the plurality of first groove portions is provided on the one main surface of the second common electrode,
the other end of each of the plurality of control pins is disposed within the second groove,
The semiconductor device according to claim 11, wherein the plurality of control pins have the same length as the plurality of main current pins. 14. The semiconductor device according to claim 1, wherein the sealing member is provided with a chamfered portion. The average linear expansion coefficient of the sealing member from the curing temperature to room temperature is the average linear expansion coefficient of the semiconductor material of the plurality of semiconductor chips and the average linear expansion coefficient of the first common electrode and the second common electrode. The semiconductor device according to any one of claims 1 to 14, characterized in that the semiconductor device is located between.

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