JPS61222093A - Nonvolatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To enlarge data reading margin by changing load registance of a memory cell and a dummy cell. CONSTITUTION:When memory information of a memory cell 31 is '0', a controlling signal E is made to '0', and an MOS transistor 35 for load in parallel with an MOS transistor 34 for load becomes off, and load resistance of the cell 31 side becomes low. Consequently, input potential to a sense amplifier 33 corresponding to the content of memory of the cell 31 becomes low, and the difference between reference potential through a dummy cell 32 becomes large, and the content of memory of the cell 31 is read out by the differential potential through the sense amplifier 33. On the other hand, when the content of memory of the cell 31 is '1', an MOS transistor 37 for load is made off through a controlling signal W, and reference potential by the cell 32 is lowered by lowering of load resistance, and the difference between memory information and reference potential becomes large. Thus, data reading margin becomes large.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a nonvolatile semiconductor memory device with an improved load circuit.

[Technical background of the invention and its problems] For example, a non-volatile device that programs stored data by injecting electrons into a floating gate through a thin silicon oxide film of about 100 layers, or by emitting electrons. Semiconductor memory bags (hereinafter referred to as EEPROMs) are well known. As shown in FIG. 5, such an EEPROM memory cell has a floating gate (floating gate) and a (control gate).
It is composed of a double-gate structure MOS transistor 1 for data storage with a MOS transistor 1 having a double gate structure, and a selection MOS transistor 2 connected in series thereto.The drain of the selection transistor 2 is connected to a data line 3. An example of the element structure of a memory cell connected in this manner is shown in FIG.

FIG. 6(a) is a pattern plan view of this memory cell, and FIG. 6(b) is a cross-sectional view taken along line a-a'. In FIG. 6, n medium semiconductor regions 12, 13, and 14 are formed on the surface of a p-type silicon semiconductor substrate 11, separated from each other. Of these, the semiconductor region 12 constitutes the drain of the selection transistor 2 and the data line 3, and the semiconductor region 13 constitutes the selection transistor 2.
The semiconductor region 14 constitutes the source of the transistor 1 and the train of the data storage transistor 1, and the semiconductor region 14 constitutes the source of the transistor 2. And the semiconductor region 14 which is the source of the transistor Ri1
is connected to a reference potential point, for example a ground potential point.

Between the semiconductor regions 12 and 13, a gate wiring 15 of the selection transistor 2 made of a polycrystalline silicon layer doped with impurities is provided extending laterally through an insulating film. Further, between the semiconductor regions 13 and 14, a 70-ring gate 16 of the data storage transistor 1 made of a polycrystalline silicon layer doped with impurities is provided. Between them, on the floating gate 1G, a control gate 17 of the data storage transistor 1 made of a polycrystalline silicon layer doped with impurities is provided extending laterally. Here, the n+ type semiconductor region 13 and the floating gate 1
6 overlap each other via a thin insulation 1118 of, for example, about 100, as described above.

In a memory cell with such a configuration, transistor 1
When writing data by injecting electrons into the 70-ting gate 16, the potential of the floating gate 16 is raised by setting the control gate 17 to a high potential, for example, +20V, and the potential of the floating gate 16 is increased. Electrons are injected into the 70-ring gate 16 via the thin insulating film 18 between the semiconductor region 13 and the semiconductor region 13 . On the other hand, when erasing data, that is, when releasing the electrons captured by the floating gate 16,
This is done by setting the control gate 17 to o■, applying a high potential to the gate wiring 15 of the selection transistor 2 and the data line 3, and supplying the high potential to the semiconductor region 13. At this time, a current flows between the floating gate 16 and the semiconductor region 13 through the insulating film 18 in the opposite direction to the writing of data.
The electrons captured in the semiconductor region 6 are released into the semiconductor region 13.

By the way, in an EEPROM having such a memory cell, when programming data, the same memory chip has a function to check whether a sufficient amount of electrons have been injected into the floating gate or whether enough electrons have been emitted from the floating gate. There is also one on top. Such a function is called a self-verify function, and in EEPROMs with this self-verify function, the memory chip enters the program mode and immediately after injecting or ejecting electrons from the memory cell's 70-ring gate, The data is read and it is checked whether predetermined data has been programmed. If the programming is not sufficient, electrons are injected or ejected again to reconfirm whether or not the programming is sufficient. Such operations are continued until the data is sufficiently programmed.

FIG. 7 is a characteristic curve diagram showing the relationship between the control gate voltage VCG of the data storage transistor 1 and the drain current ID in the memory cell having the structure shown in FIG. 5. Curve 21 in the figure is the characteristic in the initial state when no data programming is performed, curve 22 is the characteristic after electrons are injected into the floating gate and data is written, and curve 23 is the characteristic in the floating gate. This is the characteristic after data is erased by emitting electrons from the gate. By performing data programming in the memory cell, the characteristics initially shown by the curve 21 in FIG. 7 gradually shift in parallel to the characteristics shown by the curves 22 or 23 in FIG.

By the way, the data programming state using the self-verify function can be confirmed by sensing the input potential read from the memory cell and the reference potential read from the dummy cell, which is not programmed and maintains the characteristics of curve 21 in FIG.・This is done by comparing using an amplifier. Therefore, when the input potential of the sense amplifier slightly exceeds or falls below the reference potential during this programming, the detection signal of the sense amplifier is inverted, and it is determined that the data programming has been completed. However, if the potential difference between the input potential and the reference potential is small, the input potential will cross the reference potential due to the influence of power supply noise, for example, causing malfunction. Therefore, when reading data, it is desirable that the potential difference between the input potential and the reference potential be large, and the greater this potential difference, the wider the data read margin during normal data reading.

[Objective of the Invention] This invention has been made in consideration of the above-mentioned circumstances, and its purpose is to provide a nonvolatile semiconductor memory device that can widen the data read margin in the normal data read mode. It's about doing.

[Summary of the Invention] In order to achieve the above object, the non-volatile semiconductor memory device of the present invention has a structure in which the load transistor on the memory cell side or the dummy cell side is By changing the load capacity, the potential difference between the reference potential during normal data reading and the input potential, which is the data of the memory cell, is widened.

[Embodiments of the invention] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing only the essential parts of a nonvolatile semiconductor memory device according to the present invention.

In the figure, numeral 31 is one of the memory cells consisting of the data storage transistor 1A and the selection transistor 2A as described above, and 32 is a dummy cell consisting of the data storage transistor 1B and the selection transistor 2B. Here, no electrons are injected or emitted into the floating gate of the data storage transistor 1B in the dummy cell 32, and the floating gate is kept in a neutral state. The input potential and reference potential generated on the data lines 3A and 3B of the memory cell 31 and dummy cell 32 are supplied to a sense amplifier 33.

The sense amplifier 33 detects stored data in the data write state and the data erase state of the memory cell 31 by comparing the same potentials. In addition, the data line 3A on the memory cell 31 side and the power supply voltage V
A MOS transistor 34 whose threshold voltage is approximately Ov is connected between the c application point and the load of this memory cell 31.
is inserted.

The gate of this transistor 34 is connected to the power supply voltage Vc application point, and is kept in an on state at all times. Further, a MOS transistor 35 whose threshold voltage, which is the load on the memory cell 31, is set to approximately OV is connected in parallel with this transistor 34, and the gate of this transistor 35 is connected to the gate of the transistor 35 for transmitting data to the transistor 1A in the memory cell 31. A control signal E is supplied which is set to the "1" level only when erasing is to be performed.

The data line 3B on the dummy cell 32 side and the power supply voltage V
A MOS transistor 36 whose threshold voltage is approximately OV is connected between the c application point and the dummy cell 32 as a load.
is inserted. The gate of this transistor 36 is connected to the application point of the power supply voltage Vc, and is kept in an on state at all times. Furthermore, a MOS transistor 37 whose threshold voltage is approximately OV is connected in parallel with this transistor 3B, and serves as a load for the dummy cell 32. A control signal W is supplied which is set to the "1" level only when writing is performed.

In addition, here, the emission of electrons from the floating gate is referred to as data erasure, and the erased data is referred to as “
0'' level, injecting electrons into the floating gate is defined as data writing, and the written data is defined as ``1'' level.

Next, the operation of the circuit configured as described above will be explained. Now, suppose that electrons are accumulated in the 70-ting gate of the transistor 1A in the memory cell 31, and data at the "1" level is stored, and when this stored data is erased to make the "O" level. The self-verification operation of is explained.

During this erasing operation, the control signal E is set to the "1" level, and the control signal W is set to the "0" level.

As a result, the transistor 35 on the memory cell side is turned on, and the transistor 37 on the dummy cell side is turned off. Therefore, at this time, the load capacity on the memory cell side is made larger than that on the dummy cell side.

As the erase operation progresses, the cell current flowing through the transistor 1A in the memory cell 31 increases sequentially. FIG. 2 is a characteristic curve diagram showing the cell current flowing through the transistors IA and IB in the memory cell 31 or dummy cell 32 and the change in the input potential or reference potential of the sense amplifier 33 corresponding to the cell current at that time. If the cell current flowing through the transistor 1A changes according to the curve 41 in FIG. 2, then the input potential also changes along the characteristic curve 41. At this time, if the characteristics on the dummy cell side are given by the curve 42 and the cell current flowing through the transistor 1B in the dummy cell 32 is I1, then the reference potential at this time is vl.

In this state, erasing on the memory cell side progresses, and when the cell current further increases and the input potential drops to v2, which is slightly lower than vl, the detection signal of the sense amplifier 33 is inverted. At this point, it is determined that the erasure has been sufficiently performed. The cell current at this time is I2.

Next, during normal data reading after the above-described erasure is performed, the control signal E is set to the "0" level. At this time, the cell current has the same I2 value as during erasing, but the load capacity on the memory cell side has decreased, and if the characteristic curve at this time is 43, the input potential will change from ■2 to ■3. decreases to As a result, the difference between the reference potential and the input potential becomes wider during actual data reading than during erasing.
Data read margin can be increased.

Next, in a state where electrons are accumulated in the 70-ting gate of the transistor 1A in the memory cell 31 and data at the "0" level is stored, a self-verification operation is performed when data is written to the "1" level. Explain. During this write operation, the control signal E is set to the "0" level, and the control signal W is set to the "1" level. As a result, the transistor 37 on the dummy cell side is turned on, and the transistor 35 on the memory cell side is turned off.

As the write operation progresses, the cell current flowing through the transistor 1A in the memory cell 31 gradually decreases, and at this time, the cell current and the sense current corresponding to the cell current at that time decrease.
The characteristic curve 43 in FIG. 2 shows the change in the input potential of the amplifier 33. At this time, the characteristics of the dummy cell side are curve 44
It is given in Transistor 1 in dummy cell 32
Since the cell current flowing through B is I1, the reference potential at this time is V4. In this state, writing on the memory cell side progresses, and when the cell current further decreases and the input potential rises to v5, which is slightly higher than v4, the sense amplifier 3
The detection signal of No. 3 is inverted. At this point, it is determined that sufficient writing has been performed. The cell current on the dummy cell side at this time is 11.

Next, during normal data reading after the above writing is performed, the control signal W is set to the "0" level.

At this time, the cell current on the dummy cell side has the same value of I1 as during the above writing, but the load capacity on the dummy cell side has decreased, and the characteristic curve at this time is 42, so the reference potential changes from ■4 to ■1. decreases to As a result, the difference between the reference potential and the input potential is wider during actual data reading than during writing, and the data read margin can be increased in this case as well.

In this manner, according to the above embodiment circuit, the load capacity is set so that the potential difference between the input potential and the reference potential becomes large during data erasing and data writing, and the sense amplifier 33 compares the potentials. As a result, the potential difference between the input potential and the reference potential during normal data reading can be made sufficiently large, thereby widening the data read margin.

FIG. 3 is a circuit diagram showing the configuration of another embodiment of the invention. This embodiment circuit differs from the above embodiments in that one more transistor 38 is connected in parallel to the load transistor 34 on the memory cell side. This transistor 38 also has a threshold voltage set to approximately Ov, and its gate is supplied with a program signal P that is always at the "1" level during the data write period or erase period and during the verify period after these periods have ended. has been done.

The reason why this transistor 38 is further provided is as follows. That is, as is clear from the characteristic curve diagram of FIG. 2, as the cell current increases, the input potential C or the reference potential changes gradually. Therefore, if a device with a large cell current is produced during the manufacturing stage, even if the control signal E is set to the "0" level during normal data reading to widen the potential difference between the input potential and the reference potential, the potential difference will not be widened sufficiently. there is a possibility. Therefore, in this embodiment, the transistor 38 is turned on by the signal P during programming to increase the load capacity on the memory cell side, lowering the input potential to a lower value than in the embodiment shown in FIG. This is to widen the potential difference between the input potential and the reference potential during reading.

FIG. 4 is a characteristic curve diagram corresponding to FIG. 2 in this embodiment, and curves 1m5i and 52 show the relationship between the cell current and input potential on the memory cell side during programming, and curve 51 is one of them. The curve 52 shows the case where the control signal E is set to "1" level, and the curve 52 shows the case where the control signal E is set to "0" level.
The control signal P is at the "1" level in both cases.Curves 53 and 54 show the relationship between the cell current and the input potential on the dummy cell side. For song @53, the control signal W is set to “1”.
The curve 54 is the one when the control signal W is set to the "O" level.
5 shows the relationship between the cell current on the memory cell side and the input potential during normal data reading, and control signals E and P are both set to the "0" level.

[Effects of the Invention] As described above, according to the present invention, it is possible to provide a nonvolatile semiconductor memory device that can widen the data read margin during normal data read.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of one embodiment of the present invention, Fig. 2 is a characteristic curve diagram of the circuit of the above embodiment, Fig. 3 is a circuit diagram of another embodiment of the invention, and Fig. 4 is the circuit diagram of the above embodiment circuit. FIG. 5 is a circuit diagram of an EEPROM memory cell, and FIG. 6 is a characteristic curve diagram of the example circuit.
The figures are a pattern plan view and a sectional view of an example of the element structure of the memory cell shown in FIG. 5, and FIG. 7 is a characteristic curve diagram of the memory cell shown in FIG. 5. 31...Memory cell, 32...Dummy cell, 33.
...Sense amplifier, 34.35.36.37.38.
...MOS transistor for load. Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 2 □ Cell power supply L Figure 3 Figure 4 - Kof Maru

Claims (3)

[Claims] (1) a nonvolatile memory cell, a sense amplifier that detects data by comparing a reference potential and an input potential that is data of the memory cell, and a first load circuit that serves as a load for the memory cell; A dummy cell for forming the comparison potential, a second load circuit serving as a load for the dummy cell, and means for changing the resistance value of the first or second load circuit in accordance with a control signal. A nonvolatile semiconductor memory device characterized by: (2) The first load circuit is connected to a first load transistor in parallel with the first load transistor, and is controlled to be in a conductive state when erasing data in the memory cell. and a second load transistor, and the second load circuit is connected in parallel to the third load transistor, and when writing data in the memory cell, the second load circuit is connected in parallel to the third load transistor. 2. The nonvolatile semiconductor memory device according to claim 1, further comprising a fourth load transistor controlled to be in a conductive state. (3) A fifth load transistor is further controlled to be in a conductive state with respect to the first load transistor during a data write period or erase period in the memory cell and a predetermined period after the end of these periods. The nonvolatile semiconductor memory device according to claim 2, wherein the nonvolatile semiconductor memory device is connected in parallel.