JPH10302488A - Non-volatile semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve reliability for write protection in a non-selective NAND train by applying a voltage which is sufficiently capable of ON state even in a normally OFF state and selective automatic boost of the channel potential on the control gate of each of the selected memory cells, the neighboring memories, and the memory cells sharing a control gate. SOLUTION: The control gates of memory cells selected ones with a circular mark, the neighboring one and the other ones are impressed with 20V, 4.5V and 11V. With this voltage control, the selected transistor SG 1 is made OFF by 3.3V supplied from a non-selective bit line BL2 to generate automatic boost. Accordingly the potential of the control gate of the memory cell impressed with 4.5V becomes lower than the channel potential and made OFF to provide a write operation. The potentials of the channel regions 2, 1 and 3 of the memory cells are raised to 10V, 7V in response to the rise of the voltage from 0V to 20V, and from 0V to 11V, diminishing the potential difference. Therefore, stress applied to memory cells are mitigated, improving reliability.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically rewritable nonvolatile semiconductor memory using, as a memory cell, a memory element having a structure in which a floating gate electrode for charge storage and a control gate electrode are stacked. More specifically, the present invention relates to a NAND-type EEPROM (elec) in which a plurality of memory cells are connected in series.
trically erasable programmable ROM).

[0002]

2. Description of the Related Art FIG. 1A shows a NAND type EEPROM.
FIG. 2 is a plan view extracting and showing one memory cell column of FIG.
FIG. 1B is an equivalent circuit diagram thereof. FIG. 2 shows FIG.
It is sectional drawing which follows the II-II line of (A). FIG.
FIG. 3A is a cross-sectional view along the line III-III.

[0005] This memory cell column is formed in a double diffusion type P well 11 formed on a p-type semiconductor substrate. Each memory cell has a floating gate electrode 14 for charge storage and a control gate electrode 16 which are stacked on a channel region between source and drain regions via insulating films 13 and 15. However, in the following description, a memory cell may be simply referred to as a cell. As shown in the figure, a plurality of stacked memory cells M1 to M8 controlled by control gates CG1 to CG8 are connected in series in the memory cell column, and both ends of the serially connected memory cell column, that is, the drain D Select transistors S1 and S2 are provided on the side and the source S side, respectively. By the selection gates SG1 and SG2 of these selection transistors S1 and S2,
The configuration is such that the connection with the bit line 18 and the common source line of the memory cell column is controlled. Incidentally, reference numeral 17 in FIG. 3 denotes an interlayer insulating film. Moreover, 14 in FIG. 2 ₉ 16 _9,
And 14 ₁₀ and 16 ₁₀ are electrically connected to each other in a region (not shown) and are processed into select gates SG1 and SG2.

FIG. 4 is a diagram showing an example of a voltage applied to each part at the time of erasing, writing and reading operations in the memory cell. Hereinafter, these operations will be described, and the accompanying problems will be described.

<Erase of Data> To erase data, the bit line BL and the source S are opened, and the control gate CG is erased.
And the selection gate SG are all biased to 0 V, and the substrate W
By applying an erasing voltage VEE (for example, 20 V) to the (P-well layer) 11, electrons in all floating gate electrodes are extracted by utilizing a tunnel phenomenon of an oxide film. As a result, the threshold values of all the memory cells become 0 V or less, and the memory cells are normally turned on (depletion type). This normally ON state is defined here as data "1". On the other hand, a normally OFF (enhanced type) state is defined as data “0”.

As described above, the conventional NAND type EEPR
When data is collectively erased in the OM, a high erase voltage (VEE) of about 20 V needs to be applied to the P-well layer. For this reason, in the conventional NAND type EEPROM,
In order to be able to operate at such a high voltage, it is necessary to use a high breakdown voltage transistor (for example, a gate oxide film having a thickness as large as about 400 Å). The space needed to be wider than the ones. For this reason,
There is a problem that miniaturization and high density of the element are hindered.

Furthermore, since a high voltage is used, there is a problem that it is difficult to design the element in order to ensure reliability.

<Writing and Reading Data> In writing data, the write voltage Vpp (for example, 20 V) is applied to the control gate of the selected cell among the control gates CG.
V), and Vpp and 0 V are applied to the control gates of the non-selected cells.
(For example, 10 V). In this state, 0 is applied to the bit line BL of the cell to which data “0” is written.
While V is applied, the potential Vm is applied to the bit line BL of the cell in which the data remains at "1".

The selected memory cell (control gate = Vpp
= 20V, bit line = 0V), the control gate electrode 16
Applied between the substrate and the substrate 11 (Vpp = 20V)
Is the capacitance between the floating gate electrode 14 and the semiconductor substrate (C
s1) and the ratio (Cs2 / (Cs1 + Cs2)) of the capacitance (Cs2) between the floating gate electrode 14 and the control gate electrode 16 (hereinafter referred to as a coupling ratio). For example, Cs2 /
When (Cs1 + Cs2) = 0.5, the potential difference between the floating gate electrode 14 and the semiconductor substrate 11 is 10V. At this time, the electric field applied to the gate oxide film (hereinafter referred to as a tunnel oxide film) between the floating gate electrode 14 and the semiconductor substrate 11 is 10 MV / cm if the thickness of the tunnel oxide film is 10 nm, and the Fowler-Nordheim A current (hereinafter referred to as a tunnel current) flows through the tunnel oxide film, and electrons are injected into the floating gate electrode 14. As a result, the threshold value of the selected memory cell becomes positive, becomes a normally OFF state, and data "0" is written. Note that the threshold value of the write cell is set to be 0 V or more and Vcc (for example, 5 V) or less.

On the other hand, for an unselected memory cell row (NAND cell row) holding data "1", although a slight electric field is applied, a voltage (Vm = 10 V) from a bit line is applied to the channel side. Therefore, even if a high voltage (Vpp) is applied to the control gate electrode 16, the voltage applied between the substrate 11 and the control gate electrode 16 becomes smaller than that of the selected cell (Vpp-Vm = 20-10V = 10V). Therefore, the electric field applied to the tunnel oxide film is also reduced (about 5 MV / c).
m), a tunnel current does not flow, and writing of data “0” is not performed.

In reading data, the bit line connected to the cell column to which the selected cell belongs is, for example, 1 bit.
V, and the other bit lines are set to 0V.
Then, 0 V is applied to the control gates of the selected cells, and Vcc (= 5 V) is applied to the control gates of the other unselected cells. As a result, the selected cell is turned ON or OFF depending on whether the written data is “1” or “0”, while the non-selected cell has the written data “1” or “0”. Any of "0" is turned on. As a result, select gates SG1 and S1
When G2 is opened, if the data of the selected cell is "1" and a normally ON (depletion) state is applied, a current flows to the source side, but the data of the selected cell is "0" and normally OFF. (Enhanced), no current flows. Therefore, whether or not the data of the selected cell is “0” or “1” can be determined depending on whether or not a current flows from the bit line to the selected cell column. FIG. 5 shows the static characteristics of cells having a threshold value Vth larger than 0 V (ie, enhanced) and cells having a threshold value Vth smaller than 0 V (ie, depletion). VCG is the voltage to the control gate,
Id is a drain current.

As a technique for improving the above described fixed potential writing method, KDSuh et al.
There is a self-boosting method announced in d-State Circuits, vol. 30, No. 11 (1995). In this self-boosting method, as a result of the improved write-inhibiting mechanism in the non-selected NAND cell column, the potential amplitude between the selected bit line and the non-selected bit line is changed from the conventional 0V → VM (for example, 10 V).
V) to 0 V → Vcc (for example, 3.3 V). As a result, there are obtained effects such as reduction in breakdown voltages of various transistors and achievement of miniaturization of elements.

Further, as a method of further improving the self-boosting method according to KDSuh et al., TSJung et al.
l Self-boosting (LSB) method is devised (TSJun
g et al., ISSCC Tech-Dig., p32, 1996). According to this method, the stress due to the write voltage Vpgm in the non-selected NAND cell row can be reduced, and a great improvement effect can be obtained particularly with respect to the variation in the threshold value of the multi-value cell.

However, in the above-described selective self-boosting method, the reliability of the write prohibition in the non-selected NAND cell row cannot be said to be sufficient, and random writing to a plurality of cells in the selected NAND cell row cannot be performed. There was a problem.

[0015]

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and a first object of the present invention is to provide a NAND type E
In applying the selective self-boosting method in the EPROM, it is necessary to improve the reliability of the write prohibition in the non-selected NAND cell row, and to randomly write to a plurality of cells in the selected NAND cell row. It is an object of the present invention to provide a nonvolatile semiconductor memory device which can be used.

A second object of the present invention is to make it possible to erase data in a NAND-type EEPROM by using an erase voltage lower than that of the prior art, and to realize a non-volatile memory capable of miniaturizing elements, improving reliability and improving yield. Another object of the present invention is to provide a nonvolatile semiconductor memory device.

[0017]

According to one aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising: a plurality of electrically rewritable memory cells connected in series; and a bit line side of the plurality of memory cells. A non-volatile memory comprising a NAND-type memory cell column including a first select gate transistor provided at one end and a second select gate transistor provided at the other end on the source line side of the plurality of memory cells. In a semiconductor memory device, when writing to a selected memory cell in a selected NAND-type memory cell column, a low voltage is applied from a bit line to the selected NAND-type memory cell column. Unselected N sharing control gate electrode with selected NAND type memory cell column
A high voltage is applied from a bit line to the AND memory cell column, and the potential of the channel region is floated. The selected NAND memory cell is connected to the control gate electrode of the selected memory cell. A first voltage is applied such that a potential difference between the column and a channel region in the column is sufficient for writing data, and a control gate electrode of at least one of memory cells adjacent to the selected memory cell is applied. In addition, the channel potential of the memory cell which is sufficient to turn on the memory cell in the normally-OFF state and which shares the control gate electrode with the selected memory cell in the unselected NAND type memory cell column is Wherein a second voltage enabling selective self-boosting is applied.

A nonvolatile semiconductor memory device according to another aspect of the present invention is provided with a plurality of electrically rewritable memory cells connected in series and one end on the bit line side of the plurality of memory cells. A first select gate transistor;
A NAND comprising a second select gate transistor provided at the other end of the plurality of memory cells on the source line side
A non-volatile semiconductor memory device including a memory cell column of a selected type, wherein when writing data to a selected memory cell of a selected column of a NAND type memory cell,
An unselected NAN sharing the control gate electrode between an AND type memory cell column and the NAND type memory cell column
For a D-type memory cell column, at least from a bit line to at least the selected memory cell and a channel region of a memory cell of an unselected NAND-type memory cell column sharing the control gate electrode with the selected memory cell. The bit line potential is transmitted, the channel region of the non-selected NAND memory cell column is floated, the potential of the control gate electrode in the selected NAND memory cell column is raised to a predetermined level, and the capacitive coupling is performed. As a result, the potential of the channel region in the non-selected NAND type memory cell column is self-boosted, and the potential difference between the self-boosted potential of the channel region and the control gate electrode potential of the memory cell adjacent to the selected memory cell is used. The adjacent memory cell and the control gate electrode in the non-selected NAND memory cell column. After the shared memory cell is turned off and the memory cell is turned off, the channel potential of the memory cell of the non-selected NAND memory cell column sharing the control gate electrode with the selected memory cell is finally adjusted. It is characterized by being boosted to a potential.

A nonvolatile semiconductor memory device according to still another aspect of the present invention includes a plurality of electrically rewritable memory cells connected in series and one end of the plurality of memory cells on a bit line side. And a second select gate transistor provided at the other end on the source line side of the plurality of memory cells.
A nonvolatile semiconductor memory device including an AND-type memory cell column, wherein when erasing data of a selected memory cell in the NAND-type memory cell column, the NAN
In the D-type memory cell column, the first voltage is transmitted from the bit line to the channel region of the memory cell between at least the selected memory cell and the second selection gate transistor, and the potential of the channel region is in a floating state. And the second control gate electrode of the selected memory cell
Are applied to the control gate electrodes of the non-selected memory cells, respectively. In this case, the polarity of the second voltage is opposite to the polarity of the first and third voltages. It is characterized by the following.

[0020]

Embodiments of the present invention will be described below with reference to the drawings.

First, before specifically describing the embodiments of the present invention, an existing technology as a base thereof will be described from the viewpoint of facilitating understanding of the present invention.

The present invention relates to the self-boosting method of KDSuh et al. And the selective self-boosting method of TSJung et al.
oosting), which form part of the present invention. Therefore, in order to understand the present invention, it is indispensable to understand these conventional techniques. First, these two self-boosting methods will be described.

FIG. 6 is an explanatory diagram showing a write method in the self-boosting method of KDSuh et al. FIG. 7 is a diagram showing the timing of the voltage applied to each part at the time of writing.

As shown in FIG. 6A, 0 V is applied to the selected bit line BL1, and the unselected bit line BL2 is applied.
Is applied with 3.3V. At a timing t1 in FIG. 7, the selection gate SG1 of the drain-side selection transistor is selected.
Is raised from 0 V to 3.3 V to turn on the transistors, and the memory cell columns are connected to the bit lines BL1 and BL2, respectively. On the other hand, 0 V is applied to the source side select gate SG2 to turn off the select transistor, thereby disconnecting the connection between the memory cell column and the common source line CSL. As a result, the channel potential Vch of the cell column between the two select transistors SG1 and SG2 is uniformly 0 V in the selected cell column connected to the bit line BL1. On the other hand, 3.3 V is supplied to the unselected cell columns from the bit line BL2.

Incidentally, regarding such a write operation,
The term “unselected” in terms such as “unselected bit line” and “unselected cell column” is synonymous with prohibition of “0” writing in which the threshold value of a cell is shifted positively, and The same applies to the description.

Returning to FIG. 6A, the writing in the selected cell column will be described. A high voltage Vpgm (for example, 18 V) for writing is applied only to the control gate electrode 16 of the selected cell. In the state of the selected cell (state A), as shown in FIG. 6B, the control gate electrode is 18 V and the channel potential is 0 V. Here, when the coupling ratio of the cell is 0.6, the potential difference between the floating gate electrode 14 and the semiconductor substrate 11 becomes 11 V, and electrons are injected into the floating gate electrode 14 through the tunnel oxide film, and the threshold voltage of the cell is reduced. Becomes positive, and “0” is written to the selected cell. For the non-selected cells in the selected cell column, the control gate electrode 16 applies an intermediate potential (Vpass, for example, 1).
0V). As described above, the coupling ratio is set to 0.
Therefore, the potential difference between the floating gate electrode 14 and the semiconductor substrate 11 is 6 V. At this potential, writing by injection of a tunnel current is not performed within a normal writing time. Therefore, no writing is performed on cells other than the selected state A.

On the other hand, a write operation is prohibited in the NAND cell column connected to the unselected bit line BL2 as follows. As described above, 3.3 V (power supply voltage Vcc) is applied to the unselected bit line BL2. FIG.
At time t1, SG1 changes from 0V to Vcc = 3.3V
, The selection transistor is turned on, and a 3.3 V potential is supplied from the bit line to the cell column connected to the bit line BL2. If all data in this NAND cell row is "1", that is, normally ON, the channel potential Vch of all cells in the cell row becomes Vch = Vcc-Vths, where Vths is the threshold value of the selection gate SG1. After that, the selection gate SG1 is turned off. That is, V
Assuming that cc = 3.3 V and Vths = 1.3 V, the channel potentials of all the cells in the non-selected cell row are Vch = 3.3-1.
3 = 2V. Thus, as shown at the bottom of FIG. 7, the channel potential (eg, N2, N2 ′ in FIG. 6A)
Is charged to 2 V between time t2 and time t3. On the other hand, since the selection gate SG2 is OFF (the voltage of SG2 is 0) as shown in FIGS. 6A and 7, at this time, the channel potential Vch (source / drain) of the non-selected NAND cell row The potential of the region and the inter-cell diffusion layer is in a floating state. After the channel potential becomes a floating state in this way, the voltage of the control gate rises to the write voltage (Vpgm = 18V) or the intermediate potential (Vp = 10V) between t3 and t4. At this time, since the channel potential is in a floating state, the voltage applied to these control gates causes the channel potential to change from the initial value of 2 V to 8 V, as is apparent from the potentials of N2 and N2 'shown in the bottom row of FIG. (State B in FIG. 6C). The magnitude of this self-boosting is determined not by Vpgm = 18V but by Vpass = 10V. Because, for example, when 16 memory cells are connected in series to form a NAND cell row, Vpgm = 18V is applied to only one control gate, and the other 15 control gates Are all applied with Vpass = 10V,
This is because the influence of pass = 10 V is overwhelmingly large.

As a result of the self-boosting, as shown in the state B of FIG. 6C, in the non-selected NAND cell row, the write voltage Vpgm applied to the control gate electrode 16 is 18 Vg.
The potential of the floating gate electrode 14 is about 11 V (18 V ×
0.6), the voltage applied to the tunnel oxide film between the substrate and the floating gate electrode 14 is only 3 V.
As a result, a tunnel current does not flow and writing in the non-selected NAND cell row is prevented.

Further, in the cells other than the state B in the non-selected NAND cell row, the voltage of the control gate electrode 16 is Vpass = 1.
0 V, and the voltage of the floating gate electrode 14 is 6 V (10 V × 0.
6) Since the channel potential is about 8 V, the potential difference applied to the tunnel oxide film is 2 V, and no writing occurs.

As is clear from the above description, KDSuh
According to the self-boosting method of et al., the following advantages can be obtained.

The amplitude of the bit line potential, which was conventionally 0V → VM (for example, 10V), is changed to 0V → Vcc (3.3V).
Can be reduced to Therefore, the withstand voltage of various transistors for driving the bit lines can be reduced, and the transistors can be further miniaturized. In addition, the area of the sense amplifier and the like and the chip size can be reduced.

The intermediate potential generating circuit for the bit line voltage can be omitted, which leads to a reduction in chip size.

However, the self-boosting write method by KDSuh et al. Has the following drawbacks.

When writing after all NAND cells have been erased in advance, the channel potential is sufficiently boosted when the control gate voltage rises during the period from t3 to t4 in FIG. However, in the case of self-boosting in a state where the threshold value of the cell transistor is increased to a positive value after the cell has been written in advance, Vpass and Vpgm become the threshold values after the cell is written between t3 and t4. When the voltage exceeds (for example, +1 V) and all the cell transistors of the same NAND type cell row are turned on, the channel portion becomes a floating state and the bootstrap is activated. Therefore, Vch after channel boosting is lower than Vch after erasing. This will be described below.

The power supply voltage is Vcc, the threshold value of the memory cell is Vth, the threshold value of the selection gate is Vths, the write voltage is Vpgm, and the intermediate potential (write inhibit voltage) is Vpass. The potential Vch of the channel after Vpgm and Vpass are respectively increased from 0 V is: Vch = Vchφ + (β / 16) [(Vpgm−Vth−Vchφ) +15 (Vpass−Vth−Vchφ)] (1) , Vchφ = Vcc−Vths (2)

Here, β is a quantity representing the ratio of the channel potential to the control gate potential, and is described by KDSuh et al. (IEEE Journal of Solid-State Circuits, vol. 30, N.
O.11 (1995)), Vch = [Cins / (Cins + Cchannel)] Vwl (3) β = [Cins / (Cins + Cchannel)] (4)

Usually, the value of β is about 0.8. Here, Cins is the total capacitance between the control gate and the channel, and 1 / Cins = 1 / Cono + 1 / Ctunnel (5) where Cono: the capacitance of the inter-insulating film between the floating gate and the control gate, Ctunnel: It is given by the capacitance between the tunnel oxide films (see FIG. 8). Cchannel is the capacitance between the channel and the substrate, and Vwl is the potential of the control gate.

Using the above equation (1), when Vch is calculated for each of the case where the cell threshold value is -1 V and the case where the cell threshold value is +1 V, Vch = 9.7 V (Vth = -1 V) (6a) Vch = 8.1V (Vth = + 1V) (6b) However, in this calculation, Vcc = 3.3 V, Vth
s = 1V, β = 0.8, Vpgm = 18V, Vpass = 10
V, Vth = −1 / + 1V. In this condition,
Vchφ = 3.3-1 = 2.3V.

Based on the above results, all 16 cells were erased and the threshold value became -1 V, and data was written in all 16 cells and the threshold value became +1 V. The comparison with time is as follows.

As shown in FIG. 9, the threshold value of all cells is-
In the case of 1V, the potential Vch of the channel of the NAND cell column connected to the unselected bit line is 9.7V. On the other hand, when the threshold values of all the cells are +1 V, the potential Vch of the channel of the NAND cell column connected to the unselected bit line is 8.1.
V. The difference between the two is 1.6 V (= 9.7 V-8.1).
V), as shown in FIG. 9, the difference between Vch and Vpgm is larger in the case of Vth = + 1 V, and the stress of the cell in the state A is larger than in the case of Vth = -1 V. Recognize. That is, when the threshold value of all cells is -1 V, V
The pgm stress is 8.3V, but the threshold of all cells is +
At 1 V, the Vpgm stress increases to 9.9 V. This is because the boosted magnitude of the channel potential Vch differs depending on the threshold value of the cell. As a result, when data is written to the selected cell in the selected NAND cell row, Vpgm
Means that the reliability of write prohibition decreases.

As a method for improving the disadvantages of the self-boosting writing method described above, TSJung et al. Devised a Local Self-Boosting (LSB) system in which self-boosting is selectively performed to perform writing to reduce Vpgm stress. , In particular, has a great effect on the threshold variation of multi-valued cells (TSJung
et al., ISSCC Tech. Dig., p.32, 1996).

In this LSB system, as shown in FIG. 10, Vpgm (for example, 20 V) is applied to the control gate of the selected cell, but two control gates adjacent to the control gate of the selected cell are applied to the control gate of the selected cell. Apply Vdcp (0V). An intermediate potential Vpass (for example, 11 V) is applied to the other control gates. As a result, the two cell transistors Qd1 and Qd2 to which Vdcp is input are turned off, and the NAN
The D-type cell column is divided into three channel regions 1, 2, and 3 (regions indicated by potentials Vch1, Vch2, and Vch3, respectively). Channel region 1 in unselected NAND cell row
In No. 3, the potentials Vch1 and Vch3 of the channel portion are self-boosted to 7V by the intermediate potential Vpass (for example, 11V) applied to the control gate of the cell transistor according to the mechanism described above. On the other hand, the potential Vch2 of the channel region 2 in the cell of the non-selected NAND cell row sharing the same control gate as the selected cell, that is, the "1" holding cell Qs, is also changed to the voltage Vpgm (2
0V). However, in this case, since the adjacent cell transistors Qd1 and Qd2 are off, unlike the case of KDSuh et al.
It is not affected by self-boosting in the channel regions 1 and 3. Therefore, the potential Vch2 of the channel region 2 becomes Vpass
By the higher voltage Vpgm (20 V), the voltage is self-boosted even more than the voltages (Vch1, Vch3) of the other channel regions 1 and 3, and rises to about 10V (FIG. 11). In other words, only the channel potential of the “1” holding cell is higher than the other channel potentials.
ting) occurs. The reason is, as mentioned earlier,
Cell transistors on both sides of "1" holding cell Qs are off
This is because the "1" holding cell Qs is not affected by Vpass and is only subjected to self-boosting by Vpgm.

This will be further described below in comparison with the conventional self-boosting method. That is, FIG.
As shown in FIG. 2, in the conventional self-boosting method, the channel portion is uniformly self-boosted, and its channel potential becomes 7V.
On the other hand, in the selective self-boosting system, as shown in FIG.
As a result, in the conventional self-boosting system, the stress applied to the cell is Vpgm-Vch1 = 20-7 = 13 V, whereas in the selective self-boosting system, Vpgm-Vch2 = 20-1.
0 = 10V. Therefore, the selective self-boosting method reduces the stress by as much as 3 V, so that it can be said that the method is more reliable in prohibiting writing by Vpgm in the non-selected NAND cell row.

However, this selective self-boosting method has the following problem when writing in a selected NAND cell row. In the selected NAND cell row, the bit line is at 0 V as described above, and this 0 V must be transmitted to the selected memory cell to be written. That is, when writing to a selected cell surrounded by a circle in FIG. 10, writing to the selected cell cannot be performed unless all cells between the selected cell and the bit line BL1 are in the ON state. on the other hand,
In the above-described selective self-boosting method, Vdcp = 0 V is applied to cells on both sides of the selected cell. Therefore, if the adjacent cell is in a normally depressed normally ON state (threshold value is minus), 0 V of the bit line BL1 is transmitted to the selected cell to perform writing. However, if the adjacent cell is in the normally-off state where the enhanced state is set (the threshold value is positive), the 0 level of the bit line BL1 is
V does not reach the selected cell, and writing is not performed. Therefore, in the above-described selective self-boosting method, the selected N
When data is sequentially written to a plurality of cells in an AND-type cell row, the writing order must be written in order from the source side of the cell (far from the bit contact) to the cell closer to the bit line. There are restrictions.

An embodiment of the present invention will be described below based on the above description.

[Embodiment Based on First Aspect of the Present Invention] First, first to fifth embodiments based on the first aspect of the present invention will be described. Here, a description will be given mainly of a write processing technique in the NAND type EEPROM.

FIG. 13 is a diagram showing N according to the first embodiment of the present invention.
FIG. 3 is a diagram illustrating voltage control of an AND-type EEPROM. It should be noted that a plan view, an equivalent circuit diagram, a vertical cross-sectional view, and a horizontal cross-sectional view of this embodiment are the same as those shown in FIG.
(A), FIG. 1 (B), FIG. 2 and FIG. 3, so please refer to these drawings.

As shown in FIG. 13, Vpgm (eg, 2 pgm) is applied to the control gate of the selected memory cell indicated by a circle.
0V), and a control gate of a memory cell adjacent to the selected memory cell is supplied with a voltage Vdcp (for example, 4.5 V) lower than Vpass described below. And
Vpass (for example, 11
V). The important thing here is that TSJung et a
In this embodiment, a positive voltage Vdcp = 4.5 V is applied, while Vdcp = 0 in the selective self-boosting method of l.

By controlling the voltage as described above,
For unselected NAND cell strings, TSJung et al.
A write inhibit operation similar to the selective self-boosting method described above can be obtained. That is, after Vcc (3.3 V) -Vth is supplied from the bit line, the selection transistor SG1 is turned off and KD
Self-boosting occurs as in Suh et al. at the same time,
The cell to which Vdcp = 4.5 V is applied is turned off because the potential of the control gate electrode becomes lower than the channel potential. As a result, the channel portion is divided into three channel regions 1, 2, and 3 (regions indicated by potentials Vch1, Vch2, and Vch3, respectively) as in the case of TSJung et al. (See FIGS. 13 and 14). The channel region Vch2 of the memory cell holding “1” self-boostes as Vpgm rises from 0V to 20V because the adjacent cell is in the OFF state, and changes from 0V to 10V. The state of this boost,
FIG. 21 is a timing chart. On the other hand, Vch1 and Vch3 change the potential of Vpass (11V) from 0V to 11V.
As the voltage rises to V, the voltage rises to 7V. Therefore, the channel voltage Vch2 of the “1” holding cell is Vc
It becomes higher than h1 and Vch3. As a result, Vpgm-Vch
The potential difference of 2 is also smaller than the self-boosting method of KDSuhet al., And the stress applied to this cell is reduced.

On the other hand, in the selected NAND cell row, as described below, even if there is a cell already written in the cell row, writing can be selectively performed without any problem.

In the case where writing is performed in a cell surrounded by a circle in FIG. 13, the selection gate SG1 is opened and the bit line BL is opened.
When it is connected to 1, the potential of the channel portion of this NAND cell row becomes 0 V uniformly as shown by the broken line in FIG.
In this case, the problem with the selective self-boosting method of TSJung et al. Is that Vdcp = 0 as described with reference to FIG.
V, the adjacent unselected cell 1 is normally OFF.
In this case, the adjacent cell 1 is turned off, and the voltage of the bit line BL1 is not transmitted to the selected cell. On the other hand, in this embodiment, as shown in FIG. 14, Vdcp = 4.5 V higher than the threshold value of the cell written in the normally OFF state is applied to the adjacent unselected cells 1 and 2 as well. ing. Therefore, even if the adjacent cell 1 is written in the normally OFF state, the adjacent cell 1 is turned ON, and the 0V of the bit line BL1 is turned on.
To the channel region of the selected cell. As a result, in the selected cell, the control gate potential V
Desired writing can be performed by a potential difference (20 V) between pgm = 20 V and channel potential Vch = 0 V. The control gates of the other cells are
Since pass = 11V is applied, even if it is normally O
It goes without saying that even if the data is written in the state of the FF, it is turned on and does not hinder the writing in the selected cell.

In the above example, the case where the gate potential Vdcp of the cell on both sides of the selected cell is 4.5 V has been described. However, a desirable value of Vdcp is not limited to this value.
As will be described later, the distance may be within a predetermined range. Hereinafter, the lower limit value Vdcpmin and the upper limit value Vdcpmax of the desirable range of Vdcp will be described.

First, the lower limit value Vdcpmin will be described.

At the time of writing, in order for the potential Vchφ (2.3 V) on the “H” side on the bit line to propagate without lowering the threshold value, Vdcp is determined as follows: Vdcp> Vchφ + Vths (7) where Vchφ = 2 0.3 V, Vths = 1 V (8) Thus, the lower limit value Vdcpmin = 3.
3V can be obtained. Note that the lower limit value Vdcpmin may be set to 2 V if a slight drop in the threshold value is allowed.

Next, the upper limit value Vdcpmax will be described.

Here, a case of a NAND cell structure in which 16 cells are connected in series is considered. As described above, the power supply voltage is Vcc, the threshold of the memory cell is Vth,
The threshold of the select gate is Vths, the write voltage is Vpgm,
The description will be made on the assumption that the intermediate potential (write inhibit voltage) is Vpass.

First, the potential Vch of the channel region after Vpgm and Vpass are respectively increased from 0 V is calculated below. In the following calculation, for simplicity, it is assumed that Vdcp is a constant value independent of time (actually, Vdcp
dcp slightly changes according to modified examples such as the second to fourth embodiments described later in addition to the first embodiment, but the approximate tendency can be determined by the following calculation.)

The initial values of Vpgm and Vpass are set to zero (time t = 0). It is assumed that t = 1 when Vpgm and Vpass reach the final write voltage. Therefore, 0 <t
<1 indicates an intermediate state.

At time t, the voltage Vch (t) of the channel in the NAND cell is as follows: Vch (t) = Vchφ + (β / 14) [(tVpgm−Vth−Vchφ) +13 (tVpass−Vth−Vchφ)] ( 9) Here, Vchφ = Vcc−Vths (10)

In the above equation (9), of the 16 memory cells, the two cells to which Vdcp is applied do not contribute to booting, and the remaining 14 cells contribute to booting. It is assumed that

For example, Vpgm = 18V, Vpass = 10
V, β = 0.8, Vchφ = 2.3 (V) = 3.3 (V)
Assuming −1 (V), from equation (9), Vch (t) = 8.457t−0.8Vth + 0.46 (V) (11) is obtained. While t is small, the two cells to which Vdcp is applied to the gate (cells on both sides of the selected cell) are also in the ON state. Therefore, the channel potential Vch (t) increases as Vpgm and Vpass increase, and takes the same value over the entire channel. However, the potential Vch (t) of this channel is Vdc
At the moment when p-Vthx (Vthx is Vth of the adjacent control gate), the cells on both sides of the selected cell are turned off, the channel of the selected cell and the channel of the other cell (non-selected cell) are turned off, and the entire channel is turned off. Self-boosting ends at
Thereafter, the channel of the selected cell is selectively self-boosted, and its potential rises. The channels of the non-selected cells are self-boosted, but have a potential lower than the potential of the selectively self-boosted channel.

Here, when the condition of Vch (t) = Vdcp-Vthx is substituted into the equation (11), the following is obtained: Vdcp-Vth = 8.457t-0.8Vth + 0.46 (12)

In practice, it is conceivable that the threshold value Vth of a non-selected cell takes various values, and the calculation becomes enormous in all the states. Hereinafter, for simplicity, only the case where Vth of the unselected cell is -1 V (erased state) and +1 V (written state) will be considered.

When t is derived from the above equation (12), t = (Vdcp−0.2Vth−0.46) /8.457 (13) is obtained. However, Vth = Vthx = ± 1V.

In the above equation (13), Vth = + 1
When (V), t = (Vdcp−0.66) /8.457 (14a) On the other hand, when Vth = −1 (V), t = (Vdcp−0.26) /8.457 ( 14b).

In the above equation (14a), for example, Vdc
When p = 4.5V, t = tc = 0.45 (Vth = + 1V) (15), and Vch at this time tc is Vch (tc) = 3.47V (16).

On the other hand, in the above equation (14b), for example, when Vdcp = 4.5V, t = tc = 0.50 (Vth = −1V) (17), and Vch at time tc is Vch ( tc) = 5.49V (18)

As described above, the time tc, that is, the time t
At about half of the final value 1 (0.45 to 0.5), the self-boosting changes to the selective self-boosting. In other words, when 0 <t <tc, a self-boosting state is established,
The channel of the selected cell and the channel of the unselected cell are connected, and self-boosting is performed at the same potential. On the other hand, tc <t <
At 1, the channel of the selected cell is disconnected from the channel of the non-selected cell, the channel of the selected cell is in a selective self-boosting state, and the non-selected cell is in a self-boosting state. From the above equations, it can be seen that tc increases as Vdcp increases, and tc decreases as Vdcp decreases.

As described above, at the time of tc <t <1, the manner of the subsequent boosting differs between the channel region of the selected cell and the channel region of the non-selected cell. The state of boosting of the channel of the non-selected cell is expressed by the following equation (19). The state of boosting the channel of the selected cell is expressed by the following equation (20).

Vchn = Vch (1) = Vch (tc) + (1-tc) βVpass (19) Vchs = Vch (1) = Vch (tc) + (1-tc) βVpgm (20) For example, Vdcp Vchn = 7.5V (Vth = + 1V) (21a) Vchn = 9.5V (Vth = -1V) (21b) Vchs = 10.7V (Vth = + 1V) (22a) Vchs = 12.7V (Vth = 1V) (22b)

The theoretical upper limit (maximum value) that Vdcp can take is a condition under which selective self-boosting occurs immediately before tc = 1. Therefore, when tc = 1 is substituted in the equations (14a) and (14b), Vdcpmax = 9.1V (Vth = + 1V) (23a) Vdcpmax = 8.7V (Vth = -1V) (23a) . In other words, when Vpgm or Vpass reaches the final value, switching between self-boosting and selective self-boosting (tc = 1) corresponds to the upper limit value (maximum value) Vdcpmax of Vdcp. Vdcpmax is calculated by the above equation (23a), (23
If the lower value of the expression b) is adopted, the value becomes 8.7V. Considering that Vpass is 10V, Vdcpmax
Is lower than the voltage value Vpass.

As a result, the theoretical range that Vdcp can take is 2.0V <Vdcp <8.7V (24).

Hereinafter, Vdcp is 3.5 V, 4.5 V, 6
FIG. 15 is a table showing the results of calculating the potential of the channel in the NAND memory cell in the case where t ranges from 0 to 1 for the four cases of V and 8V. FIGS. 16 to 19 show graphs thereof.

The horizontal axes of the graphs in FIGS. 16 to 19 indicate t, and the vertical axes indicate Vpgm, Vpass, and Vch (Vchs and Vchn). Vchs (+1) indicates the channel potential of the selected cell when Vth = 1V, and Vchs (-1) indicates Vt
It shows the potential of the channel of the selected cell when h = -1V. Vchn (+1) indicates the potential of the channel of the unselected cell when Vth = 1V, and Vchn (-1) indicates Vth = -1.
The potential of the channel of the non-selected cell at V is shown. tc (-
1) shows a time at which the self-boosting and the selective self-boosting are switched when Vth = -1 V, and tc (+1) is Vth = +
The time at which the voltage is switched between self-boosting and selective self-boosting at 1 V is shown.

As can be seen from FIGS. 16 to 19, Vdcp
= 3.5V (FIG. 16) and Vdcp = 4.5V (FIG. 17), the selective self-boosting potential Vchs is equal to the self-boosting voltage of the non-selected cell regardless of whether Vth is -1V or + 1V. It is higher than the potential, and the effect of the present invention is clearly shown. However, as Vdcp increases, the difference between the selective self-boosted potential of the selected cell and the self-boosted potential of the non-selected cells becomes narrower, and the effect of the present invention does not appear. In particular, it can be seen that when Vdcp = 8 V, almost only self-boosting occurs.

Therefore, it can be said that the practical range in which the effect of the present invention is exhibited is 3V ≦ Vdcp ≦ 6V.

As is clear from the above description, according to this embodiment, by applying Vdcp of an appropriate value as described above to the gates of the cells on both sides of the selected cell, the selected NAND type is applied. After randomly writing data to cells in the cell column, even if the next cell to be written is located on the source side of the already written cell, the potential 0V of the bit line BL1 is selected. Of the control gate potential Vpg
m can be written.

As apparent from the above description, in order to obtain the effect of the first embodiment, of the two non-selected cells adjacent to the cell selected to write "0", the bit line Only the cells on the side need to be conductive. That is, writing to the selected cell is achieved even if the adjacent cell on the source side does not conduct. Therefore, as a modification of the first embodiment, as shown in FIG. 20, Vdcp is applied only to the unselected cell 1 adjacent to the bit line side, and 0 V is applied to the unselected cell 2 adjacent to the source side. It may be configured as follows. Further, a configuration may be adopted in which a positive voltage lower than Vdcp is applied to the non-selected cells 2 on the source side.

Next, a second embodiment of the present invention will be described with reference to FIG. This embodiment is different from the first embodiment in the voltage control timing, but the basic operation principle is the same as the first embodiment.

First, during the period from t0 to t1, the gate voltage of the selection transistor SG1 is set to 3.3V. Thereby, the potentials (Vch1, Vch2, Vch3) of the channel portion of the non-selected NAND cell row are charged to about 2V.
In the period from t1 to t2, the potentials of Vpgm, Vpass, and Vdcp are increased from 0V to 4.5V. This allows
4.5 V is applied to all the control gates of the eight memory cells. Further, the potential of the channel portion is raised to about 3V. After t2, Vpass is changed from 4.5V to 11V.
And raise Vpgm from 4.5V to 20V. As a result, the channel Vch2 of the “1” holding cell becomes 10V. This is because, at the timing after t2, the memory cell adjacent to the “1” holding cell has a self-boosted channel potential higher than the voltage applied to the control gate (Vdcp = 4.5 V), and is turned off. It is. The potentials (Vch1, Vch3) of the other channel portions also rise to 7V. This final potential relationship is the same as the potential relationship in FIG. 20 in the first embodiment. As a result, similarly to the first embodiment, the write prohibition in the non-selected NAND cell row is achieved.

Also, writing in the selected NAND cell row can be performed at random, as described in the first embodiment.

Next, a third embodiment will be described with reference to FIG. This embodiment also differs from the first embodiment in the voltage control timing, but the basic operation principle is the same as the first embodiment.

In the period from t1 to t2, Vpgm, Vpass, Vdcp
To 11V. At this time, the potential V of the channel portion
ch1, Vch2 and Vch3 rise to 7V. At time t2, only Vdcp is reduced from 7V to 4.5V, and "1"
The cell transistor adjacent to the holding cell is turned off.
At t2, Vpgm is increased from 11V to 20V. Thereby, the channel potential Vch of the “1” holding cell is
Only 2 is boosted to 10V.

Also in this case, since the final potential relationship is the same as in the first embodiment, writing is prohibited in the non-selected NAND cell column and writing in the selected NAND cell column is performed in the same manner as in the first embodiment. Will be

Next, a fourth embodiment will be described with reference to FIG. This embodiment also differs from the first embodiment in the voltage control timing, but the basic operation principle is the same as the first embodiment.

In the period from t0 to t1, the selection gate S
The potential of G1 is set to a potential higher than Vcc (Vcc + Vths or more,
For example, 4.5 V). In this case, the selection gate SG1
And the potential of the bit line BL1 becomes V
cc, Vcc is applied to the channel portion of this NAND cell row.
(For example, 3.3 V) is transmitted.

During the period from t1 to t2, Vpgm is set to 0V
To a high voltage (for example, 20V), Vpass is raised from 0V to 11V, and Vdcp is raised from 0V to 4.5V. As a result, Vch1 and Vch3 rise to 7V, and Vch2 rises to a high value exceeding 10V. As described above, the drop in the threshold voltage (for example, 1.0 V) due to the selection gate transistor can be eliminated, and the voltages of Vch1, Vch2, and Vch3 can be further increased, so that the possibility of erroneous writing can be further reduced. .

In the period from t2 to t3, in this embodiment, the potential of the selection gate SG1 is reduced from 4.5V to 3.3V. This is for the following reason. That is,
During this period, the channel portions Vch1 and Vc of the memory cell
Since the potentials of h2 and Vch3 are self-boosted higher than in the first to third embodiments, if the potential of the bit line drops even slightly due to noise or the like, leakage from the floating channel portion to the bit line occurs. There is a possibility that a current flows and the potential of the channel portion drops to cause erroneous writing. To prevent this, the potential of SG1 is lowered to make it difficult for a leak current to flow.

FIG. 25 shows the voltage control timing in the fifth embodiment of the present invention. In this embodiment, as in the fourth embodiment, the potential of the selection gate SG1 is set to a potential higher than Vcc (V
(cc + Vths or more, for example, 4.5 V). Therefore, the threshold value does not drop due to the selection gate SG1, and the bit line B
Since the potential of L1 is Vcc, Vcc (for example, 3.3 V) is transmitted to the channel portion of this NAND cell row.

In the period from t1 to t2, the potential of SG1 is reduced to 4.5V to 3.3V. The reason is the same as in the fourth embodiment.

During the period from t2 to t3, Vpgm is set to 0V
To a high voltage (for example, 20V), Vpass is raised from 0V to 11V, and Vdcp is raised from 0V to 4.5V. As a result, Vch1 and Vch3 rise to 7V, and Vch2 rises to a high value exceeding 10V. As a result, electrons are injected into the selected memory cell to perform writing, and the non-selected cells are in a write-inhibited state.

In the above-described embodiment, for any of the two memory cells adjacent to the selected memory cell, Vdcp lower than Vpass is applied to their control gate electrodes.
Has been described to be in the OFF state by applying
The present invention is not limited to this. That is, in the present invention, a voltage that allows the use of the selective self-boosting method for partially self-boosting the channel region of the memory cell column may be applied to the control gate electrodes of two adjacent memory cells. For example, apply Vdcp to one and Vpas to the other
s may be applied. However, from the viewpoint of boosting only the channel of the “1” holding cell in which Vpgm is applied to the control gate electrode higher than the other channel regions, Vdcp is applied to the gate electrode of any two adjacent cells. Is preferably turned off by applying.

[0093] Regarding the embodiment based on the first aspect of the present invention described above, the following modified examples can be considered.

At the time of reading, the voltage Vdcp
May be the same as the voltage applied to the control gate electrodes of the memory cells other than the selected memory cell in the selected NAND type memory cell column. The voltage at this time is a voltage for turning on both the normally ON memory cells and the normally OFF memory cells, and the 0 V potential of the bit line selected at the time of writing is set to the channel of the selected memory cell. This is the voltage that will be properly sent to the area.

The voltage Vdcp may be the same as the power supply voltage. In this case, there is an advantage that it is not necessary to generate a new voltage as the voltage Vdcp.

When one of the adjacent cells on both sides of the selected cell is the selection transistor S1, the gate voltage of the other adjacent cell is 4.5V (= Vdcp) even if it is 0V.
Or a positive voltage lower than Vdcp.
This is because it is not necessary to supply 0 V to the selected cell through the adjacent cell on the selected NAND cell column side. When one of the adjacent cells on both sides of the selected cell is the selection transistor S2, the gate voltage of the adjacent cell is desirably Vdcp to turn on the other adjacent cell.

[Embodiment Based on Second Aspect of the Present Invention] Next, sixth and seventh embodiments based on the second aspect of the present invention will be described. Here, a description will be given mainly of the erasing processing technology in the NAND type EEPROM.

FIGS. 26, 27 and 28 are diagrams showing the voltage control of the NAND type EEPROM according to the sixth embodiment of the present invention. A plan view, an equivalent circuit diagram, a longitudinal sectional view, and a transverse sectional view of this embodiment are the same as those shown in FIGS. 1A, 1B, 2 and 3 referred to in the description of the prior art. Please refer to these drawings.

As shown in FIG. 26, 3.3 V is applied to a bit line BL1 connected to a selected NAND cell row including a selected cell from which data is to be erased, and to other unselected bit lines BL2. Applies 0V.

First, the NAN connected to the bit line BL1
Data erase in a selected cell and data retention in an unselected cell in a D-type cell row will be described. FIG.
In a period t1 of 7, as shown in FIG. 27, the selection gate SG1 and the control gates CG1 to CG8 are precharged to Vcc (for example, 3.3 V). On the other hand, select gate S
0 V is applied to G2, and the selection transistor SG2 is turned on by O.
Let it be FF. At this time, as shown in FIG. 27, the potential VCHN of the channel portion is Vcc-Vths (Vths is about 1 V as the threshold value of the selection transistor), that is, 3.3-1 = 2.
3V and the selection gate SG2 is OFF,
The channel portion is in a floating state.

Then, during the period of t2, as shown in FIG. 26, -10 V is applied to the control gate CG6 of the selected cell, and the control gates G1 to G5, G7 to G of the non-selected cell are applied.
To +8, + 10V is applied. At this time, the erase voltage -10V
Is applied to the control gate, the selected cell is turned off. However, since the channel portions on the source side and the drain side of this selected cell are both in a floating state, the voltage of 10 V applied to the control gate of the unselected cell causes One channel unit self-boosts to about 9V. Since the self-boosting has already been described in detail, the description is omitted here. Note that the channel portion on the drain side of the selected cell does not necessarily have to be in a floating state.
The voltage applied to 1 may be, for example, 4.5V.

As a result, the control gate of the selected cell is -10 V, and at least one of the source and the drain is 9
V between the gate and the source / drain
A voltage of 19 V is applied which is sufficient to generate a tunnel current between the floating gate electrode and the source / drain. Therefore, the electrons stored in the floating gate electrode are
It is emitted from the floating gate electrode as a tunnel current. As a result, the threshold value of the selected memory cell becomes negative (for example, -2 V), and the data is erased instead of the normally ON state.

On the other hand, in a non-selected cell, since the potential of the control gate is +10 V and the potential of the channel is +9 V, only a potential difference of +1 V is applied between the gate and the substrate.
Therefore, no tunnel current flows and the threshold value of the memory cell remains in the initial state.

Next, data retention in another NAND cell row sharing the control gate electrode with this NAND cell row will be described.

As shown in FIG. 26, the bit line BL2 is set to 0V, the potential of the selection gate SG1 is set to Vcc = 3.3V,
When all the control gates are set to 3.3 V, t1 in FIG.
During the period, all the potentials of the channel portion become 0V. FIG.
In the period t2 of FIG. 8, as shown in FIG. 26, while applying the erase voltage -10 V to the control gate CG6,
+10 V is applied to the other control gates CG1 to CG5 and CG7 to CG8. Thereby, the selected NAND
As in the case of the type cell row, the cell transistor in which the erase voltage is applied to the control gate electrode is turned off. Therefore, as shown in FIG. 26, the channel region is the channel region 1 (potential VCHN1) and a channel region 2 (a region indicated by the potential VCHN2) between the control gate CG6 and the selection gate SG2. Since the selection gate SG1 is ON, the channel region 1 on the drain side is connected to the bit line BL2, and the potential VCHN1 is always 0 as shown in FIG.
Keep V. On the other hand, the source side channel region 2 is shown in FIG.
Is turned off, the potential V
CHN2 is in a floating state. Therefore, when the potential of the control gate electrode of the unselected cell becomes +10 V, as shown in FIG. 28, the potential VCHN2 of the channel region 2 is 0 to 5 V
(For example, 3 V). As a result, in this NAND cell row, the potential difference between the control gates of CG1 to CG5 and the channel is 10 V, and the potential difference between the control gates of CG7 to CG8 and the channel is 7 V. With such a potential difference, no tunnel current flows between the charge storage layer and the substrate as long as a normal erase time is employed. On the other hand, if a tunnel current flows in a cell transistor whose channel is turned off, it flows through a path between the floating gate and the source or drain region. However, since the potential difference in this path is 10 V or 13 V, no tunnel current flows as long as a normal erase time is used. Therefore, no data is erased in this NAND cell row.

As described above, in this embodiment, a voltage of -10 V is applied to the control gate of the cell selected for data erasing, and the source / drain is applied using the self-boosting method of KDSuh et al. Is raised to 9V, thereby applying a voltage sufficient to erase data between the control gate electrode and the source / drain of the selected cell. That is, since voltages of opposite polarities are applied to the control gate electrode and the channel region of the NAND cell row, the absolute value of each voltage is approximately half the value when one of the voltages is set to 0V. Can be For example, in the case of the flash erase described in the related art, the control gate is set to 0.
Compare with the fact that it was necessary to apply a high voltage of 20 V to the P-well layer because V was set to V. In this manner, since the absolute value of the erase voltage can be reduced, in this embodiment, a high breakdown voltage transistor as in the related art is not required as a transistor constituting the NAND EEPROM. In addition, since the design rule between the wirings can be the same as that in the case where a normal low voltage is used, it is possible to achieve a higher density of elements and a reduction in chip size.
Further, since high voltage is not required, reliability is improved.

In the above description, bit erasing for erasing data for each selected cell has been described. However, all bit lines BL for a predetermined number of NAND cell rows sharing a control gate electrode are used. 3.3V
In all of these NAND-type cell columns, it is possible to collectively erase cells connected to the selected control gate, that is, to perform “page erasure” for erasing all pages at once.

Next, a seventh embodiment will be described with reference to FIG. In this embodiment, the N-well layer and the P-well layer are not formed, and the memory cell section is formed directly on the p-type substrate. The timing of voltage control during erasing is
This is the same as the sixth embodiment.

According to this embodiment, since the potential of the p-type substrate can be set to 0 V, a NAND-type memory cell array can be formed in this p-type substrate region, similarly to the N-channel transistor of the peripheral CMOS circuit. Therefore, FIG.
As in the case of the NAND type EEPROM shown in FIG. 1, there is no need to form an N-well layer and a P-well layer for forming a memory cell portion, and the process steps can be simplified.

The present invention is not limited to the above embodiments, but can be implemented with various modifications within the scope of the invention.

[0111]

As described above in detail, according to the first aspect of the present invention, in the NAND cell row connected to the non-selected bit line, the memory cell section to which the write high voltage is applied to the control gate electrode is provided. Since the channel potential is sufficiently self-boosted, stress applied at the time of writing is reduced. on the other hand,
Even after data is written to an arbitrary memory cell in the NAND cell row, data can be randomly written without any problem. Further, the reliability can be improved without deteriorating the conventional device performance.

Further, according to the second aspect of the present invention, it is not necessary to use a high voltage as in the prior art at the time of erasing, so that the number of stages of the booster circuit can be reduced. Further, since it is not necessary to increase the breakdown voltage of the transistor, the area occupied by the peripheral circuit can be reduced. In addition, since the erasing operation can be performed at a low voltage, the reliability of the device can be improved, and an improvement in yield can be expected.

[Brief description of the drawings]

FIG. 1 is a plan view showing a memory cell column of a NAND type EEPROM and its equivalent circuit diagram.

FIG. 2 is a sectional view taken along the line II-II in FIG.

FIG. 3 is a sectional view taken along the line III-III in FIG.

FIG. 4 is a diagram showing an example of voltage control in reading, erasing, and writing in a conventional NAND EEPROM.

FIG. 5 is a diagram showing a threshold value of a cell transistor when information of a memory cell is “1” or “0”;

FIG. 6 is an explanatory diagram showing a writing method in a self-boosting method.

FIG. 7 is a diagram illustrating timing of voltage control in writing in a self-boosting method.

FIG. 8 is a diagram showing an analysis of electrode potential and capacitance between electrodes of a memory cell transistor.

FIG. 9 is a diagram showing a potential applied to each electrode in a state B in FIG. 6C.

FIG. 10 illustrates a writing method in a selective self-boosting method.

FIG. 11 is a diagram showing a relationship between a potential applied to each electrode and a channel potential at the time of writing in a selective self-boosting method.

FIG. 12 is a diagram showing a relationship between a potential applied to each electrode during writing and a channel potential in the self-boosting method.

FIG. 13 is a diagram showing voltage control during writing in the improved selective writing method of the present invention.

FIG. 14 is a potential relation diagram for explaining an operation at the time of writing in the improved selective writing method of the present invention.

FIG. 15 is a diagram illustrating a relationship between a rise in potential of a channel in a NAND memory cell and time.

FIG. 16 is a graph showing a part of data shown in the table of FIG. 15;

FIG. 17 is a graph showing a part of data shown in the table of FIG. 15;

FIG. 18 is a graph showing a part of the data shown in the table of FIG. 15;

FIG. 19 is a graph showing a part of data shown in the table of FIG. 15;

FIG. 20 is an explanatory view similar to FIG. 14 in a modification of the first embodiment of the present invention.

FIG. 21 is a diagram showing a first embodiment of voltage control timing in the improved selective writing method of the present invention.

FIG. 22 is a diagram showing a second embodiment of the voltage control timing in the improved selective writing method of the present invention.

FIG. 23 is a diagram showing a third embodiment of the voltage control timing in the improved selective writing method of the present invention.

FIG. 24 is a diagram showing a fourth embodiment of the voltage control timing in the improved selective writing method of the present invention.

FIG. 25 is a diagram showing a fifth embodiment of the voltage control timing in the improved selective writing method of the present invention.

FIG. 26 is a diagram showing voltage control at the time of erasing in a sixth embodiment of the present invention.

FIG. 27 is a diagram illustrating an erase operation on a selected cell in a selected NAND cell row and an erase inhibit operation on a non-selected cell row in the sixth embodiment of the present invention.

FIG. 28 shows another NAN according to the sixth embodiment of the present invention.
FIG. 9 is a diagram for explaining an erase prohibition operation in a D-type cell column.

FIG. 29 shows a NAND type E according to a seventh embodiment of the present invention.
FIG. 4 is a cross-sectional view showing a memory cell column of an EPROM.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 ... P type substrate, 12 ... Element isolation region, 13 ... Tunnel oxide film, 14 ... Charge storage layer, 15 ... Inter insulating film, 16 ... Control gate, 17 ... Interlayer insulating film, 18 ... Bit line.

──────────────────────────────────────────────────続 き Continued on front page (51) Int.Cl. ⁶ Identification code FI H01L 29/792

Claims (20)

[Claims] 1. A plurality of electrically rewritable memory cells connected in series, a first select gate transistor provided at one end of the plurality of memory cells on a bit line side, and the plurality of memories A second select gate transistor provided at the other end on the source line side of the cell.
What is claimed is: 1. A non-volatile semiconductor storage device including an ND type memory cell column, wherein when writing to a selected memory cell of a selected NAND type memory cell column,
A low voltage is applied from the bit line to the type memory cell column, while a non-selected NAND type memory cell column sharing a control gate electrode with the selected NAND type memory cell column is supplied with a high voltage from the bit line. When a voltage is applied, the potential of the channel region is floated, and the potential difference between the control gate electrode of the selected memory cell and the channel region in the selected NAND-type memory cell column is the data difference. A first voltage sufficient for writing is applied, and a control gate electrode of at least one of the memory cells adjacent to the selected memory cell is
Turns on the memory cell when it is in the normally OFF state
In the non-selected NAND-type memory cell column, a second voltage is applied that is sufficient to cause the channel potential to be selectively self-boosted in the memory cell sharing the control gate electrode with the selected memory cell. A nonvolatile semiconductor memory device. 2. A method according to claim 1, wherein writing to the control gate electrodes of the memory cells in the selected NAND type memory cell row other than the memory cells to which the first and second voltages are applied can be prohibited, and unselected NAND cells can be written. 2. The nonvolatile semiconductor memory device according to claim 1, wherein a third voltage enabling self-boosting of a channel potential of the type memory cell column is applied. 3. The first voltage, the second voltage and a third voltage.
3. The nonvolatile semiconductor memory device according to claim 2, wherein the relationship of the following voltages is: first voltage> third voltage> second voltage> 0. 4. 4. The memory cell according to claim 1, wherein the second voltage is applied to a control gate electrode of a memory cell which is closer to the bit line among memory cells adjacent to the selected memory cell. 3. The nonvolatile semiconductor memory device according to item 2. 5. An unselected memory cell sharing a control gate electrode with the selected memory cell as a control gate electrode of a memory cell adjacent to the source line among memory cells adjacent to the selected memory cell. 5. The nonvolatile semiconductor memory device according to claim 4, wherein a fourth voltage enabling selective self-boosting of a channel potential in one memory cell of the NAND type memory cell column is applied. 6. The relationship among the first voltage, the second voltage, the third voltage, and the fourth voltage is: first voltage> third voltage> second voltage> fourth voltage ≧ 0 The nonvolatile semiconductor memory device according to claim 5, wherein 7. The relationship among the first voltage, the second voltage, the third voltage and the fourth voltage is as follows: first voltage> third voltage> second voltage ≧ fourth voltage> 0. The nonvolatile semiconductor memory device according to claim 5, wherein 8. The second voltage is the same as a voltage applied to a control gate electrode of a memory cell other than a selected memory cell in a selected NAND type memory cell column at the time of reading. 2. The nonvolatile semiconductor memory device according to claim 1, wherein: 9. The nonvolatile semiconductor memory device according to claim 1, wherein the second voltage is the same as a power supply voltage. 10. The gate voltage of the first select gate transistor is set to a power supply voltage, and the potential of each of the control gate electrodes is set to a potential lower than the power supply voltage, and then each of the control gate electrodes is set as a final set voltage. 6. The nonvolatile semiconductor memory device according to claim 5, wherein the first voltage, the second voltage, the third voltage, and the fourth voltage are set. 11. A gate voltage of the first selection gate transistor is set to a power supply voltage, a potential of each of the control gate electrodes is set to a potential lower than the power supply voltage in a first period, and in a second period. The voltage is temporarily increased to substantially the same voltage as the second voltage, and thereafter set to the first voltage, the second voltage, the third voltage, and the fourth voltage as final setting voltages, respectively. The nonvolatile semiconductor memory device according to claim 5, wherein: 12. A gate voltage of the first selection gate transistor is set to a power supply voltage, a potential of each of the control gate electrodes is set to a potential lower than the power supply voltage in a first period, and in a second period. Temporarily raising the voltage to substantially the same voltage as the third voltage, and thereafter setting the first voltage, the second voltage, the third voltage, and the fourth voltage as final setting voltages, respectively; The nonvolatile semiconductor memory device according to claim 5, wherein: 13. A gate voltage of the first select gate transistor is higher than a power supply voltage during a first period and a second period, and is the power supply potential during a third period. The potential of each control gate electrode is set to a potential lower than the power supply voltage in the first period, and the first voltage, the second voltage,
6. The non-volatile semiconductor memory device according to claim 5, wherein the third voltage and the fourth voltage are set. 14. A gate voltage of the first select gate transistor is set to a voltage higher than a power supply voltage during a first period, and is set to the power supply potential in a second period and a third period. The potential of each control gate electrode is set to a potential lower than the power supply voltage in the first and second periods, and the first and second voltages are respectively set as final setting voltages in the third period. 6. The nonvolatile semiconductor memory device according to claim 5, wherein the voltage is set to a third voltage and a fourth voltage. 15. When the selected memory cell is adjacent to one of the first and second select gate transistors, a control gate electrode of a memory cell adjacent to the other of the selected memory cells is provided. The second voltage or the fourth voltage;
6. The non-volatile semiconductor memory device according to claim 5, wherein the following voltage is applied. 16. A plurality of electrically rewritable memory cells connected in series, a first select gate transistor provided at one end of the plurality of memory cells on a bit line side, and the plurality of memories And a second select gate transistor provided at the other end of the cell on the source line side.
What is claimed is: 1. A nonvolatile semiconductor memory device including an AND-type memory cell column, wherein when writing to a selected memory cell of a selected NAND-type memory cell column,
A non-selected NAND type memory cell column sharing the control gate electrode between the non-selected memory cell column and the NAND type memory cell column, and at least the selected memory cell and the selected memory cell from a bit line. The bit line potential is substantially transmitted to the channel region of the memory cell of the non-selected NAND memory cell column sharing the control gate electrode, and the channel region of the non-selected NAND memory cell column is floated, The potential of the control gate electrode in the selected NAND-type memory cell column is raised to a predetermined level, and the potential of the channel region in the non-selected NAND-type memory cell column is self-boosted by capacitive coupling. And the control gate electrode potential of a memory cell adjacent to the selected memory cell. Utilizing the potential difference, the memory cell sharing the control gate electrode with the adjacent memory cell in the non-selected NAND type memory cell column is turned off, and after the memory cell is turned off, the selected memory cell is turned off. A non-volatile semiconductor memory device, wherein a channel potential of a memory cell in a non-selected NAND type memory cell column sharing a control gate electrode with a memory cell is boosted to a final potential. 17. A plurality of electrically rewritable memory cells connected in series, a first select gate transistor provided at one end of the plurality of memory cells on a bit line side, and the plurality of memories And a second select gate transistor provided at the other end of the cell on the source line side.
A nonvolatile semiconductor memory device comprising an AND-type memory cell column, wherein when erasing data of a selected memory cell in the NAND-type memory cell column, at least a selected memory of the NAND-type memory cell column is selected. The first voltage is transmitted from the bit line to the channel region of the memory cell between the cell and the second select gate transistor, and the potential of the channel region is floated while controlling the selected memory cell. A second voltage is applied to the gate electrode, and a third voltage is applied to the control gate electrode of the unselected memory cell. In this case, the polarity of the second voltage, the polarity of the first and third voltages, Have the opposite polarities. 18. A negative potential is applied to a control gate electrode of the selected memory cell, a positive voltage is applied to a control gate electrode of an unselected memory cell, and a positive voltage is applied to a bit line. The nonvolatile semiconductor memory device according to claim 17, wherein: 19. A voltage of 0 V is applied to a bit line of another NAND memory cell column sharing a control gate electrode with the NAND memory cell column, and all memory cells in the other NAND memory cell column are not erased. 18. The nonvolatile semiconductor memory device according to claim 17, wherein said nonvolatile semiconductor memory device is set in a state of: 20. The nonvolatile semiconductor memory device according to claim 17, wherein said NAND type memory cell column is formed directly without forming a well diffusion layer on a semiconductor substrate.