JPS61220481A - Manufacturing method of semiconductor photodetector - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor light receiving device, and particularly to a method for manufacturing a compound semiconductor avalanche photodiode in which a guard ring is formed in a semiconductor layer with a lower impurity concentration than an avalanche multiplication layer. Concerning method improvements.

In optical communications where light is used as an information signal medium, avalanche photodiodes (hereinafter abbreviated as APDs), whose photocurrent is multiplied by avalanche breakdown, are highly effective in improving the signal-to-noise ratio of photodetectors.

In particular, in optical communication systems using stone capsule fibers, indium phosphorus/indium gallium arsenide (phosphorus) (InP/Ga
PD is important for compound semiconductors such as 1nAs(P) system, and in this PD, a guard ring to prevent breakdown outside the light receiving area is formed in a buried semiconductor layer with a lower impurity concentration than the avalanche breakdown layer. There are many things to do. However, with the conventional 8PD of this structure, the desired guard ring effect is often not obtained, and an improvement is needed.

[Conventional technology]

A semiconductor substrate of an InP/Ga1nAs(P)-based APD having a buried structure has a structure as shown in the schematic side sectional view of FIG. 2(a), for example. In the figure, 1 is an n-type InP substrate, 2 is an n-type aEnAs light absorption layer, 3 is an n-type InP avalanche multiplication layer, 4 is an n-type 1nP layer, 5 is an r-type light receiving region,
6 is a p-type guard ring region.

A high reverse bias voltage is applied to this APD, with the 1-type InP substrate 1 having positive polarity and the V-type light receiving region 5 having negative polarity.
The avalanche breakdown in which the authentic tag excited by the input signal light is used as the primary carrier in the nAs optical absorption layer 2 is performed when the forbidden band width is Ga.
It is generated in the InP avalanche multiplier layer 3, which has a larger InAs light absorption than N2. In order to prevent breakdown from occurring around the avalanche type light receiving region 5 at a voltage lower than the avalanche breakdown, p
r-type light-receiving region 5 in which the type guard ring region 6 is usually circular;
is formed in contact with the outer periphery of the

This conventional example is manufactured, for example, as follows.

That is, an n-type Ga1nAs light absorption layer 2 and an n-type rnP avalanche multiplication layer 3 are grown on an n-type InP substrate 1 by a normal liquid phase epitaxy medium growth method, and a layer 3 is formed on this layer 3 to a thickness of, for example, 0. A mask of about 1 to 0.2 μm is provided, and the n-type 1nP avalanche multiplier layer 3 is selectively removed to a depth of, for example, about 2 to 3 ptn by meltback or the like, and an impurity concentration lower than that of the avalanche multiplier layer 3 is added here. An n-type In2 layer 4 is buried and grown to form a semiconductor substrate.

For example, cadmium (Cd) is deposited on this semiconductor substrate to a depth of l.
The f-type light-receiving area 5 is diffused to about 2J1m to the n-type 1
A p-type guard ring region 6 with a gentle p-n junction is formed by ion-implanting beryllium (Be) into the type-1 InP layer 4 and performing activation heat treatment. Form.

In this manufacturing method, if the mask used for the selective removal of the n-type 1nP avalanche multiplier layer 3 and the buried growth of the 1-type 1nP layer 4 is fragile, the edges of the mask may be chipped during the manufacturing process. etc., resulting in disturbances at the selectively buried growth interface.

In order to prevent such troubles, this mask is made of silicon nitride (StJ*) or silicon dioxide (Sing), for example.
), but for reasons such as the fact that the growth rate of stepped portions of the semiconductor substrate is faster than that of flat portions during selective implantation growth, the partially enlarged schematic side sectional view of Fig. 2(b) As shown in FIG.
A step 4A limited at the edge of the mask is produced at ii4.

This step formed in the n-type InPIi4 is reflected in the rectangular light-receiving region 5 due to the above-mentioned Cd diffusion, and a curved part 5A is formed on the pn junction surface, and when a high reverse bias voltage is applied to the pn junction, the curved part 5A is Causes electric field concentration. Although this curved portion 5A is formed in the type 1 InP layer 4 having a lower impurity concentration than the avalanche multiplication layer 3, it may break down at a lower voltage than the avalanche breakdown.

[Problem to be solved by the invention 3 As explained above, in the buried structure APD, the curved part of the p-n junction in the p-type region that occurs in the buried growth layer becomes a weak point for breakdown, but the avalanche multiplication becomes stable. The conditions under which this can be obtained have not yet been established, and an early solution is desired.

[Means for solving problems]

The problem is that there is a first semiconductor layer that performs photoelectric conversion on a semiconductor substrate, and a first semiconductor layer that has a larger forbidden band width than the first semiconductor layer.
a second semiconductor layer of a conductivity type, the second semiconductor layer is selectively removed and a third semiconductor layer of the first hot conductivity type is buried and grown; a second conductivity type light receiving region forming a pn junction with the third semiconductor layer; and a second conductivity type guard ring forming a pn junction with the third semiconductor layer at the outer periphery of the light receiving region. When forming a region, the ratio of the impurity concentration of the third semiconductor layer to the impurity concentration of the second semiconductor layer is 3 to 4 or less, and the impurity concentration ratio of 3 to 4 is 1.2 μ, 1 to 1. 1.5 in 2
um, the top surface of the third semiconductor layer is the top surface of the second semiconductor layer within a range of 0.0 am or less, 2.0 Im for 1:4, and 2.3 μm for 1:5. This problem is solved by the method of manufacturing a semiconductor light receiving device according to the present invention, which increases the cost.

The correlation between the difference in the height of the semiconductor layer described above, that is, the impurity concentration ratio in the range of the amount of swelling of the buried layer and the amount of swelling of the buried layer is shown in FIG.

[For production]

According to the manufacturing method of the present invention, the top surface of the third semiconductor layer, which is to be a guard ring region, is opposite to the top surface of the second semiconductor layer, which is to be an avalanche multiplication region and a light-receiving region of the opposite conductivity type. The shape is such that it swells by 0.2 or more. This is to prevent ungrown pits from forming in the portion of the semiconductor layer that corresponds to the edge of the mask, thereby preventing local breakdown.

The effect of embedding a semiconductor layer with a low impurity concentration becomes obvious when the ratio of the impurity concentration of the third semiconductor layer to the impurity concentration of the second semiconductor layer is 3:4 or less, and p+
The local breakdown in the curved portion of the region depends on the curvature of the curved portion, that is, the height of the raised portion, and the impurity concentration of the third semiconductor layer. 1.2 Ilrn in 4, 1.5 fm in 1 to 2, 2.0 μm in 1 to 4, 1 to 5
When the impurity concentration of the third semiconductor layer is relatively high, pn
Since the curvature of the junction is kept small and the impurity concentration is suppressed when the curvature of the pn junction is relatively large, breakdown does not occur at voltages lower than avalanche breakdown and the guard ring effect is ensured. .

〔Example〕

The present invention will be specifically explained below using examples.

Similar to the APD shown in FIGS. 2(a) and (b), 1
An impurity concentration of about IXIO"cm-" and a thickness of about 2-cm is grown on an InP type InP substrate 1 by a liquid phase epitaxial growth method.
Type layer aInAs light absorption layer 2 and impurity concentration approximately 2XIQ"c
+a-', n-type InP avalanche multiplier layer 3 with a thickness of about 3 μm
on this layer 3 to a thickness of about 0.1 with 5iJ4.
A 511m mask was installed, and the n-type I
For example, the nP avalanche multiplication layer 3 is selectively removed to a depth of approximately 2.51 m, and the impurity concentration is approximately IXIQ"cm-' here.
The n-type InP layer 4 is buried and grown so that the top surface of the bulge is about 1.5 tttm higher than the upper surface of the avalanche multiplier N3 to form a semiconductor substrate.

Then, for example, cadmium (Cd) is heated to a temperature of about 2×10'
(3. Diffusion to a depth of about 1.5 μm to change the p-type 10-type light-receiving region 5 from the n-type 1nP avalanche multiplication layer 3 to the i-type 1nP layer 4.
For example, beryllium (Be) is formed at an energy of 140 keV and a dose of 5 Xl013cn+.
-'', ions are implanted into the A-type 1nP layer 4, and an activation heat treatment is performed at a temperature of, for example, 700°C for about 20 minutes.
A p-type guard ring region 6 is formed.

In this example, in which a protective insulating film and electrodes on both p and n sides were formed on this semiconductor substrate, a maximum multiplication factor of 30 times was obtained when light with a wavelength of 1.3 μm was incident, and the range shown in FIG. This is a remarkable effect compared to the maximum multiplication factor of conventional embedded type APDs that do not fall under the above criteria, which is about 10 times at most.

〔Effect of the invention〕

As explained above, according to the present invention, the occurrence of weak points outside the avalanche breakdown region is sufficiently suppressed, avalanche multiplication is realized as designed, and APDs with good characteristics can be manufactured at an excellent yield. It becomes possible.

[Brief explanation of the drawing]

Figure 1 is a diagram showing the correlation between the amount of protrusion of the buried layer and the impurity concentration ratio, Figure 2 (a) is a schematic side sectional view showing an example of a semiconductor substrate of an APD with a buried structure, Figure 2 (b) ) is a partially enlarged view. In the figure, 1 is a male-type 1nP substrate, 2 is an n-type Ga1nAs light absorption layer, 3 is an n-type 1nP avalanche multiplication layer, 4 is an n-type InP layer, 4A is a step thereof, and 5 is a p+ type optical region. 5^, the curved portion 6 of the pn junction surface is a p-type guard ring region.

Claims (1)

[Claims] A first semiconductor layer that performs photoelectric conversion on a semiconductor substrate, and a second semiconductor layer of a first conductivity type having a larger forbidden band width than the first semiconductor layer.
a third semiconductor layer of the first conductivity type is grown by selectively removing the second semiconductor layer, and growing a third semiconductor layer of the first conductivity type, between the second and third semiconductor layers. In forming a second conductivity type light-receiving region forming a p-n junction in the light-receiving region and a second conductivity-type guard ring region forming a p-n junction between the third semiconductor layer and the third semiconductor layer at the outer periphery of the light-receiving region, The ratio of the impurity concentration of the third semiconductor layer to the impurity concentration of the second semiconductor layer is 3:4 or less, and when the impurity concentration ratio is 3:4, it is 1.2 μm, and when the impurity concentration ratio is 1:2, it is 1.2 μm. 5 μm, 2.0 μm in 1 to 4, 2 in 1 to 5
．． A method for manufacturing a semiconductor light-receiving device, characterized in that the top surface of the third semiconductor layer is made higher than the top surface of the second semiconductor layer within a range of not more than 3 μm and not less than 0.2 μm.