JPS61205086A - Picture encoding and decoding device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an image encoding/decoding device used for digitally encoding and transmitting moving images, and particularly to improving encoding efficiency and detecting breaks in encoded information. The present invention relates to an image encoding/decoding device that facilitates and ensures transmission error detection.

[Conventional technology]

FIG. 9 is a block diagram illustrating an example of an inter-frame differential encoding device using block encoding that has been commonly used in the past.
1 is a raster/block converter that converts the input digital image signal 1 into blocks (K is an integer of 2 or more), 3 is an input signal sequence that is grouped into blocks, and 4 is a frame memory 12 to be described later. 5 is a differential signal sequence between the input signal sequence 3 and the past signal sequence 4;

Reference numeral 6 denotes a threshold value used for significant/insignificant identification, 7 a motion detection block encoder that performs significant/insignificant identification based on the threshold value 6t, and blocks-codes only significant differential signal sequences; 8 9 is a significant difference signal sequence block encoded signal output from the motion detection block encoder 7, and 9 decodes significant block data included in the significant difference signal sequence block encoded signal 8 to output a decoded difference signal sequence 10. A block decoder 11 is a decoded signal sequence obtained by adding the signal sequence 4 outputted from the frame memory 12 and the decoded difference signal sequence 10, and is supplied to the frame memory 12. 13 is a code allocator that outputs a code allocation signal 14 by variable length coding the significant difference signal sequence block encoded signal 8 output from the motion detection block encoder 7; 15 is connected to the code allocator 13; The buffer memory 116 is an output of the buffer memory 15, and 17 is a frame configuration circuit connected to the output side of the buffer memory 15, and outputs to the transmission frame transmission path 18.

In the next circuit configured in this way, when the input digital image signal 1 is supplied, the raster/block converter 2 converts the input digital image signal 1 into blocks for each block to generate the input signal series St3. Output. This input signal sequence St3 is subtracted from the past signal sequence PI4 located at the same position on the image in the frame memory 12 to obtain a difference signal sequence E15, and then processed at a threshold value Tθ6 in the motion detection block encoder 7. By performing significant/insignificant identification based on the above, only significant difference signal sequences are output as significant difference signal sequence block encoded signals 8. This significant difference signal sequence block encoded signal 8 is decoded in a block decoder 9 to obtain a decoded difference signal sequence EllO, which is added to the past signal sequence Pg4 to obtain a decoded signal sequence. 5111
I'm looking for. This decoded signal sequence 8111 is then supplied to the frame memory 12 to update the contents of the block, thereby making the contents consistent between transmission and reception.

Next, the significant difference signal sequence block encoded signal 8 consisting of the significant/unconscious classification result and the significant block encoding result is variable-length encoded for each cluster in block units in the code assigner 13, thereby producing a code assignment signal. 14 in the buffer 15.

The contents of this buffer 15 are read out at a constant speed to smooth the speed, and the output signal 16 is supplied to a frame configuration circuit 17 to configure a transmission frame and send it to a transmission line 18. FIG. 10 shows an encoding example.

[Problem that the invention seeks to solve]

However, in the above-mentioned conventional image encoding device, in order to prevent the propagation of transmission path errors during decoding, since significant/insignificant information occupies a large proportion of the total amount of information, certain Since it is necessary to insert a special code into each block, there is a problem in that the amount of fixed information increases.

The present invention was made to solve the above problems, and an object of the present invention is to provide an image encoding/decoding device that facilitates the detection of transmission path errors.

[Means for solving problems]

Therefore, the image encoding/decoding device according to the present invention collectively encodes the significant/unconscious classification results for each M large blocks, and adds a header to the significant/unconscious data before decoding the significant/unconscious block data. This makes it easy to detect transmission errors by decoding separate information and finding the number of significant blocks.

[For production]

In the image encoding/decoding device configured in this way,
Since the significant/unconscious results are coded together into M pieces and processing is performed in parallel with the coding of significant blocks, it is possible to improve coding efficiency, and with the addition of a header, the coded information is Since breaks are reliably detected, transmission errors can be easily detected.

〔Example〕

FIG. 1 is a block diagram showing an embodiment of an image encoding device according to the present invention, in which reference numeral 101 denotes a raster image signal 201 for dividing an input digital image signal 201 into blocks.
A block converter 102 determines whether the difference signal sequence 203 between the signal sequence 204 on the same image position in the frame memory 103 and the latest input signal sequence 202 is significant or unconscious based on a threshold value 300, and determines whether the signal sequence 203 is significant or not. 103 is a frame memory that stores at least one frame of image signals; 104 is a block-encoded signal sequence output from the motion detection block encoder 102; 206 is a block decoder which obtains a decoded difference signal sequence; 105 is a significant/insignificant code assigner which further groups M significant/unconscious results and performs variable length encoding; 106 is a significant block encoder A significant block code allocator 107 variable-length encodes a signal; a buffer 108 that temporarily stores the unevenly input significant/insignificant code allocation results and performs speed smoothing;
10 is a buffer that performs speed smoothing by temporarily storing significant block code allocation signals that are input unevenly;
9U is a header-added frame configuration circuit that reads information from a buffer at a constant speed, adds a header, and transmits the information.

FIG. 2 is a block diagram showing a specific example of the significant/insignificant code allocator 105 and buffer 107 shown in FIG.
In the figure, 110 is a blocking circuit that collects M significant/unconscious signals and further blocks them, and 111 encodes the number of consecutive patterns that have a high possibility of consecutive block patterns, or 112 is a coding control circuit that controls coding assignment processing; 113 is a run counter that counts the number of consecutive patterns; 114 is a pattern encoding circuit that assigns codes to patterns; 115; 116 is a run encoding circuit that allocates a continuous number of codes; 116 is a game that prohibits output until the code allocation process is completed; and 117 is a select circuit that selects the thread path for which the code allocation process has been completed.

FIG. 3 shows the configuration of the image decoding device, where 119 is a header detection frame decomposition circuit that detects a header and the beginning of a video frame, and 120 is a significant/unsigned decoder that decodes significant/unsigned information. , 121 is a significant block decoder that decodes significant blocks, 122 is a buffer that temporarily stores the significant/insignificant information decoding results and synchronizes with the significant block decoding results, and 123 is symmetrical to 122 and stores the significant block decoding results. A buffer for temporarily storing and synchronizing with the meaningful/insignificant information decoding results; 124 is a game for reading significant block decoded signals from the buffer according to the significant/insignificant information decoding results; 125 is a differential signal sequence 207 for the significant blocks;
a block decoder 126 for decoding past images; a frame memory 127 for storing at least l claims of past images;
is the difference signal series 207 and the corresponding signal series 204 on the past image output from the frame memory 126.
This is a raster/block inverse converter that inversely converts the decoded signal obtained by adding 208ft raster scan.

Figure 4 shows the header detection frame decomposition circuit 1 shown in Figure 3.
19 is shown in detail, the frame decomposition circuit 119' is a part of the header detection frame decomposition circuit 119 shown in FIG. A variable length decoding circuit for decoding non-nuance encoded information, 131 a run length buffer for storing the number of consecutive patterns, 132 a pattern buffer for storing patterns, and 133 a run for repeatedly reading out the same pattern by the consecutive number of patterns. Long subtraction counter, 13
4 is a pattern latch that latches the same pattern as many times as the number of times it is read out by repeating the comb.
This is a deblocking circuit that decomposes into individual pieces.

The encoding operation will be explained below based on the first example and FIG. 2. First, nine input digital image signals 201 are divided into five blocks by a raster/block converter 101 to form a signal sequence 202.

This signal sequence 202 is then transmitted to the frame memory 1.
By subtracting the past signal sequence 204 at the same position on the image read from 03, the difference signal sequence 20
3 is required. Next, the motion detection block encoder 102 uses a threshold value 300 for this difference signal sequence 203.
Significance/insignificance is identified based on the block, and only the differential signal sequence 203 of the significant block is block encoded. The block decoder 104 decodes the block encoded signal 206 to obtain a decoded difference signal sequence 207, and converts this into the past signal sequence 20
4 to obtain a decoded signal sequence 208. and,
This decoded signal series 208 is supplied to the frame memory 103 to update its contents so that the transmitted and received frame memory contents match.

On the other hand, the significant/unconscious signals 205 are further grouped into M pieces in the blocking circuit 110 shown in FIG. Determine whether or not.
The run counter 113 counts consecutive numbers for each specific combination, and sends the consecutive numbers to the run encoding circuit 115 at the time when the same pattern continues. The run encoder 115 performs variable length encoding on consecutive numbers. Further, the pattern encoding circuit 114 performs variable length encoding on the combination itself.

The gate 116 prohibits output until the encoding is completed, and the selector 117 selects the encoded data and writes it into the buffer 107. At the same time, during the period when one video frame is being encoded, the significant block code allocator 106 assigns the significant block encoded signal 20
6 is converted into a variable length code 209 and written to the buffer 108. When the encoding process for one video frame is completed, the header addition frame configuration circuit 109 first adds a header to the significant/unconscious information 210 of the entire video frame and transmits it, and finally adds a special code. Next, a header is added to the significant block data 211 of the entire one video frame and transmitted, and the transmission of the entire one video frame 2
End 01.

Fifth. 6th. 7th. FIG. 8 shows an example of the above encoding.

Next, decoding will be explained based on FIGS. 3 and 4.

The transmitted data 212 is processed by the header detection frame decomposition circuit 119 to separate it into encoded information only, and the output signal is first sent to the significant/insignificant decoder 12.
0, the combination of significant/unconscious signals of the entire video frame and consecutive numbers 219 are decoded and stored in the pattern buffer 132 and the run length buffer 131, respectively. This operation is continued until the special code indicating the delimiter of the transmission information is detected 213, and then the significant block decoder 121 decodes the significant block data by the number of significant blocks in the entire video frame obtained by decoding the significant/unconscious information. is decoded and stored in the buffer 123. Finally, when the special code 213 indicating the end of data is detected, the reception of the entire video claim is completed. Thereafter, the contents of the pattern buffer 132 are transferred to the pattern latch 134 in synchronization with the video data decoding clock.
The contents of the pattern latch 131 are held while the consecutive number of consecutive pieces indicated by the contents of the run length buffer 131 is counted by the run length subtraction kakunta. Next, the content read out in this manner is decomposed by a deblocking circuit 135 to obtain a significant/unconscious signal 205. According to this significant/insignificant decoded signal 205, significant block data 206 is read from the buffer 123. However, if it is unexpected, the output is prohibited by game) 124. This significant block data 208 is decoded by the block decoder 125 to obtain a decoded difference signal sequence 207, and frame memo IJ-1
A decoded sequence 208 is obtained by adding the corresponding past signal sequence 204 within 26. This decoded signal sequence 208
The contents of the υ frame memory 126 are updated to match the contents with those on the transmitting side, and the raster/block inverse converter 127 decomposes the individual groups to obtain a decoded digital image signal. After repeating the above steps for one video frame, the next video frame is decoded.

In the above embodiment, the significant blocks are block coded, but even if the significant blocks are coded pixel by pixel, the same effect as in the above embodiment can be obtained.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to reduce the amount of significant/unconscious information with a simple configuration, and also to reliably decode sent information and detect transmission path errors before image decoding. This has an excellent effect in that it is possible to prevent errors from being included in the contents of the frame memory.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the image encoding device according to the present invention, FIG. 2 is a block diagram showing a specific example of the significant/unconscious information encoder shown in FIG. 1, and FIG. FIG. 4 is a block diagram of the image decoding device according to the invention; FIG. 4 is a block diagram showing a specific example of the significant/unconscious information encoder shown in FIG. 3; FIG. 5 is an explanatory diagram showing the blocking operation;
The figure is a diagram for explaining the operation of significant/unconscious information, and FIG. 7 is a diagram showing an example of encoding/decoding of significant/unconscious information. FIG. 8 is a diagram showing a transmission frame after the ladder addition frame is configured, FIG. 9 is a block diagram showing an example of a conventional image encoding device, and FIG. 10 explains the encoding operation in FIG. 9. This is a diagram for In the figure, 101 is a raster/block converter, 102 is a motion detection block encoder, 103 is a H7 frame memory, 1
04 is a block decoder, 105 is a significant/insignificant code assigner, 106 is a significant block code assigner, 107, 108
is a buffer, 109 is a header addition frame configuration circuit,
110 is a blocking circuit, 111 is a pattern determination circuit,
113 is a run counter, 114 is a pattern encoding circuit,
115 is a run encoding circuit, 116 is a gate, 117 is a select, 119 is a header detection 7-frame decomposition circuit, 12
0 is a significant/insignificant decoder, 121 is a significant block decoder,
122, 123 is a buffer, 124 is a gate, 125 is a block decoder, 126 is a frame memory, 127
129 is a raster/block inverse transformer, 129 is a decoding control circuit,
130 is a variable length decoding circuit, 131 is a run length buffer, 1
32 is a pattern buffer, 133 is a run length subtraction counter, 134 is a pattern latch, and 135 is a deblocking circuit. Note that in Figure 5, the same reference numerals indicate the same or equivalent parts.

Claims (5)

[Claims] (1) A frame memory that stores digital image signals for at least one video frame, and a raster/raster system that creates an input signal series by grouping the input digital image signals into K blocks (K is an integer of 2 or more). A block converter determines significance/insignificance based on a threshold value for the difference signal sequence obtained by calculating the difference between the blocked input signal sequence and the output signal sequence at the same position on the image in the frame memory. a motion detection block encoder that block encodes only significant differential signal sequences by identifying them; and a motion detection block encoder that decodes the differential signal sequence from the output signal of the motion detection block encoder and stores the output signal in the frame memory. a block decoder that updates the content of the signal sequence in the frame memory by adding it to the signal sequence in the frame memory; a significant/unconscious code allocator for encoding, a significant block code allocator for variable length coding the significant difference signal sequence encoded signal, and a significant/unconscious code allocation result and a significant block data code allocation result. An image encoding/decoding device comprising: a buffer memory that stores each separately; and a header-adding frame configuration circuit that divides the contents of the buffer memory into units of a certain word length, adds a header, and then transmits the data. (2) Significant/unconscious codes obtained from the input digital image signal in units of K small blocks are grouped into M large blocks, and identification codes of small blocks within the large block can be consecutively in the same combination. For combinations of small blocks within a large block with high probability, the number of consecutive large blocks is used as an external code and that number is variable-length encoded, and for other combinations using identification codes of small blocks within large blocks, The image encoding/decoding apparatus according to claim 1, wherein the image encoding/decoding apparatus performs internal encoding using a variable length based on the probability of occurrence. (3) Separate the significant/unconscious code assignment results performed for each video frame and the significant block data code assignment results and store them in a buffer memory, add a header, and separate them from the beginning of the video frame and other parts. Claim 1, characterized in that a special code is added to the end of each of the significant/unconscious code assignment result and the significant block data code assignment result to indicate the boundary and the transmission is performed. Image encoding/decoding device. (4) When receiving the significant/unconscious code assignment results and the significant block data code assignment results, the significant/unconscious codes are sequentially decoded for each video frame based on the header and special code detection results. Claim 3, characterized in that after storing the data in the buffer memory, the number of significant block data of an entire video frame is determined, and then the decoding is performed until the number of significant block data matches the number of significant block data, and the data is stored in the buffer memory. The image encoding/decoding device described above. (5) When decoding the significant/unconscious code assignment results and storing them in the buffer memory, the consecutive numbers and their combinations are stored separately, and the combinations are repeated for the consecutive numbers during decoding. 5. The image encoding/decoding apparatus according to claim 4, wherein the reading is synchronized with the buffer memory reading operation of the significant block data decoding result.