JPS6362944B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an apparatus for encoding a binary image created by facsimile or the like using a two-dimensional encoding method such as an MR (Modified READ) encoding method.

Conventionally, from a binary image that is scanned two-dimensionally and stored in memory for each line, two adjacent
The image data for each line is read out sequentially, and the above binary image is converted into two by using the correlation that exists between two lines.
As an example of a device for dimensional encoding, there is the one shown in FIG. 1 in the MR encoding system. In the diagram,
1b is a coding line memory that stores the image signal of the coding line; 1a is a reference line memory that stores the image signal of the reference line directly above the coding line;
2a and 2b are address counters for each of the memories 1a and 1b, and 3a and 3b are address counters for each of the memories 1a and 1b.
4 is a primary storage circuit (hereinafter abbreviated as latch) for the image signal read out from the image signal, and 4 is an encoding circuit.
Here, this encoding circuit 4 has an address counter 2
It is assumed that the function also has the function of controlling the value of .

Next, the operation will be explained. line memory 1
It is assumed that the image signals of the reference line and the encoded line are stored in advance in a and 1b by some method. The encoding circuit 4 controls the address counters 2a and 2b, reads out image signals pixel by pixel, and temporarily stores them in latches 3a and 3b. The encoding circuit 4 detects each change point defined by the MR encoding method from the input image signal series. Further, the encoding circuit 4 increases or decreases the address counter 2a or 2b according to a predetermined control procedure depending on the order in which each change point is detected, and outputs the address counter 2a or 2b while referring to the necessary signals. Determine the sign. Once the code is determined, the corresponding code word (bit pattern) is selected and sequentially output. Here, since the encoding circuit 4 can refer to only one pixel of each of two lines of image signals at a time, the encoding circuit 4 needs a control function to increase or decrease only the address counter 2a or 2b. Furthermore, when one code is determined, detection of the next code is restarted after output of the corresponding code word is completed. Therefore, it is necessary to stop the address counters 2a and 2b while converting the detected code into a code word.

Since the conventional encoding device has the above configuration, the processing time for encoding one line is
It is impossible for the value to be less than (processing time for one pixel)×(number of pixels in one line). Furthermore, the processing time will vary greatly depending on the nature of the input image signal. This is because the image signal that can be referenced at a time is one pixel each for both the reference line and the encoded line, and the process of detecting the code and the process of converting the detected code into a code word cannot be processed in parallel at the same time. This is caused by For this reason, the processing speed thereof has not been sufficient as an encoding device for transmitting image signals using a high-speed data transmission path.

This invention was made in order to eliminate the drawbacks of the conventional device as described above. Image signals read from a line memory are stored in a shift register, and multiple adjacent pixels can be referred to at the same time. This eliminates the need to increase or decrease the code word, and separates the encoding circuit into a code detection circuit and a code word conversion circuit, and uses the space between them for temporary storage.
By connecting with FIFO memory, two independent processes can be executed in parallel, eliminating the need to stop reading image signals from line memory. It is an object of the present invention to provide a binary image encoding device capable of high-speed processing and capable of sufficiently handling even high-speed images.

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 2, 1a and 1b are reference line memories and encoding line memories, respectively, and 2 is both memory 1.
Address counter common to a, 1b, 3a, 3b
5a and 5b are temporary storage circuits for each memory output (hereinafter referred to as memory latches), and 5a and 5b are memory latches 3a and 3.
6a and 6b are temporary storage circuits for the outputs of shift registers 5a and 5b, respectively (hereinafter referred to as shift registers). (abbreviated as latch), 7 is address counter 2
A control circuit (hereinafter referred to as latch control circuit) that generates a control signal for latching the shift register latches 6a and 6b from the value of , and a code detection circuit 8 that detects a code from the signal values of multiple pixels stored in the shift register latch 6. , 9 is a FIFO (First-in First-out) memory for temporarily storing the detected code; 10
is a code word conversion circuit that converts the detected code from the FIFO memory 9 into a code word and outputs the code word.

Next, the operation of this encoding device will be explained. In this case as well, it is assumed that the image signals of the reference line and the encoded line are stored in each line memory 1a, 1b in advance by some method. First, the code detection circuit 8 initializes the address counter 2, and then instructs to start counting up (or counting down) one count at a time. From then on, the address counter 2 automatically repeats counting until a stop signal is received from the outside, and plays the role of sequentially reading out the image signals in the line memories 1a and 1b. The memory latches 3a, 3b and shift registers 5a, 5b operate in synchronization with the address counter 2, making it possible to simultaneously refer to the signals of a plurality of adjacent pixels read out from the line memories 1a, 1b. Latch control circuit 7
refers to the value of the address counter 2, and when it detects that a predetermined number of pixels of image signals have been accumulated in the shift registers 5a, 5b, it sends a latch control signal to the shift register latches 6a, 6b. Send. Shift register latch 6
a, 6b temporarily store the image signals stored in the shift registers 5a, 5b according to the control signals. The image signals of these plural pixels are collectively input to the code detection circuit 8. The code detection circuit 8 checks whether the values of the input image signal of multiple pixels match a certain pattern (bit sequence), and if so, selects the code corresponding to that pattern. and transmits a predetermined code. At this time, since image signals of pixels on a plurality of encoding lines are input to the code detection circuit 8, two or more code codes may be detected at the same time. That is, with this device, it is possible to simultaneously encode multiple pixels. For example, 6 shift register latches at once
Assuming that the number of pixels on the encoded line stored in a and 6b is N, increasing the readout speed of the line memories 1a and 1b by N times effectively reduces the time required for encoding one line to 1/1 in the conventional device. 1 in time less than or equal to N
Encoding of the line will be completed. Also, the output of the sign detection circuit 8 is output from the FIFO memory 9.
The code detection circuit 8 can detect the next code without considering the processing time difference between the two circuits. Similarly, the code word conversion circuit 10 can read the code code from the FIFO memory 9 according to its own processing speed and convert it into a code word, so that the conversion process can be continued without wasting time as long as the FIFO memory 9 is not empty.

Hereinafter, a case of MR encoding will be specifically explained as an example of encoding.

MR encoding is an encoding method that distinguishes modes based on the relative distance between change pixels (pixels whose color changes from white to black or from black to white) between a reference line and an encoded line. The modes are broadly classified into vertical mode, pass mode, and horizontal mode. FIG. 3 shows examples of each mode.

As shown in FIG. 3a, when the absolute value of the distance between the changed pixels on the reference line and the encoded line is 3 or less, the mode is vertical mode. If there is no changed pixel on the encoding line that corresponds to the changed pixel on the reference line, as shown in FIG. Furthermore, if a new changed pixel occurs on the encoding line as shown in c in the same figure, or if the absolute value of the distance between the changed pixel on the reference line and the encoded line is 4 or more as shown in d in the same figure, the horizontal mode.

FIG. 4 is a table showing code word assignments for each mode. In the case of horizontal mode, two MH codes follow the prefix "001" indicating horizontal mode. The first MH code encodes the distance to the first changed pixel on the coding line, and the second MH code encodes the distance from the first changed pixel to the next changed pixel. corresponds to Further, in the case of the vertical mode, it is subdivided into seven ways as shown in FIG. 4, depending on the distance value of the changed pixel.
That is, when there is a changed pixel on the encoding line directly below a changed pixel on the reference line, the value is V(0).
If the changed pixel of the encoding line is n pixels (n=1, 2, 3) to the right of the changed pixel of the reference line, then
V _R (n). The changed pixel of the encoded line is n pixels larger than the changed pixel of the reference line (n=1, 2,
3) If it is on the left, it becomes V _L (n).

Now, the case where an image as shown in FIG. 5 is encoded using the binary image encoding apparatus of the present invention will be described. It is assumed that the number of pixels of the shift register latches 6a and 6b is 4 (N=4).

The reference line and the encoded line are sequentially read from address 0, and when they are read up to address 3, they are latched into shift register latches 6a and 6b. At that point, a total of eight pixels of block 1 will be input to the code detection circuit. The sign detection circuit detects that the vertical mode is V _L (1),
Outputs to FIFO memory that it is in V _L (1) mode. Next, when address 7 is read out, block 2 is latched in shift registers 6a and 6b, and the sign detection circuit detects V _R (1) and writes it into the FIFO memory. Similarly, block 3 outputs the pass mode (P) and block 4 outputs the horizontal mode (H) to the FIFO. Furthermore, in the case of block 5, two V(0) modes are detected, so two V(0)
written to. In block 6, V _R (2) is written to the FIFO.

On the other hand, the code word conversion circuit sequentially reads the mode data from the FIFO, converts it into the code word shown in FIG. 4, and outputs the code word.

In the above embodiment, a case has been described in which a line memory for one line is used as a reference line, but in the case of a general two-dimensional encoding method, two or more lines may be used as a reference line. In this case, as in the case of one line, by providing the required number of line memories, shift registers, and temporary storage circuits, it is possible to provide a device that achieves the same effects as the above embodiment.

As described above, according to the binary image encoding device of the present invention, since codes are detected by simultaneously referring to a plurality of adjacent pixel signals of a reference line and an encoding line, a plurality of pixels can be simultaneously encoded. Furthermore, since the code detection circuit and the code word conversion circuit are separated and each can perform independent processing, the encoding time for one line can be significantly shortened as a result.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional binary image encoding device, FIG. 2 is a block diagram of a binary image encoding device according to an embodiment of the present invention, and FIG. 3 is an example of modes in an MR code. FIG. 4 is a diagram showing mode and codeword assignment in an MR code, and FIG. 5 is a diagram showing an example of reference lines and coded lines. In the figure, 1 is a line memory, 2 is an address counter for the line memory, 3 is a temporary storage circuit for line memory output, 5 is a shift register, 6 is a temporary storage circuit for shift register output, 7 is a control circuit, and 8 is a code detection circuit. circuit, 9 is FIFO for temporary storage of code
Memory 10 is a code word conversion circuit. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] 1. Image data for two adjacent lines are sequentially read out from a binary image that is two-dimensionally scanned and stored in a memory for each line, and the correlation that exists between the two lines is determined. In a binary image encoding device that performs encoding using , two shift registers provided corresponding to the encoding line memory and the reference line memory and capable of sequentially reading out the signals in the memory and simultaneously outputting the signals of a plurality of adjacent pixels; two temporary memory circuits that store a plurality of pixels at appropriate times; a code detection circuit that uses the outputs of the two temporary memory circuits as input to discover a predetermined image signal sequence and detects the corresponding code; FIFO that temporarily stores the output of the code detection circuit
(First-in First-out) memory; and a code word conversion circuit that converts the code code corresponding to the detected code from the FIFO memory into a transmission line code word and outputs the code word. Binary image encoding device.