JPS61205024A - Analog-to-digital converting circuit for video signal - Google Patents

Abstract

PURPOSE:To control the level of the reference voltage from outside by using the reference voltage set by an A/D converting circuit for setting the reference voltage to give the A/D conversion to the TV video signal and at the same time feeding back the set reference voltage t said A/D converting circuit. CONSTITUTION:The working voltages V1 and V2 are supplied to an integration circuit 4; while the working voltages V1' and V2' are supplied to an integration circuit 5. The circuit 4 integrates the V1 and V2 in response to the signal given from a pulse producing circuit 2 and then delivers the integration output to a luminance A/D converting circuit 1 in the form of the upper limit reference voltage VH. Then the circuit 5 integrates the V1' and V2' in response to the signal sent from a pulse producing circuit 3 and delivers the integration output to the circuit 1 in the form of the lower reference voltage VL. The output of both circuits 4 and 5 undergo the level shifts through level shifters 6a-6c and are applied to a red A/D converting circuit 7a, a green A/D converting circuit 7b and a blue A/D converting circuit 7c in the form of upper and lower reference voltages VH' and VL' respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a video signal A/D conversion circuit in a television receiver using a panel type display section.

"Prior art and its problems" In recent years, small portable television receivers that use a liquid crystal display panel for the display section have been put into practical use.

This type of conventional black-and-white television receiver using a liquid crystal display panel converts a video signal amplified by a video amplification circuit into a digital signal by an A/D conversion circuit, and drives the liquid crystal display panel for display using this digital signal. That's what I do. However, due to its characteristics, the liquid crystal display panel has a narrow gradation range from the white level to the black level, making it difficult to obtain images with good contrast. In order to solve this problem, conventionally, the average value of the television video signal is detected and the reference voltage of the A/D conversion circuit is set according to the brightness and darkness, so that good contrast can be obtained. In other words, the video signal does not always change from the white level to the black level, and there is no need to A/D convert the entire range of the video signal.
Contrast can be improved by varying the conversion level of the conversion circuit. Recently, as a control means for the A/D conversion circuit, data of all "OIT" corresponding to all "1" and completely black for a complete mill in the signal digitized by the A/D conversion circuit is used. A method has been considered in which each number is counted, a voltage corresponding to the counted value is generated, and the voltage is fed back as a reference voltage for the A/D conversion circuit. That is, A/D
Upper and lower limit reference voltages are set in the conversion circuit, and when there is an input voltage in the A/D conversion circuit, 4-bit data indicates which level of the 16 equal parts of the upper and lower limit reference voltages the input voltage belongs to. With this method, optimal contrast can always be obtained.

However, although all of the conventional circuits mentioned above can be implemented in LSI, there is a problem that once implemented in LSI, adjustment cannot be made from the outside. In particular, when used in a color television, there is a problem that unless adjustment can be made for each of R, G, and B, the desired hue cannot be obtained because the luminance components of each color are different.

[Object of the Invention] The present invention has been made in view of the above-mentioned circumstances, and an object thereof is to provide a video signal A/D conversion circuit that can externally adjust a reference voltage for A/D conversion of a video signal. do.

[Summary of the Invention 1 The present invention provides an independent A/D conversion circuit for setting a reference voltage separately from an A/D conversion circuit for A/D converting a television video signal, and the A/D conversion circuit for setting the reference voltage. The TV video signal is A/D converted using the reference voltage set by
A video signal A/D that feeds back to the D conversion circuit, performs A/D conversion while accurately following changes in the R degree of the video signal, and allows the level of the reference voltage to be adjusted externally.
It is a conversion circuit.

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings. First, the overall schematic configuration will be explained with reference to FIG. In FIG. 1, 1 is a luminance A/D conversion circuit, R,
Average G and B video signals are input. This R, G, B
As the average video signal, for example, a luminance signal sent from a video signal processing circuit (not shown) via a signal line DL is used. Further, the brightness A/D converting circuit 1 is supplied with an upper limit reference voltage V from an integrating circuit 4.5, the details of which will be described later.
H and lower limit reference voltage VL are input, and, for example, 3
．． A 12 MHz sampling clock φ8 is input. The luminance A/D conversion circuit 1 compares the luminance signal Y with an upper limit reference voltage VH and a lower limit reference voltage VL, and
Levels above H and below the lower limit reference voltage VL are detected and outputted as a bright level signal W and a dark level signal B, respectively, in synchronization with the sampling clock φS. The bright level signal W output from the luminance A/D conversion circuit 1 is input to the pulse generating circuit 2, and the dark level signal B is input to the pulse generating circuit 3. Further, the pulse generating circuit 2.
3 receives the clock pulse φ2, tego, -〇lower 1 from the control section.

The above clock pulse φ2 is outputted approximately 50,000 times within one field, and the clock pulse CK2 is outputted when the field changes.
(H is the horizontal period) It is output with a delay. The outputs of the pulse generation circuits 2.3 are sent to integration circuits 4.5, respectively. Operating voltages V1 and V2 are supplied to the integrating circuit 4,
The integrating circuit 5 is supplied with operating voltages Vl' and V2'.

Then, the integrating circuit 4 integrates the voltages v1 and 2 according to the signal from the pulse generating circuit 2, and outputs the integrated output as the upper limit reference voltage VH to the luminance A/D converter circuit 1. Voltage Vl according to the signal from the creation circuit 3
', V2' are integrated, and the integrated output is output to the luminance A/D conversion circuit 1 as the lower limit reference voltage VL. Further, the outputs of the integration circuits 4.5 are each sent to a level shifter 6a.

Level shifted by 6b and 6C, upper limit reference voltage V)
(', is given as the lower limit reference voltage VL' to the red A/D conversion circuit 7a, the green A/D conversion circuit 7b, and the blue A/D conversion circuit IC.
, the green A/D conversion circuit 7b, and the blue A/D conversion circuit 7C.
1 green signal G and blue signal B are respectively input. The A/D conversion circuits 7a, 7b, 7C receive the upper limit reference voltage VH' from the level shifters 6a, 6b, 6C.
, the color signals R, G, and B are converted into 4-bit digital signals according to the lower limit reference voltage vL' and output to a liquid crystal display circuit (not shown) using a color liquid crystal display panel. The level shifters 6a, 6b, 6G have an input terminal 6al for manually adjusting the voltage level.
, 6 bl and 13 cl are provided.

Therefore, in the above configuration, the level shifter 6a.

E) Portions other than b and 13c can be integrated into LSI.

Next, details of the luminance A/D conversion circuit 1, pulse generation circuit 2, and integration circuit 4 will be explained with reference to FIG. Brightness A
, / The D conversion circuit 1 includes an A/D conversion circuit 11 and a decoder 12, and a luminance signal Y is input to the A/D conversion circuit 11, and an upper limit reference voltage VH and a lower limit reference voltage V are input to the A/D conversion circuit 11.
L is input. Then, the A/D conversion circuit 11 converts the level of the luminance signal Y that is higher than the upper limit reference voltage H into a 4-bit digital signal (all "1''), and converts the level that is lower than the lower limit reference voltage VL into a 4-bit digital signal (all "1''). It is converted into a digital signal (all O'') and output. This A/D conversion circuit 1
The output signal No. 1 is decoded by the decoder 12 in synchronization with the sampling clock φS, and outputted as a bright level signal W and a dark level signal B.

Then, the bright level signal W is sent to the pulse generating circuit 2, and the dark level signal B is sent to the pulse generating circuit 3.

The pulse generating circuit 2 includes an AND circuit 21, for example 40
96-decimal counter 22, data latch circuit 23, D/D
Consists of a converter 24, a latch circuit 25, and a brightness A/D
The bright level signal W from the conversion circuit 1 is input to the clock terminal of the counter 22 via the AND circuit 21. Also,
The latch output of the latch circuit 25 is input to the AND circuit 21 . This latch circuit 25 is latched by the clock pulse CK1 and reset by the carry signal of the counter 22.

Further, the clock pulse σ is inputted to the reset terminal page of the counter 22. And the above counter 2
The count output of 2 is latched by the data latch circuit 23 in synchronization with the clock pulse CK2 and sent to the D/D converter 24. This D/D converter 24 converts the latch data of the data latch circuit 23 into a clock pulse CK2.
D/D conversion is performed in synchronization with , and the conversion output is output to the integrating circuit 4.

The integrating circuit 4 includes a time constant circuit 41 consisting of an integrating resistor R and an integrating capacitor C, a gate circuit 42 that controls the supply of an operating voltage v1 to the time constant circuit 41, and a gate circuit 43 that controls the supply of an operating voltage v2, The output signal of the D/D converter 24 is input directly to the gate terminal of the gate circuit 43 and is also input to the gate terminal of the gate circuit 42 via the inverter 44 . The above time constant circuit 41
The time constant is set to about 2 ms, and its output is sent to the luminance A/D conversion circuit 1 as the upper limit reference voltage VH.

On the other hand, the pulse generation circuit 3 and integration circuit 5 that process the dark level signal B are configured similarly to the pulse generation circuit 2 and integration circuit 4 described above, and the details thereof will be omitted.

Next, the operation of the above embodiment will be explained with reference to the timing chart of FIG. In this example, the number of dots for each color of R, G, and B on the color liquid crystal display panel is r1.
20x160j, and the numbers of bright level signals W and @level signals B on the basic screen are each r2300J. When the brightness signal Y is sent from the video signal processing circuit to the brightness A/D conversion circuit 1, the brightness A/D conversion circuit 1 compares the brightness signal Y with the upper limit reference voltage vRH1 and the lower limit reference voltage VRL. , for a level higher than the upper limit reference voltage VRH, for example, all t11I, lower limit reference voltage V
For levels below RL, a 4-bit digital signal of all "O"' is output from the A/D conversion circuit 11. The digital signal output from this A/D conversion circuit 11 is decoded by the decoder 12 and output as a bright level signal W and a dark level signal B. The bright level signal W output from the decoder 12 is sent to the pulse generating circuit 2, and the dark level signal B is sent to the pulse generating circuit 3.

In the pulse generating circuit 2, the counter 22 is reset in synchronization with the clock pulse frame, and the clock pulse CKI is latched in the latch circuit 25. When the clock pulse c below is latched into this latch circuit 25,
The output becomes 4 (19m), and the gate of the AND circuit 21 is opened.As a result, the bright level signal W output from the decoder 12 is sent to the counter 22 via the AND circuit 21@.
, and the count-up operation of the counter 22 is started. This counter 22 counts the bright level signal W sent from the decoder 12 for one field, and the count contents are transferred to the data latch circuit 23 in synchronization with the clock pulse (lower) when moving to the next field. is latched and sent to the D/D converter 24. In this case, when a signal of r4096J or more is sent from the decoder 12 to the counter 22 within one field, a carry signal is output from the counter 22 and the latch circuit 25 is reset. This closes the gate of the AND circuit 21 and prohibits further input. The D/D converter 24 performs the D/D conversion operation shown in FIG. 3 depending on the contents of the data latch circuit 23. Figure 3 shows counter 2
2 shows the operation of the D/D converter 24 when, for example, the count value r1000j is latched in the data latch circuit 23. The D/D converter 24 is
A D/D conversion operation is performed according to the contents of the data latch circuit 23. That is, the D/D converter 24 is reset by the clock pulse φ2 when the field changes, and converts each field from the 1st block to the 13th block.
The block is equally divided into 13 blocks, and the time width of each block is obtained by counting 4096 clock pulses φ2. Further, the first to thirteenth blocks are equally divided into 16 blocks from the first small block to the 16th small block, and each small block corresponds to 256 clock pulses φ2. Then, the D/D converter 24
to the 16th small block, the data latch circuit 23
A pulse signal with a time width corresponding to the latch data is output. For example, the data latch circuit 23 has a count value r100.
When 0J is latched, the 1st to 8th small blocks are pulse signals with a time width of 263 clock pulses, and the 9th to 16th small blocks are pulse signals with a time width of 262 clock pulses. Output.

That is, the count value r1000J is averaged and divided into the first to 16th small blocks. and,
The signals of the first to sixteenth small blocks are sent to the integrating circuit 4 as outputs of the D/D converter 24.

The integration circuit 4 opens the gate of the gate circuit 43 and outputs the voltage V2 to the time constant circuit 41 while a high level signal is applied from the D/D converter 24 to each of the first to sixteenth small blocks. While the low level signal is applied, the gate circuit 4 is activated by the output of the inverter 44.
The gate No. 2 opens and outputs the voltage ■1 to the time constant circuit 41. This time constant circuit 41 integrates the voltages V2 and Vt applied to its input point a via the gate circuit 43 or gate circuit 42, and uses the integrated voltage as an upper limit reference voltage VH to supply the luminance A/D conversion circuit 1. give. The above voltage V
1 is the lower limit value of the luminance signal Y, and voltage 2 is the upper limit value. Therefore, when the latched data of the data latch circuit 23 in the pulse generation circuit 2 is rOJ,
The output of the D/D converter 24 is always at a low level, so the output of the gate circuit 42 becomes "°1", the gate of the gate circuit 42 is opened, and the voltage v1 is output as the upper limit reference voltage VH.

Also, the latch data of the data latch circuit 23 is “409
6'', the output of the D/D converter 24 remains at a high level, so the gate of the gate circuit 43 is opened and the voltage V2 is output as the upper limit reference voltage VH.

Therefore, the latch data of the data latch circuit 23 is "1".
Each time the output of the integrating circuit 4 decreases, "i V2-Vt
l , decreases by /4096J. If the latch data of the data latch circuit 23 is "2300J," the integrating circuit 4
The upper limit reference voltage VH outputted from the circuit has a level approximately intermediate between voltages V1 and V2.

On the other hand, in the pulse generating circuit 3 and the integrating circuit 5 that process the dark level signal B output from the brightness A/D converter circuit 1, the bright level is processed in the same way as the processing for @W, and the integrating circuit 5 Lower limit group from? The $ lightning voltage t is output and sent to the luminance A/D conversion circuit 1.

As described above, the upper limit reference voltage VH according to the luminance signal Y is
1 lower limit reference voltage VL is output from the integrating circuit 4.5, and the brightness A is adjusted according to this upper limit reference voltage VH1 lower limit reference voltage VL.
The A/D conversion operation of the /D conversion circuit 1 is controlled.

Further, the output of the integration circuit 4.5 is sent to a level shifter 6a,
6b and 6c, and their outputs are red A as the upper limit reference voltage VH' and lower limit reference voltage VL'.
/D conversion circuit 7a, green A/D conversion circuit 7b, blue A/
The signal is sent to the D conversion circuit 7C. These A/D conversion circuits 7a, 7b, 7C are level shifters 6a, 6b,
Upper limit reference voltage VH', lower limit reference voltage VL' from 6C
Accordingly, the color signals R, G, and B are A/D converted into 4-bit digital signals 200 times within 1H and output to the color liquid crystal display circuit. Now, for example, if a general screen is switched to a bright screen and the number of all 1's output from the brightness A7/'D conversion circuit 1 increases, then the pulse generation circuit 2
The first to sixteenth signals output from the D/D converter 24 of
The signal time width in the small block becomes longer, and the integration circuit 4
The upper limit reference voltage VH outputted from the lower limit increases. This upper limit reference voltage VH is fed back to the luminance A/D conversion circuit 1, and is level-shifted by level shifters 6a and 6b16C, and is converted into the upper limit reference voltage VH'N and lower limit reference voltage VL' to the A/D conversion circuit 7a, It is input to 7b and 7C. These A/D conversion circuits 7a, 7b, IC
performs A/D conversion operations for the R, G, and B color signals, respectively, according to the upper limit reference voltage VH' and the lower limit reference voltage VL', but as the upper limit reference voltage H' rises,
The output signal level decreases by that amount, and therefore an image with the same brightness as before is displayed. In this way, images with stable contrast are always displayed.

In the above embodiment, the A/D conversion circuit for color video signals has been described, but when applied to monochrome video signals, the circuit is as shown in FIG. 4. This figure is almost the same as the circuit in Figure 1, so a detailed explanation will be omitted, but the luminance A/D conversion circuit 1
A video signal is inputted to the luminance A/D conversion circuit 1 via the signal line DL, and the upper limit reference voltage VH is outputted from the integrating circuit 4, and the lower limit reference voltage Vt is outputted from the integrating circuit 5.
The upper limit reference voltage VH- is fed back to the video signal A/D conversion circuit 7d via the level shifter 6d.
1 lower limit reference voltage VL'. By manually changing the potential applied to the input terminal 6d1 of the level shifter 6d, the brightness standard can be changed as desired.

[Effects of the Invention] As detailed above, according to the present invention, the luminance signal is
An independent luminance A/D conversion circuit is provided to convert the luminance, and a reference voltage for the luminance A/D conversion circuit is created from the output signal of the luminance A/D conversion circuit, and the level is further adjusted and applied as a reference voltage to the video signal A/D conversion circuit. As a result, the reference voltage creation method used in monochrome televisions can be used even in color televisions without complicating the circuit configuration so much, and a color video signal with good contrast can be obtained.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the overall schematic configuration of an embodiment of the present invention, Fig. 2 is a circuit configuration diagram showing details of the main parts of Fig. 1, and Fig. 3 is a timing chart for explaining the operation. FIG. 4 is a block diagram showing the overall schematic configuration of another embodiment of the present invention. 1... Brightness A, -D conversion circuit, 2.3... Pulse creation circuit, 4.5... Integrating circuit, 6a to 6d... Level jitter, 7a... Red A/D conversion circuit , 7b...
Green A, / [) Conversion circuit, IC... Blue A, /
D conversion circuit, 1d... Video signal A/D conversion circuit.

Claims (2)

[Claims] (1) A first A/D conversion circuit that A/D converts a television video signal according to an upper limit reference voltage and a lower limit reference voltage, and a bright level signal and a dark level signal output from this first A/D conversion circuit. means for setting the upper limit reference voltage and lower limit reference voltage according to the above and feeding them back to the first A/D conversion circuit; and A/D converting the television video signal according to the set upper limit reference voltage and lower limit reference voltage. A video signal A/D conversion circuit comprising: a second A/D conversion circuit for obtaining a digital video signal. (2) R, G, and B A/D conversion circuits that A/D convert the color signals R, G, and B of the color television video signal according to the upper limit reference voltage and lower limit reference voltage, respectively, and the upper limit reference voltage and lower limit reference voltage. Therefore, a luminance A/D conversion circuit that samples the average video signal of color signals R, G, and B, and a luminance A/D conversion circuit that samples the average video signal of color signals R, G, and
The brightness A/D conversion circuit and A of R, G, and B according to the bright level signal and dark level signal output from the D conversion circuit.
1. A video signal A/D conversion circuit comprising means for setting an upper limit reference voltage and a lower limit reference voltage of the A/D conversion circuit.