JPH0887246A - Video display device - Google Patents

Abstract

PURPOSE: To automatically perform operation by a circuit in a display device not by visual and manual means for performing the fittest image display adjustment by performing recognition of display dignity of a display video. CONSTITUTION: A video amplifier 2 amplifies an inputted video signal to the signal of a proper level, and the signal is A/D converted by an A/D converter 4. A horizontal position shifter 9 forms a synchronizing signal with an optional delay from an inputted horizontal synchronizing signal, and a vertical position shifter 10 forms the synchronizing signal with the optional delay from an inputted vertical synchronizing signal. A skew generator 11 forms a clock for display from the horizontal synchronizing signal. A trigger generator 8 forms the clock with optional delay from the former clock. A latch circuit 6 gains the video in an optional position in a video field. A system microcomputer 1 controls the videos by a prescribed method from gained video information.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video display device,
The present invention relates to a video display device having the same display pixel configuration as the video information amount. For example, it is applied to a video display device using a liquid crystal display device for data display applications for personal computers, workstations and the like.

[0002]

2. Description of the Related Art For example, a case of displaying an image using a personal computer as an image device on an image display device using a liquid crystal image element will be described. The video signal is assumed to be composed of a horizontal synchronizing signal, a vertical synchronizing signal, and a video signal, but even a signal in which these are combined is only the difference between the presence and absence of the separation circuit. FIG. 12 is a block diagram of a conventional liquid crystal display device. In the figure, 41 is a video amplifier, 42 is a gain control, 43 is an A / D converter, 44 is a γ correction circuit, 45 is a skew generator, and 46 is a PLL. (Phase
Locked Loop circuit, 47 is a horizontal position shifter, 48 is a vertical position shifter, and 49 is a liquid crystal display element.

The video signal is first input to the video amplifier 41, amplified to an appropriate level, and then A / D converter 43.
Is converted to digital. After being processed by the characteristic compensation circuit 44 such as γ correction, it is input to the liquid crystal display element and displayed. Further, there are a horizontal position shifter 47 and a vertical position shifter 48 for inputting a vertical synchronizing signal and a horizontal synchronizing signal, and for setting an optimal phase relationship for displaying an image on the liquid crystal display element 49. A horizontal clock signal and a frequency division ratio suitable for display are set in the PLL circuit 46 to generate a dot clock, which serves as a clock for the sample of the A / D converter 43 and also for a video sample of the liquid crystal display element. Is also supplied to the liquid crystal display element 49.

If the specifications of the horizontal synchronizing signal and the vertical synchronizing signal do not strictly match on the video signal side and the display device side, the contrast of characters or the like is bad, or the distortion of images such as characters or lines occurs. Further, the display quality is deteriorated such that the display positions do not match and information is lost in the periphery. For this reason, there may be no problem depending on the combination of the video signal side and the display device, but there is a combination in which the display quality is deteriorated, and there is a compatibility between the devices. Depending on the frequency band, the influence of the transmission cable may be considered. When avoiding the above-mentioned event, or when the user's computer, etc. does not meet the regulations, while displaying the image on the target display device, the user can visually check the screen displayed manually. It is necessary to work to improve the display quality by operating the adjustment switch. The following work can be considered as adjustment items.

(1) Poor contrast of image quality adjustment characters has a problem in the timing of sampling video signals to the liquid crystal display device in the video display device. In the case where the phase relationship between the video and the sampling clock (referred to as a dot clock) is, for example, as shown in FIGS. 11A and 11B, although it is originally one 100% luminance point, the actual In the display, two 50% luminance points are displayed. In order to avoid this, the phase of the change point of the dot clock and the video signal should be shifted, but a switch that shifts the phase while observing this displayed image is provided, and 100% brightness is 1 Make adjustments so that only one is displayed.

(2) Video level adjustment Among video signals, there are cases where the signal level is not protected, and the signal level is lowered due to attenuation in the transmission cable, which causes deterioration of the video quality. . Therefore, the gain can be adjusted by the video amplifier at the input stage, and it can be adjusted to an appropriate level. This is also visually adjusted to an appropriate level.

(3) Horizontal / Vertical Display Position Adjustment The horizontal image display start time is defined by the time from the horizontal synchronizing signal, but it is often strictly different depending on the type of the image signal. As can be seen from the adjustment explanation, a difference of one pixel may occur. In data display applications, the difference may be a problem, so strict adjustment is required. Therefore, the signals are displayed on the video signal side for the entire left and right video display periods so that the video can be visually displayed. As the circuit, a circuit that shifts the phase of the horizontal synchronizing signal that starts the display of the first pixel in the horizontal direction of the liquid crystal display element is configured. The same applies to the vertical display position.

[0008]

In the conventional image display device, it is necessary to perform the manual work while visually observing the displayed image, and the adjustment requires familiarity with the operation and familiarity with the adjusting method. Also, since the operation is complicated, it is very troublesome even if you get used to it. Further, when the user wants to connect the video display device to another video device, the user needs to perform the adjustment process again, which is inconvenient for the user.

On the other hand, when the pixel configuration of the display device is not sufficiently fine with respect to the pixel configuration of the target video signal, the minimum structural unit of the pixel corresponds to the minimum structural unit of the target video. Moreover, unless the minimum unit of the display element corresponds to an integral multiple of the minimum constituent unit of the image, the quality of the displayed image is significantly deteriorated. In the case of a video signal for such an application, a signal level change of 100% and 0% for each pixel is not uncommon, and there is a feature that faithful reproduction of such a signal is required. Further, the target is a signal in which the sync signal does not exist at the level change point of the video signal but only the horizontal sync signal and the vertical sync signal exist.

Further, in the case where the image display device does not have the number of constituent pixels having a margin larger than the number of constituent pixels of the image to be reproduced (the same case), the image information in the periphery of the screen is not lost. In addition, it is necessary to accurately control and configure the video signal. However, in reality, it cannot be said that the time relationship between the sync signal and the video signal satisfies the necessary and sufficient conditions described above, and depending on the compatibility between the video device and the display device, the video quality is The problem of being extremely inferior occurs. In such applications, there is a demand for a video display capable of displaying a high-quality video by absorbing the difference between the video devices in the display device.

The present invention has been made in view of such circumstances, and in order to perform the optimum image display adjustment by recognizing the display quality of the display image in the circuit of the display device, the image display is performed. It is an object of the present invention to provide a video display device in which an operation is automatically performed by a circuit in the display device instead of visual and manual operations.

[0012]

In order to solve the above-mentioned problems, the present invention provides an amplification means for amplifying an input video signal to a signal of a proper level, and an amplification means for amplifying the signal to a proper level signal. Sampling means for sampling a video signal, a synchronizing signal generating means for producing a synchronizing signal with an arbitrary delay from the input horizontal synchronizing signal, and a synchronizing signal generating means for producing a synchronizing signal with an arbitrary delay from the inputted vertical synchronizing signal A synchronizing signal generating means, a clock generating means for generating a clock for display from the horizontal synchronizing signal, a clock generating means for generating a clock with an arbitrary delay from the clock of the clock generating means, and an arbitrary clock in the video field. An acquisition means for acquiring the image of the position and a microcomputer capable of controlling the image information in a predetermined method from the acquired image information are provided. It is obtained by, characterized in that.

[0013]

The video display device of the present invention having the above-mentioned structure, means for amplifying the input video signal to a signal of an appropriate level, means for sampling the same, and an arbitrary delay from the input horizontal synchronizing signal. Means to make the sync signal you have,
In the video field, a means to make a sync signal with an arbitrary delay from the input vertical sync signal, a means to make a clock for display from a horizontal sync signal, and a means to make a clock with an arbitrary delay from it. By adding a means to acquire an image at an arbitrary position and a microcomputer that can control them from the acquired image information in a predetermined method, a small number of circuits and a small amount of a microcomputer program can be added. Thus, the adjustment associated with the video equipment such as the data display equipment can be extremely simplified.

That is, a specific but simple video display is made to be displayed on the video equipment, the video display equipment is input, and the user presses a button or the like on the video equipment. As a result, the microcomputer examines the image in the internal circuit, and by knowing the state of the image, it is possible to optimize the image level so as to eliminate the deterioration of the vertical and horizontal image display positions and display quality. By.

[0015]

Embodiments will be described below with reference to the drawings. FIG. 1 is a configuration diagram for explaining an embodiment of a video display device according to the present invention. In the figure, 1 is a system microcomputer (microcomputer), 2 is a video amplifier, 3 is a gain controller, and 4 is an A / D. Converter (ADC) 5, gamma correction circuit, 6 latch circuit, 7 PLL (Phase Lo)
cked loop circuit, 8 is a trigger generator, 9 is a horizontal position shifter, 10 is a vertical position shifter, 11
Is a skew generator, and 12 is a liquid crystal display element. In addition,
A personal computer or the like can be considered as a device that outputs a video signal, but in this embodiment, the output video and the signal device are simply described.

Each block constituting this embodiment will be described below. First, the trigger generator will be described. FIG. 2 is a circuit diagram of the trigger generator. In the figure, 21 is an up counter, 22 is a comparison circuit, 23 is an OR circuit, 2
4 is a TH register, 25 is an up counter, 26 is a comparison circuit, 27 is a TV register, and 28 is a delay element.

By setting the video position to be generated in the register of the trigger generator 8 by the path of the system microcomputer 1, the video of an arbitrary video position can be sampled. For example, in the horizontal direction, two dots are used as the dot clock. More specifically, with the horizontal synchronization signal as the start position, one cycle of the dot clock corresponds to one dot of the video signal from that position. 3) in the vertical direction and to sample the video of the fourth line in the vertical direction, by setting “2” in the TH register and “4” in the TV register by the path of the system microcomputer 1, Generate signal LTCLK as in e). The image is sampled by the latch circuit 6 by the signal LTCLK, and the signal INT (FIG. 3 (f)) is generated with a slight delay.

This is transmitted to the microcomputer 1 as an interrupt signal, and the system microcomputer 1 acquires the signal by reading the contents of the latch circuit 6 by the interrupt processing. For example, set "2" in the TH register as a signal, and
Set "4" in the register. Then, the trigger generator 8 generates a trigger pulse at the timing of the horizontal position 2 and the vertical position 4, and generates the interrupt signal INT with a slight delay. This signal is connected to the interrupt signal input of the system microcomputer 1. In response to this, the contents of the latch circuit 6 are acquired through the path of the system microcomputer 1 by the interrupt processing of the system microcomputer 1 or the like. Through this series of operations, the system microcomputer 1 can take in the value at which the image at the designated time in the image field is sampled by the program operation.

That is, for example, when it is desired to sample the video of 2 clocks in the horizontal direction and the 4th line in the vertical direction, "2" is set in the TH register 24 and "4" in the TV register 27 by the path of the system microcomputer 1. By setting, signals as shown in FIGS. 3A to 3G are generated. The CLK shown in FIG. 3G is input to the up counter 21 and the delay element 28. Also,
The HCLK shown in FIG. 3B corresponds to the up counter 21.
Is input to the up counter 25. VCLK shown in FIG. 3A is input to the RES of the up counter 25. The output of the up counter 21 and the output of the TH register 24 are compared by the comparison circuit 22, and when both outputs are equal, the signal shown in FIG. 3 (d) is output. Also, the output of the up counter 25 and the TV register 2
The output of 7 is compared by the comparison circuit 26, and when both outputs are equal, the signal shown in FIG. SIG1 and SIG
2 is input to the OR circuit 23, and its output is shown in FIG.
3 is obtained via the delay element 28.
The INT shown in (f) is obtained.

An image is sampled by the latch circuit 6 by the signal LTCLK, and the signal I is slightly delayed.
Since NT is generated, this is transmitted to the system microcomputer 1 as an interrupt signal, and the system microcomputer 1 acquires the signal by interrupt processing. The system microcomputer 1 sets the trigger generator 8 so that the horizontal signal generation position is approximately the center value of the image. The time from the horizontal synchronization signal to the start of horizontal image display has not been measured yet, so it is not strictly defined, but the center value is set because there is no practical problem in the center. If the signal has 640 pixels in the horizontal direction, 320 may be designated in the TH register 24.

Next, the vertical direction is first set to "1".
Then, the trigger generator 8 generates a desired signal, is notified to the system microcomputer 1 by an interrupt signal, and takes in the sampled value from the latch circuit 6. Now, since the level of the video signal also varies depending on the video equipment, the video gain is adjusted.

Next, the skew generator will be described.
The skew generator 11 uses the dot clock 1 (FIG. 5A).
On the other hand, it is a circuit that can control the clock skew of the dot clock 2 by a microcomputer. FIG.
Is a circuit diagram of the skew generator, in which 31 is a delay element, 32 is a selector, and 33 is a register. The delay element 31 generates a clock delayed by a desired time from the input clock. That is, FIG. 5B
As shown in (e) to (e), a clock delayed by 0 delay to 9 delay is generated, and the clock is generated by the system microcomputer 1
The circuit configuration is such that selective output is performed according to the value of the register 33 set by the path of.

From the configuration of the embodiment, the skew generator 11
The dot clock 2 is an output clock that causes a delay (skew) of an arbitrary value from the dot clock 1 which is an input signal in a time unit smaller than one cycle time of the clock according to the setting value of the system microcomputer 1. Is a circuit that causes. The value may be set in the register 33 of the skew generator 11. Note that the delayed amount of delay is determined by being applied to an applied device, and is set to 10 in this embodiment for convenience of description.

Next, the A / D converter will be described. According to the specifications of the liquid crystal display element 12, assuming that the conversion resolution is 8 bits, it is expected that a 0% luminance signal is converted to 00h (h represents hexadecimal notation) and a 100% luminance signal is converted to FFh. Suppose In such a case, it is determined whether or not an effective video signal is present in the first line by performing the determination with 80h as the threshold value.

If the line sequential number is increased from 1 by 1, the effective video period start position in the vertical direction can be obtained. Further, if it is further continued, the end position of the effective image period can be known, and the period of the effective image in the vertical direction can be known. This makes it possible to display the video signal at the display position most suitable for the video display element. That is, the first line of the video to be displayed can be displayed on the first line of the video screen.

When a video signal having an effective video signal of 400 lines is to be displayed on a liquid crystal display device having 480 lines, 40 lines are not vertically displayed and the middle 400
It is also possible to display the center on the display screen by setting the video signal to be displayed on the line. As a result, the set value for the vertical position shifter 10 is determined, set, and recorded by the system microcomputer 1 as the set value.

Each function of the present invention will be described below. (1) Vertical image range / centering adjustment A signal as shown in FIG. 6 is generated as an output image from a signal device. This is a signal such that the video period (effective video period) that can be output from the video device is 100% luminance. After such a signal is input, the user notifies the display device. For example, a button indicating a function for adjustment may be attached to the display device, and the meaning that the user presses the button is to perform the adjustment. In addition, the same applies to the communication control function between the system microcomputer 1 and an external device such as a remote controller or a device control function, which is optional.

That is, the signal as shown in FIG. 5 is such a signal that the effective image period is all 100%. With such a signal inserted, the system microcomputer 1 causes the trigger generator 8 to move in the horizontal direction. Set so that the signal generation position of is at the center of the image. Specifically, first, the center position is designated in the horizontal direction in order to reliably sample the image. If the signal has 640 pixels in the horizontal direction, "320" is specified as the position.
“320” is set in the H register 24. Next, in order to specify the vertical direction at 1H, the TV register 27 is set to "1".
Set. Then, by the trigger generator 8, the horizontal position "320" and the vertical position "1" are obtained by the series of operations described above.
The system microcomputer 1 can capture the value sampled at the timing of.

For example, if the conversion resolution of the ADC4 is 8 bits, then 80h (h represents hexadecimal notation)
It is possible to determine whether or not the effective video signal is present on the first line by performing the determination with the threshold as. If the line sequential number is increased from 1 by 1, the effective video period start position in the vertical direction can be obtained. Further, by continuing further, it is possible to know the end position of the effective image period, and it is also possible to know the period of the effective image in the vertical direction. This makes it possible to display the video signal at the display position most suitable for the video display element.

Further, a display device having 480 lines has 40
When displaying a video signal having an effective video signal of 0 line, it is possible to display the video signal in the center of the display screen by setting the video signal to be displayed in the middle 400 lines without displaying 40 lines vertically. It is also possible. In this way, the set value for the vertical position shifter 10 is determined,
It is set and recorded as a set value by the system microcomputer.

(2) Gain (Amplitude) Adjustment of Video Signal The video gain is adjusted when it is determined in the process of 1 that an effective video signal exists. When the effective video signal is sampled and already FFh, the ADC 4 may exceed the upper limit of the convertible signal. Also,
It may be low such as F8h. In such a case, the gain / amplitude of the video gain (amplitude) is controlled by the gain controller 3 for gain adjustment, that is, the gain is reduced by one step, and then sampled again at the same place. Continue this until it becomes FEh. If it is increased by one step at that point, the ADC 4 will have a proper amplitude of the video signal. On the other hand, if it is FEh or less,
The video amplitude is increased by one step by the gain controller 3 for gain adjustment, and then sampled again. This is continued until it becomes FFh. The value of the gain controller 3 for adjustment at this time is set as an initial setting value.

(3) Video-to-dot clock phase optimization adjustment: The horizontal phase is set to 0 and the dot clock phase is set to 0. The signals at this time are shown in FIGS. 7 (a) and 7 (b). As the video signal, a signal that is composed only of a point having 100% luminance and a point having 0% luminance is used. This may be a case where characters having 100% brightness are displayed on a black screen. When scanning such a signal 100
There is no problem if it is sampled as a signal of% luminance and 0% luminance, but if the rising edge of the horizontal synchronizing signal is blunted or there is a skew with the video signal, the phase difference between the video signal and the sampling clock Can be the timing when accurate sampling is not performed.

That is, it is possible that the ADC 4 is sampling and converting the image during the rising and falling periods of the image signal. For example, in the case of the phase relationship as shown in FIG. 11, it is recognized as a signal such as 50% luminance. At this time, the display quality of characters and the like in the display image is degraded. To improve this, the phase of the dot clock is increased. The system microcomputer 1 is
By changing the setting value of the skew generator 11, FIG.
The dot clock is moved while maintaining the relationships shown in (c) to (e). At the same time, the system microcomputer 1 samples the image, but the image signal is recognized as the brightness increases.

Continuing this is the same as measuring the video signal in time series. This state is recorded by the system microcomputer 1, and it is possible to know the phase relationship between the image and the dot clock that sufficiently satisfies the sample-hold relationship for conversion of the ADC 4, and the skew generator 11 Is set.

That is, in order to find the change point of the video signal, the following steps 1 to 9 are performed. step1 : First, a video signal having a video brightness of 0% and 100% is input as a video signal. For example, a signal such as character information can be considered. step2 : Next, the VS obtained in the step (1) is set in the TV register. step3 : Set "1" to the TH register. Step 4 : After that, if the contents of the latch circuit 6 are acquired, the video signal at that time can be acquired, as described in (1) above. step5 : Next, the set value of the TH register is incremented by 1 and the contents of the latch circuit 6 are acquired.

Step 6 : If there is a change in the video signal, the TH register value at that time is defined as THS and the process proceeds to the next step. If there is no change, the process returns to step 5 and the contents of the latch circuit 6 are enhanced. At this time, if the number of constituent image pixels in the horizontal direction is 640, for example, the TH register 24 has 64 pixels.
When it becomes 0 or more, the TV register 27 is incremented by 1 and T
The H register 24 is set to "1" and the process is repeated from step 5. step7 : In order to obtain the change point of the video signal, by performing the above, for example, in the time series such as setting THS-1, THS, THS + 1 in the TH register, as shown in FIG. It is assumed that the clock phase relationship is 11.

[0037] step8: Examples The following step, will be described with reference to FIG. When TH = THS, 0 shown in FIG.
It is assumed that there is a phase relationship between the video and the dot clock such that dot clock 1 comes at the time. Register D
If T = 0 is set, dot clock 1 and dot clock 2 are at the same time. Here, when "1", "2", ..., "9" are set in the register DT, the dot clock 2 is sequentially set to the times "1", "2", ..., In FIG.
Suppose that it occurs at "9".

As described above, the problem in the phase relationship between the dot clock and the video signal is when the sampling and holding time of the ADC 4 is not sufficient. Specifically, the sampling and holding time of the ADC 4 is 9
When only 5 is required on the time axis in, when the image is sampled by the ADC4 at time 0, the change in the image has already finished rising, as if it were 100.
It seems that sampling can be performed with% luminance, but since the integrated value in the illustrated period is actually converted,
It is only the value of the sample value at 0 shown in. For the sake of explanation, this shows a specific example of the case where the integrated value in the hold time becomes the converted value in the ADC 4 in the general ADC 4.

"1", "2", ..., In the register DT
When “9” is set, the dot clock 2 sequentially moves at time “1”, “2”, ..., “9” on FIG. 9, but the sampling conversion value at the ADC 4 at this time is As described above, since they are the integrated value of the video signal at each sampling and holding time, they have the relationship shown in FIG. Conversely, if the values shown in FIG. 10 can be acquired, it can be detected that the video signal has the changes shown in FIG. Therefore, DT = 0, 1, ..., 9 are sequentially increased, sampling is performed, the value is acquired by the latch circuit 6, and the system microcomputer 1 selects the maximum DT value among 0 to 9. . In this example, DT = 5
Becomes step9 : Then, the register DT of the skew generator 11 =
5 is set, and this is recorded in a non-volatile memory or the like as needed, and is used as a set value at power-on.

(4) Horizontal video range / centering adjustment As for the video signal, the signal shown in FIG. 6 is generated as an output video from the signal device as in the vertical direction. This is a signal such that the video period (effective video period) that can be output from the video device is 100% luminance. The TV register 27 uses the trigger generator 8 to perform sampling by setting the TH register 24 to "1" at an arbitrary position in the effective video period obtained above. Whether the value is a valid video signal is determined in the same manner as in the determination of the valid period in the vertical direction, and if the value of TH is sequentially increased, the video display start position in the horizontal direction can be determined. The same applies to the end position. As a result, the effective video period in the horizontal direction can be known, and the value is set in the horizontal position shifter 9 and recorded by the system microcomputer 1 as the set value.

That is, by using the trigger generator 8, T
The V register 27 is set at an arbitrary position in the effective video period, TH
First, the register 24 is set to "1" to perform sampling. Whether the value is a valid video signal is determined in the same manner as in the determination of the valid period in the vertical direction, and if the value of TH is sequentially increased, the video display start position in the horizontal direction can be determined. Also,
The end position is also the same. As a result, the effective video period in the horizontal direction can be known, and the value is set in the horizontal position shifter 9 and recorded by the system microcomputer 1 as the set value. The signal of FIG. 10 is generated as an output image from the signal device. Specifically, "240" is set in the TV register 27. Next, "1" is set in the TH register 24 to specify the horizontal direction as the first picture element.

Then, the trigger generator 8 generates a trigger pulse at the timing of the horizontal position "1" and the vertical position "320", and the system microcomputer 1 receives the interrupt signal.
Then, the system microcomputer 1 receives the sampled value from the latch circuit 6 and determines the presence / absence of a video signal. For example, if the conversion resolution of the ADC is 8 bits, 80h (h represents hexadecimal notation)
Is used as a threshold to determine whether or not an effective video signal is present at the TH video pixel position.

If the sequential number for each picture element is increased from 1 by 1, the effective effective period start position in the horizontal direction can be obtained. At this time, HS = TH. Further, if it continues further, the end position of the effective image period can be known, and the period of the effective image in the horizontal direction can be known.
This makes it possible to display the video signal at the display position most suitable for the video display element. For example, horizontal 72
When displaying a video signal having an effective video signal of 640 picture elements on a display element having 0 picture elements, do not display 40 lines on the left and right, and make settings to display the video signal on the central 640 picture element. It is also possible to display the center on the display screen with. In this way, the set value in the TH register of the horizontal position shifter 9 is determined and set, and is recorded as the set value by the system microcomputer 1.

[0044]

As is apparent from the above description, according to the present invention, by combining a video device and a video display device, a specific but simple video display, which was conventionally complicated and troublesome, can be applied to a video device. Input to the video display device, and the user optimizes the video level so that the video display position in the vertical / horizontal direction and the deterioration of the display quality can be eliminated by the user pressing a button etc. on the video device. It is done by a microcomputer. As a result, the device can be adjusted quickly and easily to improve the display quality, and the effect of significantly reducing the burden on the user of the device can be obtained. In addition, the video equipment can control the video display device by a general-purpose communication method,
If the image can be changed at the same time, adjustment can be performed with almost no operation for all uses.

[Brief description of drawings]

FIG. 1 is a configuration diagram for explaining an embodiment of a video display device according to the present invention.

FIG. 2 is a circuit diagram of a trigger generator according to the present invention.

FIG. 3 is a diagram showing signals of respective parts of the trigger generator in FIG.

FIG. 4 is a circuit diagram of a skew generator according to the present invention.

FIG. 5 is an operation explanatory diagram of the skew generator according to the present invention.

FIG. 6 is a diagram showing an output video signal (all white screen) according to the present invention.

FIG. 7 is a diagram for explaining a video-to-dot clock phase optimization adjustment in the present invention.

FIG. 8 is an explanatory diagram of video / dot clock phase adjustment in the present invention.

FIG. 9 is a diagram showing a relationship between video and sampling time in the present invention.

FIG. 10 is a diagram showing a relationship between a sampling time and a conversion value in the present invention.

FIG. 11 is a diagram for explaining how distortion is occurring.

FIG. 12 is a configuration diagram of a conventional liquid crystal display device.

[Explanation of symbols]

1 ... System microcomputer (microcomputer), 2 ...
Video amplifier, 3 ... Gain control, 4 ... A / D converter (ADC), 5 ... γ correction circuit, 6 ... Latch circuit, 7
... PLL (Phase Locked Loop) circuit, 8 ... Trigger generator, 9 ... Horizontal position shifter, 10 ...
Vertical position shifter, 11 ... Skew generator, 12 ... Liquid crystal display device, 21 ... Up counter, 22 ... Comparison circuit, 23
... OR circuit, 24 ... TH register, 25 ... Up counter, 26 ... Comparison circuit, 27 ... TV register, 28 ... Delay element, 31 ... Delay element, 32 ... Selector, 33 ... Register.

Claims (1)

[Claims] 1. An amplification means for amplifying an input video signal to a signal of an appropriate level, a sampling means for sampling the video signal amplified to an appropriate level signal by the amplification means, and an input horizontal synchronizing signal. From the horizontal synchronizing signal, a synchronizing signal generating means for producing a synchronizing signal with an arbitrary delay, a synchronizing signal generating means for producing a synchronizing signal with an arbitrary delay from the input vertical synchronizing signal, and a clock for display from the horizontal synchronizing signal. , A clock generating means for generating a clock with an arbitrary delay from the clock of the clock generating means, an acquiring means for acquiring an image at an arbitrary position in the image field, and a predetermined value from the acquired image information. And a microcomputer capable of controlling the video information according to the method described in 1 ..