JPS61193485A - Method for manufacturing thin film transistor array - Google Patents

Abstract

PURPOSE:To reduce troubles of resists being peeled off, by separating forming and patterning of underlying N<+> layer and Ti layer from forming and patterning of an upper Al layer, when source and drain contacts of a TFT having a three- layer structure are formed. CONSTITUTION:After contact holes are formed through an SiN layer 5 for passivation and SiN layer 3 for gate insulating, an N<+> layer 6 is formed with P-CVD and then a Ti layer 7 is evaporated. Next, The resists 11 are patterned in source and drain shapes and are removed after the Ti layer 7 is etched. Using the Ti layer 7 as a mask, the N<+> layer 6 is etched with NaOH solution. After Al 8, 9 is evaporated, the resists 11 are patterned again in the source and drain shapes. Last, after the Al is etched, the resists are removed to finish the device. In this way, troubles owing to resists being peeled off can be reduced, because the number of etchings which is done by one resist patterning is not plural.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a thin film transistor array used for switching liquid crystal of a liquid crystal display panel.

(Prior Art) In recent years, TFT arrays in which each pixel is provided with a thin film transistor (TPT) as a switching element for driving large-area liquid crystal panels are about to enter the practical stage as a display device to replace CRTs.

An example of a TFT array will be described below with reference to the drawings. FIG. 9 is a simple plan view of the TFT array.

G,, G2... are gate electrodes, Dl, D2...
. . . is a drain electrode, and L□lL2 . . . is a picture element electrode connected to the source electrode. FIG. 10 shows the equivalent circuit of FIG. Figure 11 shows the TFT in Figure 9 with the broken line A.
- It is a sectional view cut at the part A. In the figure, 1 is a transparent glass substrate, 2 is a gate, 3 is a SiN layer for gate insulation, 4 is an amorphous silicon (α-3i) layer which is a semiconductor layer,
5 is a passivation SiN layer, 6 is a doped amorphous silicon (n+) layer, 7 is a Q diffusion prevention layer, 8 is a drain electrode, and 9 is a source electrode. Al is used for the drain electrode 8 and source electrode 9. TiJ is used in the diffusion prevention layer 7.
, Ti, Mo, Zr, etc. can be used. 10 is a transparent picture element electrode (ITO). Here n+
The layer is used to maintain ohmic contact between the metal and α-5j. Further, the diffusion prevention layer 7 is made of Al
This is used to prevent the OFF resistance of TPT from increasing due to diffusion into α-3i. The operation of the TFT array constructed as described above will be explained below. This display panel is driven line-sequentially. That is,
In FIG. 10, gate line G□.

A scanning pulse is sequentially applied to G2... to turn on the TPT, and in synchronization with this, the drain lines D1... D
A video signal pulse is applied from 2..., charges are accumulated in the liquid crystal whose electrodes are picture elements, and the liquid crystal becomes transparent and appears white (or non-transparent and appears black).

When the scanning pulse is no longer applied to the gate line, TPT
is in the OFF state. At this time, a discharge starts through the TPT's OFF resistance and the liquid crystal's resistance, but since these values are sufficiently large compared to the TPT's ON resistance, the potential is maintained until the next gate selection and display is performed (for example, "LCD"). 1 ~ Fundamentals and Applications of Ronics” (Ohmsha), Akio Sasaki P147).

An outline of a method for manufacturing a conventional T-togo array having the above-mentioned configuration and operation will be explained. The outline of the process is sequentially shown in FIGS. 5 to 8. In FIG. 5, after forming a gate 2 and a transparent picture element electrode 10 on a transparent glass substrate 1, a gate insulating SiN layer 3, an α-5i layer 4, SiN for passivation
Layer 5 is continuously formed. Next, as shown in FIG. 2, the SiN layer 95 for oxidation and the α-8i layer 4 are patterned by photolithography to increase the height of the transistor portion. BH is used for etching the passivation SiN layer 5.
F (mixture of IIF and N114F) is used. For etching the α-5i layer 4, caustic acid (NaOH) is used. Next, in FIG. 7, the passivation SiN layer 5 and the gate insulating SjN layer 3 are simultaneously patterned by photolithography, and the source and drain contacts 1 to 1 are formed.
A hole and a hole for the picture element electrode section are made. Next, the eighth
As shown in the figure, after forming an n+ layer 6 by the p-cvo method, an AΩ diffusion prevention layer 7 and Al layers 8 and 9 are deposited. The resist is patterned into source and train shapes by photolithography. After etching Al, A [diffusion prevention layer 7 and n+ layer 6 are etched in order while leaving the resist. At this time, for etching Al, a mixed solution of phosphoric acid (upo, -), acetic acid (C1, COO11), nitric acid (HNO3), or ferric chloride (FeC (!)) is used.
3), ml (ocQ) can be used. When the diffusion prevention layer 7 is made of titanium (Ti), hydrofluoric acid (IF) is used.

Hereinafter, it is assumed that the Al diffusion prevention layer is made of Ti. NaOH solution is used for etching the n+ layer. In addition, Ti layer, n
Hydrofluoric acid (HF and HN4F) that can simultaneously etch the + layer.
(mixture of) may also be used. The completed drawing is shown in Fig. 11.

(Problems to be Solved by the Invention) However, the above-mentioned three-layer structure contact
In the method of sequentially etching AQ, Ti, and n+ in resist patterning, Ti.

There is a problem that the n+ etching solution (l(F', Na0H) side-etches 11. Also, the resist used is immersed in three types of etching solutions until the end, and the resist surface and resist edges are partially etched. There is also the problem that there is a phenomenon of peeling off, and it is not possible to form a clean contact.

In view of the above problems, the object of the present invention is to provide a source with a three-layer structure,
It is an object of the present invention to provide a method for manufacturing a thin film transistor array in which train contacts can be formed without any trouble.

(Means for Solving the Problems) In order to solve the above problems, the method for manufacturing a thin film transistor array of the present invention includes forming an n'' layer and a Ti layer in order to form the source and drain contacts of the three-layer structure. After film formation, the Ti layer is patterned by photolithography,
Using this Ti layer as a mask, the n1 layer is patterned.

Finally, after depositing the top layer of Al, the Al layer is patterned using photolithography to match the underlying source and drain patterns.

(Function) In the present invention, the n+ layer and the Ti layer are formed and patterned in advance, and then the Al layer is vapor-deposited and patterned. The problem of side etch of Al is avoided.

(Example) A method of manufacturing a thin film 1-transistor array according to the present invention will be explained based on FIGS. 1 to 4.

The process up to forming contact holes in the gate insulating SiN layer 3 and the passivation SiN layer 5 shown in FIG. 7 in the description of the conventional example is the same. Next, as shown in FIG. 1, after forming an n+ layer 6 by P-CVD method, T
I-layer 7 is deposited, and resist 11 is applied to the source and drain shapes.
pattern. Next, as shown in FIG.
After etching, the resist 11 is removed. Next, as shown in FIG. 3, using the 11 layer 7 as a mask, the n+ layer 6 is made of Na.
Etch using OH solution. Next, as shown in FIG. 4, Li8.9 is deposited, and the resist 1-11 is patterned again in the shape of the source and drain. Finally, as shown in Figure 11, l! 8. After etching 9, Regis 1
Complete by removing .

From the second embodiment, since AΩ is deposited and patterned last, it is not etched by the etching solution for the n+ layer. Furthermore, only the resist 1 is used when etching the Tj layer, and the resist is removed when etching the n+ layer. Since multiple etchings are not performed in one resist patterning, troubles due to resist peeling are reduced.

In the examples described above, Ti was used for the Al diffusion prevention layer, but Ti-W, Mo, Zr, TiN,
ZrN or the like may be used, and the material is not limited to Ti.

(Effects of the Invention) According to the present invention, in order to form source and drain contacts of a three-layer structure of TPT, the formation and patterning of the lower n+ layer and Ti layer, and the formation and patterning of the upper By separating the formation and patterning of 11 layers,
This has the effect of eliminating side etching of the Al layer due to different types of etching solutions, and reducing the trouble of resist peeling.

[Brief explanation of the drawing]

Figures 1 to 4 are cross-sectional views showing the manufacturing process of the TFT array of the present invention, Figures 5 to 8 are cross-sectional views of TPT showing the conventional manufacturing process, and Figure 9 is an overview of the TPT array. A plan view, FIG. 10 is an equivalent circuit diagram of FIG. 9, and FIG. 11 is a sectional view of the completed TPT. 1...Transparent glass substrate, 2. Game 1~. 3 ・
... SiN layer for gate insulation, 4 ... α-5i layer, 5 ... SiN layer for passivation, 6 ...
・n+ layer, 7...Ti layer, 8...source electrode (AQ), 9...drain electrode (AQ)
', G□lG2...Gate line, D engineering 102 ・
... Drain line, Ll, L2... picture element electrode. , Patent applicant: Matsushita Electric Industrial Co., Ltd.

Claims (1)

[Claims] In an inverted staggered thin film transistor array having a structure in which the source and drain contacts are composed of three layers in order from the amorphous silicon surface: a doped amorphous silicon layer, an Al diffusion prevention layer, and an Al layer, the doped amorphous silicon layer, the Al After forming the diffusion prevention layer, the Al diffusion prevention layer is patterned by photolithography, the doped amorphous silicon layer is etched using the Al diffusion prevention layer as a mask, and then the Al layer is formed and patterned. A method for manufacturing a thin film transistor array.