JPS61171147A - How to check the coordinates of a wafer ham tup - Google Patents
How to check the coordinates of a wafer ham tupInfo
- Publication number
- JPS61171147A JPS61171147A JP1215685A JP1215685A JPS61171147A JP S61171147 A JPS61171147 A JP S61171147A JP 1215685 A JP1215685 A JP 1215685A JP 1215685 A JP1215685 A JP 1215685A JP S61171147 A JPS61171147 A JP S61171147A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- coordinates
- measurement
- chips
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はウェハマツプの座標点検方法、より詳しくはプ
ロバー、プローブカード、テスタ等を用いてなすウェハ
マツプを利用するウェハの各チップの検査のための測定
において、測定するチップがウェハマツプの正しい位置
に対応するか否かを点検する方法に関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a method for inspecting the coordinates of a wafer, and more specifically, a method for inspecting the coordinates of a wafer using a prober, probe card, tester, etc. The present invention relates to a method for checking whether a chip to be measured corresponds to a correct position on a wafer hap during measurement.
半導体装置の製造においては、ウェハが多くの同一寸法
に区分され、各区分に同じ素子が形成され、ウェハ処理
が終る・とウェハは前記各区分ごとに切断され、各区分
が1個ずつのチップとなる。In the manufacturing of semiconductor devices, a wafer is divided into many identical dimensions, the same elements are formed in each division, and wafer processing is completed.The wafer is then cut into each division, each division containing one chip. becomes.
ウェハ処理が終ると、各区分ごとにプローブカードを用
いて測定をなし、その区分に形成された素子が良品であ
るか否かを判定し、その結果はウェハマツプにメモリさ
れる。以下説明の便宜上ウェハの各区分をチップと呼称
することにし、第3図を参照すると、ウェハ31の各チ
ップ32a、 32b、。When wafer processing is completed, measurements are taken for each section using a probe card to determine whether the devices formed in that section are good or not, and the results are stored in the wafer map. For convenience of explanation, each section of the wafer will be referred to as a chip below, and referring to FIG. 3, each chip 32a, 32b of the wafer 31.
16.についてなされた測定結果は、同図伽)のウェハ
マツプ上に32a、 32b、、、、とメモリされる。16. The results of the measurements made are stored as 32a, 32b, . . . on the wafer map shown in FIG.
なお現在の一般的な測定方法によると、座標XYを図示
の如く定めた場合、最も左の最上のチップに始まりYの
下方向’(Y減方向)に測定し、最も下のチップの測定
が終るとXを1つ右にずらし、次にYの上方向(Y増方
向)に測定し、以下これを繰り返す、この試験結果は良
品か不良品のいずれかであるが、図には簡単のため黒点
を付して示す。According to the current general measurement method, when the coordinates When the test is finished, move X one place to the right, then measure Y upwards (increasing Y direction), and repeat this process.The test result is either a good product or a defective product, but the diagram shows a simple This is shown with black dots.
このようにして作成されたウェハマツプに従って不良チ
ップになんらかの表示を付けておくと、ウェハをチップ
ごとに切断したときに不良チップが容易に判別されるよ
うになる。By attaching some kind of indication to the defective chips according to the wafer map created in this manner, the defective chips can be easily identified when the wafer is cut into chips.
ウェハマツプの現実の作成に際しては、上述した如くウ
ェハマツプが作成されないことがあり、第3図(a)の
如くにプローブカードが測定したにもかかわらず、現実
にはウェハマツプが同図[0)に示される如くに形成さ
れること、すなわちウェハマツプの座標のずれが発生す
ることがある。そこで、第3図(C)の如きウェハマツ
プが得られたときは再度測定をしなければならない問題
がある。When actually creating a wafer map, the wafer map may not be created as described above, and even though the probe card measures as shown in FIG. In other words, the coordinates of the wafer may be shifted. Therefore, when a wafer bump as shown in FIG. 3(C) is obtained, there is a problem in that measurement must be performed again.
(問題点を解決するための手段〕
本発明は、上記問題点を解消したウェハマツプの座標点
検方法を提供するもので、その手段は、プロバー、プロ
ーブカード、テスタを用いてウェハ測定をなしその結果
をウェハマツプに書き込むにおいて、測定チップの座標
を、当該チップの周囲のL字型判定パターンに測定デー
タが入っているか否かによって点検し、座標ずれがある
ときは前記り字型判定パターンによって修正することを
特徴とするウェハマツプの座標点検方法によってなされ
る。(Means for Solving the Problems) The present invention provides a method for inspecting the coordinates of a wafer that solves the above-mentioned problems. When writing on the wafer map, the coordinates of the measurement chip are checked by checking whether the measurement data is included in the L-shaped judgment pattern around the chip, and if there is a coordinate deviation, it is corrected using the L-shaped judgment pattern. This is accomplished by a wafer map coordinate inspection method characterized by the following.
上記方法においては、プローブカードの進行方向に対し
て定められた座標を点検し、各座標が測定済(11°の
状態)か未判定(“0”の状態)かを判定し、その判定
結果を前辺って定められた“1”と“0”のパターンと
比較して座標ずれを判定し、座標ずれがあれば前記比較
の結果に従うて測定結果を正しい座標に記入するもので
ある。In the above method, the coordinates determined in the direction of movement of the probe card are checked, and it is determined whether each coordinate has been measured (state of 11 degrees) or has not been determined (state of "0"), and the determination result is is compared with a predetermined pattern of "1" and "0" on the front side to determine coordinate deviation, and if there is a coordinate deviation, the measurement result is written in the correct coordinate according to the result of the comparison.
以下、図面を参照して本発明実施例を詳細に説明する。 Embodiments of the present invention will be described in detail below with reference to the drawings.
第1図(a)と偽)に本発明の方法の実施を示すウェハ
マツプが示され、xY座標は図示の如くにとる。A wafer map illustrating the implementation of the method of the invention is shown in FIG.
先ず、第1図(a)を参照すると、それはプローブカー
ドがY軸を上方向に(Y増方向)動く場合を示
Jす、ウェハマツプにおいて測定中のチップの座標が(
IC,y)であるとすると、座標(x、y)のチップに
隣接するチップのうち測定済のチップ(それは測定デー
タが入っているから1”の状態をとる)はそれぞれOF
+11 !−1) 、 (3Flx−1)、 (y
−L x−1)+ (y−L x)の座標にあり、未
測定のチップ(それは未だなんらデータが入っていない
から“0”の状態にある)はそれぞれ(y”1.x+1
) 、 (yr x+1)−(y−L x+l)、(y
rL x)の座標にある。この状態は第1図(C)に示
され図において、矢印はY減方向であることを示す。First, referring to Figure 1(a), it shows the case where the probe card moves upward on the Y axis (Y increasing direction).
The coordinates of the chip being measured in the wafer hop are (
IC, y), among the chips adjacent to the chip at the coordinates (x, y), the chips that have already been measured (they have a state of 1" because they contain measurement data) are OFF, respectively.
+11! -1), (3Flx-1), (y
-L
), (yr x+1)-(y-L x+l), (y
rL x). This state is shown in FIG. 1(C), in which the arrow indicates the Y decreasing direction.
他方、プローブカードがY軸を下方向に(Y減方向)動
く場合のウェハマツプは第1図〜)に示され、このとき
、座標(x、y)にあるチップに隣接するチップのうち
、測定済(11”)のチップはそれぞれ(711X2)
l (yr X2)l ()’ 2 + ”2 )
+ (711X)の座標にあり、未測定(“O′″
)のチップはそれぞれ(71+ Xl)+(yrxt)
會(72y xl) + (y2 * x)の座標にあ
る(第1図(a)の場合との混同を回避する目的で、x
、yの増はX1+71で、x、yの減はX2+72で示
した)、この状態は第1図(d)に示され、図において
矢印はY増方向であることを示す。On the other hand, the wafer map when the probe card moves downward on the Y axis (Y decreasing direction) is shown in Figures 1~), and at this time, among the chips adjacent to the chip at the coordinates (x, y), the Each finished (11”) chip is (711X2)
l (yr X2)l ()' 2 + "2)
+ (711X), unmeasured (“O′”
) chips are (71+Xl)+(yrxt) respectively
(72y xl) + (y2 * x) (to avoid confusion with the case in Figure 1(a), x
, y increases by X1+71, and decreases in x and y by X2+72). This state is shown in FIG. 1(d), in which the arrow indicates the Y increasing direction.
第1図(C)と(d)のパターンから、同図(e)、(
f)に示される基本的には5字型の判定パターンが得ら
れる。Yが減方向の場合には、測定中のチップに対して
、当該チップのまわりの上下逆の5字型パターンがすべ
て“1”、また左右逆の5字型パターンが60″であれ
ば、測定チップの結果はウェハマツプの正しい位置に記
入されることになる。From the patterns in Fig. 1(C) and (d), the patterns in Fig. 1(e) and (
A basically 5-shaped determination pattern shown in f) is obtained. When Y is in the decreasing direction, if the upside-down 5-shaped pattern around the chip under measurement is all "1", and the left-right upside down 5-shaped pattern is 60", The result of the measurement chip will be written in the correct position on the wafer map.
Yが増方向のとき、“1”の判定パターンは5字型パタ
ーン、“0″の判定パターンは上下左右逆の5字型パタ
ーンである。When Y is in the increasing direction, the determination pattern of "1" is a 5-character pattern, and the determination pattern of "0" is a 5-character pattern inverted vertically and horizontally.
このようにして、“1″判定パターンと“01判定パタ
ーンを点検することによって、ウェハマツプのアドレス
(座標)ずれを完全に点検することが可能となり、また
、各測定チップごとに点検を行うのであるから、ずれた
アドレスを修正することも可能になる。In this way, by checking the "1" judgment pattern and the "01 judgment pattern," it is possible to completely check the address (coordinate) deviation of the wafer happe, and each measurement chip is also inspected. It is also possible to correct misaligned addresses.
上記の方法を実施するには、第2図のプロック図を参照
すると、プローバ11からテスタ14に座標データを送
り、ウェハマツプを作ってテスタ14でそれをメモリす
る。プローブカード12でウェハ13のチップを測定し
た結果もまたテスタ14に入力される。プローブカード
がある座標(x、y)のチップに来たときは、テスタ1
4で前記した5字型パターンに従ってウェハマツプを走
査し、′1″と“0”の信号が5字型パターンに合致し
ていると測定を行い、ずれているときは必要な修正をな
す。To carry out the above method, referring to the block diagram of FIG. 2, coordinate data is sent from the prober 11 to the tester 14, a wafer map is created, and the tester 14 stores the coordinate data. The results of measuring the chips on the wafer 13 with the probe card 12 are also input to the tester 14 . When the probe card comes to the chip at certain coordinates (x, y), tester 1
The wafer map is scanned according to the 5-shaped pattern described above in 4. If the signals of '1' and ``0'' match the 5-shaped pattern, it is measured, and if they deviate, necessary corrections are made.
なお、上述の説明は、Y方向の増、減についてのもので
あったが、本発明の方法はX方向に増。Note that the above explanation was about increases and decreases in the Y direction, but the method of the present invention deals with increases and decreases in the X direction.
減の場合も全く同様に実施可能である。In the case of reduction, it can be carried out in exactly the same way.
以上説明したように本発明によれば、測定チップ座標(
アドレス)の周囲のチップのアドレスをL字型判定パタ
ーンを使用することによって点検することができるので
、座標ずれが出たときはウェハマツプを修正し測定を継
続することが可能となるので、ウェハマツプの信頼性を
向上する効果がある。As explained above, according to the present invention, the measurement chip coordinates (
By using the L-shaped determination pattern, you can check the addresses of the chips around the wafer ham (address), so if a coordinate shift occurs, you can correct the wafer ham and continue measurement. This has the effect of improving reliability.
第1図(a+と(blは測定チップの周囲のウェハマツ
プを示す図、同図(C)と(d)は(a)と中)に対応
する測定済、未測定状態を示す図、同図(e)と(fl
は(C)と(dlに基づく判定パターンの図、第2図は
本発明方法を実施するシステムのブロック図、第3図(
a)はウェハのチップを示す平面図、同図中)は(a)
のチップを正しく示すウェハマツプの図、同図(C1は
誤って作られたウェハマツプの図である。
図中、11はプロバー、12はプローブカード、13は
ウェハ、14はテスタ、をそれぞれ示す。
第1図
第1図
第2図
J
第3FIlFigure 1 (a+ and (bl are diagrams showing the wafer hamps around the measurement chip, Figures (C) and (d) are diagrams showing measured and unmeasured states corresponding to (a) and inside), Figure 1 (e) and (fl
are diagrams of determination patterns based on (C) and (dl, Figure 2 is a block diagram of a system implementing the method of the present invention, and Figure 3 is a diagram of (
(a) is a plan view showing the chips of the wafer; (in the same figure) is (a)
(C1 is a diagram of a wafer map that was made incorrectly. In the diagram, 11 is a prober, 12 is a probe card, 13 is a wafer, and 14 is a tester. 1 Figure 1 Figure 2 Figure J 3rd FIl
Claims (1)
定をなしその結果をウェハマップに書き込むにおいて、
測定チップの座標を、当該チップの周囲のL字型判定パ
ターンに測定データが入っているか否かによって点検し
、座標ずれがあるときは前記L字型判定パターンによっ
て修正することを特徴とするウェハマップの座標点検方
法。When measuring a wafer using a prober, probe card, and tester and writing the results to a wafer map,
A wafer characterized in that the coordinates of a measurement chip are checked by checking whether measurement data is included in an L-shaped determination pattern around the chip, and if there is a coordinate deviation, the coordinates are corrected using the L-shaped determination pattern. How to check map coordinates.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1215685A JPS61171147A (en) | 1985-01-25 | 1985-01-25 | How to check the coordinates of a wafer ham tup |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1215685A JPS61171147A (en) | 1985-01-25 | 1985-01-25 | How to check the coordinates of a wafer ham tup |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61171147A true JPS61171147A (en) | 1986-08-01 |
Family
ID=11797595
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1215685A Pending JPS61171147A (en) | 1985-01-25 | 1985-01-25 | How to check the coordinates of a wafer ham tup |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61171147A (en) |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6961626B1 (en) | 2004-05-28 | 2005-11-01 | Applied Materials, Inc | Dynamic offset and feedback threshold |
US6999836B2 (en) | 2002-08-01 | 2006-02-14 | Applied Materials, Inc. | Method, system, and medium for handling misrepresentative metrology data within an advanced process control system |
US7096085B2 (en) | 2004-05-28 | 2006-08-22 | Applied Materials | Process control by distinguishing a white noise component of a process variance |
US7188142B2 (en) | 2000-11-30 | 2007-03-06 | Applied Materials, Inc. | Dynamic subject information generation in message services of distributed object systems in a semiconductor assembly line facility |
US7205228B2 (en) | 2003-06-03 | 2007-04-17 | Applied Materials, Inc. | Selective metal encapsulation schemes |
US7272459B2 (en) | 2002-11-15 | 2007-09-18 | Applied Materials, Inc. | Method, system and medium for controlling manufacture process having multivariate input parameters |
US7333871B2 (en) | 2003-01-21 | 2008-02-19 | Applied Materials, Inc. | Automated design and execution of experiments with integrated model creation for semiconductor manufacturing tools |
US7354332B2 (en) | 2003-08-04 | 2008-04-08 | Applied Materials, Inc. | Technique for process-qualifying a semiconductor manufacturing tool using metrology data |
US7356377B2 (en) | 2004-01-29 | 2008-04-08 | Applied Materials, Inc. | System, method, and medium for monitoring performance of an advanced process control system |
-
1985
- 1985-01-25 JP JP1215685A patent/JPS61171147A/en active Pending
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7188142B2 (en) | 2000-11-30 | 2007-03-06 | Applied Materials, Inc. | Dynamic subject information generation in message services of distributed object systems in a semiconductor assembly line facility |
US6999836B2 (en) | 2002-08-01 | 2006-02-14 | Applied Materials, Inc. | Method, system, and medium for handling misrepresentative metrology data within an advanced process control system |
US7272459B2 (en) | 2002-11-15 | 2007-09-18 | Applied Materials, Inc. | Method, system and medium for controlling manufacture process having multivariate input parameters |
US7333871B2 (en) | 2003-01-21 | 2008-02-19 | Applied Materials, Inc. | Automated design and execution of experiments with integrated model creation for semiconductor manufacturing tools |
US7205228B2 (en) | 2003-06-03 | 2007-04-17 | Applied Materials, Inc. | Selective metal encapsulation schemes |
US7354332B2 (en) | 2003-08-04 | 2008-04-08 | Applied Materials, Inc. | Technique for process-qualifying a semiconductor manufacturing tool using metrology data |
US7356377B2 (en) | 2004-01-29 | 2008-04-08 | Applied Materials, Inc. | System, method, and medium for monitoring performance of an advanced process control system |
US6961626B1 (en) | 2004-05-28 | 2005-11-01 | Applied Materials, Inc | Dynamic offset and feedback threshold |
US7096085B2 (en) | 2004-05-28 | 2006-08-22 | Applied Materials | Process control by distinguishing a white noise component of a process variance |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN111754479B (en) | Inspection method for precise matching of layout and graph | |
JPS61171147A (en) | How to check the coordinates of a wafer ham tup | |
CN117808754A (en) | Target object detection method, target object detection system, electronic equipment and storage medium | |
JP2007335785A (en) | Apparatus, method and program for testing semiconductor wafer | |
Kim et al. | Three-dimensional inspection of ball grid array using laser vision system | |
CN113035734B (en) | Silicon wafer offset determination method and silicon wafer handover precision detection method | |
US7855088B2 (en) | Method for manufacturing integrated circuits by guardbanding die regions | |
CN101493494B (en) | Wafer testing method and system | |
US6785413B1 (en) | Rapid defect analysis by placement of tester fail data | |
US12062166B2 (en) | Method and system for diagnosing a semiconductor wafer | |
JP6053579B2 (en) | Manufacturing method of semiconductor device | |
JP4857628B2 (en) | Magnetic sensor module inspection method | |
JPH065690B2 (en) | Semiconductor wafer probe method | |
JP2008261692A (en) | Substrate inspection system and substrate inspection method | |
JPH0645428A (en) | Manufacture of semiconductor device | |
KR100687870B1 (en) | Wafer inspection method | |
JPH07312382A (en) | Probe device | |
JPH0254544A (en) | Brobing | |
US20250086829A1 (en) | Method for defining valid die positions on inspection wafer map | |
JPH0370903B2 (en) | ||
JPS6184029A (en) | Semiconductor inspecting device | |
KR19990085547A (en) | Repeat fail chip detection system and method | |
JPS59147206A (en) | Object shape inspection device | |
JPH02253110A (en) | Shape checking device for linear object | |
JPH04147637A (en) | Method of testing semiconductor integrated circuit by use of test program |