JP2008261692A - Substrate inspection system and substrate inspection method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform accurately marking determination of a defective die, while reducing an operator's load. <P>SOLUTION: This substrate inspection system has a macro inspection part 20 for inspecting the surface of a wafer 1 on which a plurality of dies are arranged, approximately by visual observation, and inspecting a surface defective spot; a micro inspection part 40 for inspecting in detail the surface of the wafer 1 by the first imaging device 42 based on a surface inspection result by the macro inspection part 20, and inspecting the surface defective spot; a storage device in a system PC 50 for storing the surface inspection result by the macro inspection part 20 and a surface inspection result by the micro inspection part 40 on a prescribed die layout; and a data analyzer 63 for outputting marking data and/or inkless data to the defective spot by analyzing and piling together a storage result by the storage device, a defect inspection result by another defect inspection device 62 to the wafer 1, and a measurement result of the detective spot of an electric characteristic to the wafer 1. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention provides a visual inspection of a front surface or a back surface of a substrate to be inspected (for example, a semiconductor wafer, hereinafter simply referred to as a “wafer”) on which a plurality of dies on which electronic devices such as semiconductor devices are formed are arranged. The present invention relates to a substrate inspection system and a substrate inspection method for performing electrical characteristic inspection.

  For example, in a method of manufacturing a semiconductor device such as an insulated gate bipolar transistor (hereinafter referred to as “IGBT”) or a diode, a circuit pattern is formed for each of a large number of dies on the surface side of the wafer. After the formation, the appearance of the surface of the wafer is inspected, and marking for attaching a defective mark with ink or the like is performed on a die having a defective portion. Further, an electrical property inspection is performed, and marking is similarly performed on a die having a defective portion. Thereafter, a large number of dies each having a semiconductor device formed on the wafer are cut and separated as chips, the defective chips are discarded, and only non-defective chips are used (for example, shipping in the case of a semiconductor manufacturer).

  Conventionally, as a technique related to appearance inspection, for example, there are those described in the following documents.

JP 2003-14654 A JP 2006-128504 A JP 2006-310551 A JP-A-10-170605

  Patent Document 1 describes a technique for inspecting (monitoring) the front and back surfaces of a substrate and marking a defective chip based on the monitoring result (see paragraphs 0006, 0020, etc.). Patent Documents 2 and 3 describe that the monitored front and back images are superimposed and displayed on the monitor screen (refer to paragraphs 0023 and 0044 in Patent Document 2 and paragraph 0049 in Patent Document 3). , 0056, etc.). Patent Document 4 describes that a visual inspection and an electrical test of a substrate are performed, and a defective portion is analyzed by superimposing a result of the visual inspection and a result of the electrical test (paragraphs 0087 to 0092, etc.). See).

  However, in the conventional substrate inspection system or substrate inspection method, a substrate external inspection is automatically performed using a microprocessor (hereinafter referred to as “MPU”) for executing a defect inspection program, and then a test program is executed. However, these inspections not only require complicated work and processing, but sometimes fail to find a defective part. Therefore, conventionally, before automatically inspecting the appearance of the substrate, when the operator visually inspects and finds a defective part, the position of the defective die in the wafer is handwritten, and the marking information is Feedback to the process and marking as defective.

  In this case, when the die size is reduced, there is a problem that the determination error of the position of the defective target chip is likely to occur and the load on the operator is increased.

  In the substrate inspection system of the present invention, a macro inspection unit that visually inspects a surface of a substrate to be inspected on which a plurality of dies on which electronic devices are formed are arranged to inspect a surface defect portion, and a surface inspection result of the macro inspection unit Based on the above, a micro inspection unit that inspects the surface of the substrate to be inspected by the first imaging device to inspect a surface defect portion, a surface inspection result of the macro inspection unit, and a surface inspection result of the micro inspection unit are predetermined. A storage device for storing on the die layout, a storage result of the storage device, a defect inspection result by another defect inspection device for the substrate to be inspected, and a measurement result of a defective portion of electrical characteristics for the substrate to be inspected. And a data analysis device that outputs the marking data and / or inkless data for the defective portion by analyzing and overlaying.

  In the substrate inspection method of the present invention, a macro inspection process for inspecting the surface of a substrate to be inspected on which a plurality of dies having electronic devices formed thereon are visually inspected to detect a surface defect portion; and A micro-inspection process for performing alignment with an inspection substrate, and inspecting a surface defect portion by inspecting a surface of the inspected substrate with a first imaging device based on a surface inspection result of the macro-inspection process; and the macro-inspection process A storage process for storing the surface inspection result and the surface inspection result of the micro inspection process on a predetermined die layout, a storage result of the storage process, another defect inspection result for the substrate to be inspected, and the inspection target This is a data output that analyzes and superimposes the measurement result of the defective portion of the electrical characteristics on the substrate and outputs the marking data and / or inkless data for the defective portion. And having a data analysis process.

  According to the substrate inspection system and the substrate inspection method of the present invention, the macro inspection result by visual inspection, the micro inspection result by visual inspection, and other defect inspection results are simultaneously managed as a database on the system based on the macro inspection result. In addition, since the image data of the defective portion can be acquired at the same time during the macro inspection, it is possible to accurately determine the marking of the defective die while suppressing the load on the operator.

  In the substrate inspection system, a macro inspection unit that inspects the surface of a substrate to be inspected (for example, a wafer) on which a plurality of dies on which electronic devices are formed is visually inspected to inspect a surface defect portion, and the macro inspection A micro-inspection unit that inspects the surface of the substrate to be inspected in detail by a first imaging device based on the surface inspection result of the part and inspects a defective surface portion, a surface inspection result of the macro-inspection unit, and the micro-inspection unit A storage device in a control unit for storing the surface inspection result on a predetermined die layout, a storage result of the storage device, a defect inspection result by another defect inspection device for the inspected substrate, and for the inspected substrate A data analysis device that analyzes and superimposes measurement results of defective portions of electrical characteristics and outputs marking data and / or inkless data for the defective portions; It is.

(Board Inspection System of Example 1)
FIG. 1 is a schematic configuration diagram of a substrate inspection system showing Embodiment 1 of the present invention. FIG. 2 is a schematic configuration diagram showing a control unit (for example, a system personal computer (hereinafter referred to as “system PC”) in FIG. 1.

  The substrate inspection system shown in FIG. 1 has a wafer carrier 10 that houses a plurality of substrates (for example, wafers) 1 to be inspected. The wafer 1 has an orientation flat portion for alignment (hereinafter referred to as “orientation flat portion”) 1a in which a part of the outer periphery of a thin disk is cut, and a substantially square die 2 on which a circuit pattern is formed is on a plane. Are arranged in the horizontal X-axis direction and the vertical Y-axis direction. Furthermore, this substrate inspection system is for aligning the macro inspection unit 20 for visual inspection of the wafer 1 taken out (loaded) from the wafer carrier 10 and the orientation flat 1a of the wafer 1 in a certain direction. A wafer positioning unit 30 for orientation flat alignment, and a micro inspection unit 40 including a micro stage 41 and a first imaging device 42 for visually inspecting the wafer 1 subjected to orientation flat alignment. The wafer carrier 10, the macro inspection unit 20, the wafer positioning unit 30, and the micro inspection unit 40 are controlled by the system PC 50.

  The macro inspection unit 20 irradiates the wafer 1 placed on the rotatable macro stage 21 from the upper oblique direction by the epi-illuminator 22 and visually observes the wafer reflection surface with the operator's eyes 23. A rough appearance portion (for example, a defect in a circuit pattern, a flaw, a pattern defect in metal film formation, a defect such as attached foreign matter) 3 is inspected, and this macro inspection result is stored in the system PC 50. . The wafer positioning unit 30 performs alignment so that the pattern of the microstage 41 is close to the X-axis direction and the Y-axis direction before the wafer 1 is loaded and set to the microtage 41.

  The micro inspection unit 40 performs an objective lens 42a and a charge coupled device camera (hereinafter referred to as “CCD”) on the wafer 1 set on the macro stage 41 movable in the X axis direction and the Y axis direction based on the macro inspection result. The camera is called a “camera”.) The first imaging device 42 constituted by 42b and the like performs a detailed appearance inspection on the wafer 1, acquires an image of the defective portion 3, and detects the position of the defective portion 3 to detect a defect. The coordinate conversion of the die data is performed, and the image data of the defective die and the coordinate value of the converted defective die data are stored in the system PC 50.

  For example, as shown in FIG. 2, the system PC 50 has an internal bus 51 connected to the wear carrier 10, the macro inspection unit 20, the wafer positioning unit 30, and the micro inspection unit 40 via an input / output interface. is doing. In the internal bus 51, for example, a control unit (for example, a central processing unit, hereinafter referred to as “CPU”) 52 configured by a control unit, a calculation unit, an address management unit, and the like can be read and written at any time. Auxiliary memory device such as a hard disk for storing a memory map die layout data and the like, a memory (hereinafter referred to as “RAM”) 53, a read only memory (hereinafter referred to as “ROM”) 54 for storing a defect analysis program and the like 55, an input unit 56 such as a keyboard, an output unit 57 such as a display device and an output port for displaying defective die data of the visual inspection unit 20 and the micro inspection unit 40, and a network interface 58 and the like. It is connected to the.

  To the network interface 58, for example, a defect analysis device 60 described in Patent Document 2 for automatically inspecting the appearance of the wafer 1 and automatically measuring electrical characteristics is connected. A defect analysis apparatus 60 shown in FIG. 1 is an apparatus for inspecting and analyzing wafer defects in a plurality of semiconductor manufacturing processes. For example, an image capturing apparatus 61, a defect inspection apparatus 62, and a data analysis apparatus 63 are used. The electrical characteristic measuring device 64 is connected to the data analyzing device 63, and the marking data S63b is output to the marking device 70 from the output terminal of the data analyzing device 63, or the inkless data S63c is output. It has a function to do.

  For example, in response to receiving the defect distribution information S63a given from the data analysis device 63, the image capture device 61 captures the observation image of the wafer surface with an electron microscope or the like, and the digital signal substrate observation information S61 or the like is used as the data analysis device. 60. The defect inspection apparatus 62 is an apparatus for inspecting defects on the wafer 1 to obtain defect distribution information S62 including defect coordinates, defect distribution, and defect size in a two-dimensional coordinate system composed of the X axis and the Y axis, and supplying the defect distribution information S62 to the data analysis apparatus 63. For example, it is configured by an optical image comparison inspection device, a laser scattering inspection device, an electron microscope image inspection device, or the like.

  The data analysis device 63 includes, for example, substrate observation information S61 given from the image capturing device 61, defect distribution information S62 given from the defect inspection device 62, and a wafer measured by an electrical characteristic measurement device 64 having a tester and a probe card. Marking for generating defect information by combining the electrical characteristic measurement results of 1 and determining the defect of the die 2 in the wafer 1 based on the defect information and marking the die 2 determined to be defective with ink It has a function of outputting the data S63b to the marking device 70, or outputting the inkless data S63c, and is configured by an MPU or the like.

(Substrate inspection method of Example 1)
FIG. 3 is a process diagram showing a substrate inspection method using the substrate inspection system of FIG. 4A to 4C are diagrams showing processing of the wafer positioning unit 30 in FIG. FIGS. 5A to 5C are diagrams showing a die layout creation method in the system PC 50 of FIG. Further, FIGS. 6A to 6D are explanatory diagrams of the processing steps of FIG.

Hereinafter, the substrate inspection method according to the first embodiment will be described mainly with reference to the process diagram of FIG.
First, with respect to the wafer 1 taken out from the wafer carrier 10, the orientation flat portion 1 a is positioned by the wafer positioning portion 30, and the wafer 1 is loaded on the microstage 41. Further, the rotation angle component Θ of the wafer 1 with respect to the microstage 41 is corrected (step P1 in FIG. 3).

  That is, in the processing of the wafer positioning unit 30, as shown in FIGS. 4A to 4C, the die layout position of the wafer 1 on the micro stage 41 composed of the X stage coordinates and the Y stage coordinates, and the system PC 50 In order to match the die layout on the wafer 1 drawn (stored) on the auxiliary storage device 55, the first alignment position A1 and the second alignment position A2 are aligned at the die origin 2a on the same line in the wafer 1. The wafer rotation component Θ of the orientation flat portion 1a with respect to the microstage 41 is corrected.

  After the correction, the die layout for the wafer 1 is created based on the die layout of the wafer 1 on the actual microstage 41 by using the die layout for the wafer 1 and the offset from the wafer center 1b to the die origin 2a. (Step P2).

  That is, in the die layout creation, for example, as shown in FIG. 5A, when the wafer center 1b is set to the origin (0, 0), the corner (die) of the die 2 from the origin (0, 0) is used as a reference. The distances x and y to the origin 2a) are input to the system PC 50, or calculated from the X and Y stage coordinates and input to the system PC 50. Next, as shown in FIG. 5B, the sizes on the X and Y axes of the die 2 are input to the system PC 50, and a die layout grid is drawn based on the die origin 2a (stored in the auxiliary storage device 55). To do). 5 (a) and 5 (b) specify the layout position of the die 2 with respect to the wafer 1 and draw a lattice. Thereafter, as shown in FIG. 5 (c), chips outside the effective diameter with respect to the wafer outer diameter are obtained. The chip in the shaded area is erased to match the die layout pattern transferred onto the actual wafer.

  As described above, the coordinates in the wafer 1 on the macro stage 21 and the position on the die layout in the wafer map on the auxiliary storage device 55 of the system PC 50 coincide with each other, and the auxiliary storage device 55 of the system PC 50 is used as a recipe. Register (step P3).

Next, the product (wafer 1) is inspected as follows (step P10).
First, a recipe registered in the auxiliary storage device 55 of the target system PC 50 is read (step P11).

  After the surface of the wafer 1 is visually inspected by the macro inspection unit 20, the wafer 10 is loaded onto the micro stage 41 by the wafer positioning unit 30, and the surface of the wafer 1 is inspected by the objective lens 42a and the CCD camera 42b of the micro inspection unit 40. Then, the position of the die 2 where the defective portion 3 is found by the macro inspection unit 20 and the micro inspection unit 40 is registered on the die layout in the auxiliary storage device 55 in the system PC 50 (step P12). At this time, in addition to the position coordinates of the defective portion 3 observed by the macro inspection unit 20 and the micro inspection unit 40, the image data of the defective portion 3 observed by the objective lens 42a and the CCD camera 42b is also simultaneously stored in the auxiliary storage device 55. Register (step P13).

  The defective die data registered in the auxiliary storage device 55 is transferred to the defect analysis device 60 (step 1 in FIG. 6A). In the defect analysis device 60, an appearance inspection is automatically performed by the image capturing device 61 and the defect inspection device 62, and an electrical property inspection is automatically performed by using an electrical property measurement device 64 by probing. Then, the registered defective die data (step 1 in FIG. 6A) by the data analysis device 63, the die position determined as abnormal by the automatic appearance inspection result (step 2 in FIG. 6B), The marking position S63b or the ink cell data S63c is output from the data analyzer 63 by superimposing the die position (the electrical characteristics step in FIG. 6C) determined to be abnormal based on the automatic electrical characteristics inspection result. When the marking data S63b is output from the data analysis device 63, the marking device 70 performs marking on the die 3 at the defective portion using ink. Ink marking data S63c is output from the data analysis device 63 when marking using ink cannot be performed due to the miniaturization of the die 3 (step P14).

  Thereafter, a large number of dies 2 each having a semiconductor device formed thereon are cut and separated as chips on the wafer 1. For example, in the case of a semiconductor manufacturer, defective chips are discarded and only non-defective chips are released to the market. To do.

(Effect of Example 1)
According to the substrate inspection system of the first embodiment, the operator has a function of linking a defective die position on the wafer 1 found by visual inspection by the operator to the position of the die 2 of the wafer die layout on the system PC 50. The configuration is such that the defective chip position is easily output as defective die information. Therefore, in the original visual appearance inspection, the die coordinate on the wafer 1 at the time of observing the defective part, the die coordinate on the system PC 50 and the coordinate of the defective part are matched and converted into a database, and the image of the defective part is simultaneously captured. Thus, it is possible to mark the abnormalities that cannot be judged as abnormal in terms of electrical characteristics by superimposing defective dies in a plurality of steps.

  That is, as shown in FIG. 6, the result of the inspection process 1 by the macro inspection unit 20 and the micro inspection unit 40 (FIG. 6A) and the result of the automatic appearance inspection process 2 (FIG. 6B). In some cases, the registered defective portion 3 of the die 2 is not defective in the electrical property inspection result (FIG. 6C), and by marking the electrical property inspection result as described above, Normally, it is possible to prevent a defective die that is not determined to be defective only by electrical characteristic inspection from flowing out to the market.

  FIG. 7 is a schematic explanatory diagram of a substrate inspection method using the substrate inspection system according to the second embodiment of the present invention. Elements common to those in FIG. Has been.

  Visual inspection results by the macro inspection unit 20 and the micro inspection unit 40 of the first embodiment shown in FIG. 1 and, for example, two automatic visual inspection steps 80-1 using the image capturing device 61 and the defect inspection device 62 as shown in FIG. , 80-2 and the measurement result of the electrical characteristic measuring device 64 are input, and the data analysis device 63 in the defect analysis device 60 as shown in FIG. (Merged), the marking data S63b or the inkless data S63c may be output.

  As described above, the visual inspection results by the macro inspection unit 20 and the micro inspection unit 40 of the first embodiment, the results of the two automatic visual inspection steps 80-1 and 80-2, and the measurement result of the electrical characteristic measuring device 64 are obtained. By merging, not only the marking on the defective die in which the abnormality is detected in the results of all these inspections (measurements), but also the visual inspection results, the inspection results by the automatic appearance inspection processes 80-1 and 80-2, and the biographical characteristics It is possible to mark a defective die in which an abnormality is detected in at least one of the measurement results obtained by the measuring device 64, thereby improving the screening accuracy.

  FIG. 8 is a schematic configuration diagram of a substrate inspection system showing Embodiment 3 of the present invention, and FIG. 9 is a schematic explanatory diagram of a substrate inspection method using the substrate inspection system of FIG. 1 and FIG. 7 showing the second embodiment are denoted by common reference numerals.

  For example, in a method of manufacturing a semiconductor device such as an IGBT or a diode, a circuit pattern is formed for each of a large number of dies on the front surface side of the wafer 1, and an electrode pattern or the like is formed for each of a large number of dies on the back surface side. Even when there is a defective portion in the electrode pattern or the like, it may cause a defect of the die 2. Therefore, as shown in FIG. 8, with respect to the first imaging device 42 comprising the wafer surface observation objective lens 42a and the CCD camera 42b in the micro inspection unit 40 of FIG. A second imaging device 43 comprising an objective lens 43a for observing the wafer back surface and a CCD camera 43b is provided. Then, as shown in FIG. 9, the wafer back surface inspection result by the imaging device 43 for wafer back surface observation is input (reflected) into the die position information on the wafer surface, and the die information corresponding to the wafer back surface defect location If these are superimposed, the screening accuracy can be further improved.

  Similarly, in the two automatic appearance inspection processes 80-1 and 80-2, if the wafer back surface information is reflected in the wafer front surface information, the screening accuracy is further improved.

(Modification)
The present invention is not limited to the above embodiment, for example, the configuration of the substrate inspection system is changed to a configuration other than that illustrated, or the processing content of the substrate inspection method is changed to a processing procedure other than that illustrated in accordance therewith, etc. Numerous various usage forms and modifications are possible.

It is a schematic block diagram of the board | substrate inspection system which shows Example 1 of this invention. It is a schematic block diagram which shows system PC in FIG. It is a process-process figure which shows the board | substrate inspection method using the board | substrate inspection system of FIG. It is a figure which shows the process of the wafer positioning part of FIG. It is a figure which shows the die layout production method in the system PC of FIG. It is explanatory drawing of the process process of FIG. It is explanatory drawing of the outline of the board | substrate inspection method using the board | substrate inspection system which shows Example 2 of this invention. It is a schematic block diagram of the board | substrate inspection system which shows Example 3 of this invention. It is explanatory drawing of the outline of the board | substrate inspection method using the board | substrate inspection system of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Wafer 10 Wafer carrier 20 Macro inspection part 21 Macro stage 22 Epi-illuminator 30 Wafer positioning part 40 Micro inspection part 41 Micro stage 42,43 Imaging device 50 System PC
60 Defect Analysis Device 61 Image Capture Device 62 Defect Inspection Device 63 Data Analysis Device 64 Electrical Characteristic Measurement Device 70 Marking Device

Claims (8)

A macro inspection unit that inspects the surface of a substrate to be inspected on which a plurality of dies on which electronic devices are formed are arranged, and inspects a surface defect portion;
Based on the surface inspection result of the macro inspection unit, a micro inspection unit that inspects the surface of the substrate to be inspected by a first imaging device and inspects a surface defect portion;
A storage device for storing a surface inspection result of the macro inspection unit and a surface inspection result of the micro inspection unit on a predetermined die layout;
Marking the defective portion by analyzing and superimposing the storage result of the storage device, the defect inspection result of another defect inspection device for the substrate to be inspected, and the measurement result of the defective portion of the electrical characteristics for the substrate to be inspected A data analysis device for outputting data and / or inkless data;
A board inspection system comprising: The substrate inspection system according to claim 1, further comprising:
The macro inspection unit has a function of inspecting a back surface of the substrate to be inspected by visual inspection and inspecting a back surface defective portion,
The micro inspection unit has a second imaging device arranged on the same optical axis as the first imaging device, and the back surface of the substrate to be inspected is based on the back surface inspection result of the macro inspection unit. It has a function of inspecting the back surface defective portion by inspecting with the second imaging device,
The storage device has a function of storing the front and back inspection results of the macro inspection unit and the front and back inspection results of the micro inspection unit on the predetermined die layout,
The data analysis device analyzes a storage result of the storage device, a defect inspection result by the other defect inspection device for the substrate to be inspected, and a measurement result of a defective portion of the electrical characteristic for the substrate to be inspected. A substrate inspection system having a function of superimposing and outputting marking data and / or inkless data for the defective portion. The substrate inspection system according to claim 1 or 2, further comprising:
A substrate inspection system comprising a marking device for marking a die of the defective portion on the substrate to be inspected based on the marking data.   The substrate inspection system according to claim 1, wherein the substrate to be inspected is a semiconductor wafer. Macro inspection processing that inspects the surface of a substrate to be inspected on which a plurality of dies on which electronic devices are formed are arranged, and inspects a surface defect portion;
A micro that aligns the substrate to be inspected after the macro inspection processing, and inspects the surface of the substrate to be inspected by a first imaging device based on a surface inspection result of the macro inspection processing, to inspect a surface defect portion. Inspection process,
A storage process for storing the surface inspection result of the macro inspection process and the surface inspection result of the micro inspection process on a predetermined die layout;
The storage result of the storage process, the other defect inspection result for the substrate to be inspected, and the measurement result of the defective portion of the electrical characteristics for the substrate to be inspected are analyzed and superimposed to provide marking data for the defective portion and / or Data analysis processing to output inkless data;
A substrate inspection method characterized by comprising: The substrate inspection method according to claim 5 further includes:
The macro inspection process performs a process of inspecting a back surface defective portion with respect to the back surface of the substrate to be inspected,
The micro inspection process uses a second imaging device arranged on the same optical axis as the first imaging device, and based on the back surface inspection result of the macro inspection process, the back surface of the substrate to be inspected. To inspect the backside defective part,
The storage process stores the front / back inspection result of the macro inspection process and the front / back inspection result of the micro inspection process on the predetermined die layout,
In the data analysis process, the storage result of the storage process, the other defect inspection result with respect to the substrate to be inspected, and the measurement result of the defective portion of the electrical characteristic with respect to the substrate to be inspected are analyzed and superimposed, A substrate inspection method for outputting marking data and / or inkless data for a defective portion. The substrate inspection method according to claim 5 or 6, further comprising:
A substrate inspection method, wherein marking is performed on a die of the defective portion of the substrate to be inspected based on the marking data.   The substrate inspection method according to claim 5, wherein the substrate to be inspected is a semiconductor wafer.

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