JPS61168265A - Semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention, which has an industrial application field, relates to a semiconductor device capable of improving manufacturing yield.

Conventional technology Conventionally, for example, MO8L such as static memory
In SI, contact is used when electrically connecting the Si substrate, the source/drain which is the impurity diffusion layer of the opposite conductivity type, and the polycrystalline Si part which is the first electrode wiring in the field S102 film. In order to reduce the area of the part, a contact window is often formed spanning the source/drain and the polycrystalline Si part, and this contact window is covered with an Ap wiring.

At this time, if the polycrystalline SL part 1 extends to the outside of the field S10.2 film 2 as shown in FIG. 6, the Ap wiring 3 formed above and the polycrystalline Si part 1 may react. In many cases, the formed AN-8 film alloy passes through the thin 5IO2 film 4 under the polycrystalline Si portion and reaches the Si substrate 6, causing a short circuit between the AR wiring 3 and the S1 substrate 5. However, it is desirable that the polycrystalline St portion 1 within the contact window be located on the field Sio2 film 2 as shown in FIG.

Problems to be Solved by the Invention However, in this case, when etching the polycrystalline St part 1 film 7 located on the source/drain 6 and the field S 102 film 2, the field 5102 film under the insulating film 7 is etched by one notch. 2 is also etched. At this time, if the etched field 5102 film 2 is shallow or the source/drain 6 (junction of the impurity diffusion layer) is deep, only the ends of the source/drain 6 are exposed within the contact window. However, in a miniaturized LSI, it is necessary to make the source/drain 6 shallow, so when the field S 102 film 2 is etched, the Si substrate 6
8 is exposed as shown in FIG. In this case, when the contact window is covered with the AR wiring 3, the Si substrate 1, the source/drain 6, and the polycrystalline Si portion 1 are short-circuited and broken, resulting in a defective LSI. This problem is caused by the insulating film 7
This becomes a particularly serious problem when etching is carried out by an isotropic etching method, such as a wet etching method using a diluted HF solution.

The present invention has been made in view of this point, and an object of the present invention is to provide a semiconductor device having a structure in which the above-mentioned problems do not occur.

The present invention's only means to solve the problem! In order to solve the above-mentioned conventional problems, the 4'-conductor device is provided with a side wall of a predetermined thickness on the side surface of the electrode wiring formed in the field area, so that one end of the electrode wiring extends from the edge of the field area. An interlayer insulating film located within the thickness of the side wall and formed on the source/drain and the electrode wiring is selectively etched to form a contact window spanning the source/drain and the electrode wiring. It is something.

Function: As described in "'14 conductor device of the present invention," when opening a contact window spanning an electrode wiring and a source/drain, the end of the field area within the contact window is attached to the side surface of the electrode wiring. Because it is covered with formed side walls,
Even if the interlayer insulating film on the source/drain and electrode wires is etched, the field insulating film is etched and S
The i-board is never exposed.

Example An embodiment of the present invention will be described with reference to FIGS. 1 to 5.

Figure 1 shows a source layer consisting of a shallow impurity diffusion layer of the opposite conductivity type.
FIG. 2 is a plan view and a cross-sectional view of a contact portion between a drain and an electrode wiring made of polycrystalline St, in which 10 is a field SiO2 film which is a field insulating film, and 11 is polycrystalline Si which is an electrode wiring.

12 is a source/drain, 13 is an insulating film, for example, CV
A side wall made of D S 102 film, 14 a contact window,
15 is a P-type Si substrate, 16 is an insulating film, 17 is A [wiring,
'81d'f-) It is a SiO2 film. 0MO8
The memory cells in the static RAM are two sets of C
A flip-flop circuit is constructed by connecting the gate electrode of each MOS inverter to the source/drain of the other inverter, and a contact window 14 is formed at the connection between the gate electrode and the source/drain as shown in FIG. Field S10 connected to source/drain and gate electrode
2 @ By being formed across the polycrystalline layer 5i11 above, high density can be achieved. The semiconductor device of the embodiment in which this contact portion has the structure of the present invention is as follows:
This will be explained in detail with reference to process diagrams shown in FIGS. 3 to 5. P
By selectively oxidizing the Si substrate 16, the thickness is reduced to 0.7μ.
Form a field SiO2 film 1o with a thickness of 0.01 m.
After forming the gate S102 film 18 of 51 m2, a polycrystalline Si film is formed, and the resistance is lowered by thermal diffusion of P, which is an n-type impurity, and then the gate S102 film 18 and the field S102 film 10 are formed. Second, each gate electrode and electrode wiring 11
(Figure 3).

At this time, the edge of the polycrystalline 5i11, which is the electrode wiring of the field S102 film 10'2, is separated by 0.2 μm from the edge of the field S102 film 1°.
It is located at 04:. After implanting As ions, which are n-type impurities, to form the source/drain 12 with a depth of 0.15 μm, the source/drain 12 is formed with a thickness of 0.15 μm using a vapor phase chemical vapor deposition (CVD) method.
A 4 μm 8102 film (CV D S 102 film) was formed using reactive ion etching (RIE) with strong anisotropy.
By etching the entire surface using a method, the flat portion of the CV D S 102 film is removed, and a side wall 13 having a thickness of 0.3 μm is formed only on the side surface of the polycrystal 5i11 (FIG. 4).

Next, after forming an S No 2 film (PSG film) 16 with a thickness of 0.6 μm containing a high concentration of P as an inter-station insulating film by CVD method, this PSGSiO1 gate SiO2 film 18 is selectively separated by RIE method. A contact window spanning the source/drain 12 and the polycrystal 5i11 is opened by etching to form an A111 wiring 17 (FIG. 5).

When etching the PSGSiO1 gate S102 film 18 using the RIE method, we usually take into account variations in the thickness of the PSG film 16, variations in etching rate depending on location, reproducibility of etching rate, etc. Insulating film (
In this example, PSG film 0.4 μm and gate SiO2 film ○
, o15 μm) for a certain period of time longer than the time required to etch (over-etching)
do. Alternatively, by shortening the etching time by the RIE method, a thin vPSG, Ill, for example, a 0.0811 m thick PSCi film, etc.) Si○2 film 18 total 18
In some cases, the remaining PSG film and S102 film are etched using a wet etching method with a high selectivity to the Si substrate, and in this case too, the etching time is lengthened, that is, over etching is performed to remove the PSGS in the contact window.
Attempt to completely remove the iO1 GooF 5102 film 18.

In this embodiment, the field 5i02 film 19 from the end of the polycrystalline 5i11 to the source and drain 12 is
Side wall 1 made of CVDSi○2 film formed on the side surface of i11
3, even if over-etching is performed as described in -1-, only the side wall 13 is etched and the field S
102 film 19 is not etched and the source
The Si substrate 15 under the drain 12 is not exposed within the contact window.

This means that the edge of the polycrystalline 5116 is the field S 102 film 1
This result was obtained for a cell located at a distance less than the thickness of the side wall 13 from the edge of the cell.

In the above description, the sidewalls 13 are formed after forming the source/drain 12, but the invention is not limited to this, and the sidewall 13 may be formed before the source/drain 12 is formed. As in the case of an LDD consisting of regions with different impurity concentrations, the sidewalls 13 may be formed after the source/drain with the first impurity concentration is formed, and then the source/drain with the second impurity concentration may be formed. .

Furthermore, the material of the side wall 13 is CVD510 in this embodiment.
Although the two films are not limited to this and other insulating films such as a Si3N4 film may be used, it is preferable that the remoenoting rate is lower than that of the interstation insulating film 16.

Effects of the Invention According to the semiconductor device of the present invention, when forming a contact window spanning the source/drain and the electrode wiring on the field insulating film, the field insulating film at the edge of the field region is not etched, so that the contact window is not etched. The three substrates under the source/drain are not exposed within the window, and there is no short circuit between the source/drain or electrode wiring and the Si substrate. Therefore, it is possible to improve the manufacturing yield of high-density LSIs with shallow source/drain junctions and thin SiO2 films.

[Brief explanation of the drawing]

FIG. 1 is a plan view of a contact portion of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a cross-sectional view of the same, FIGS. 3 to 6 are cross-sectional views explaining the manufacturing process of the device, and FIG. , FIG. 7 is a sectional view of a contact portion of a conventional semiconductor device. 10...Field S 102 membrane, 11...
... Electrode arrangement L12 ... Source/drain, 1
3. Mountain... side wall, 14... contact window. Name of agent: Patent attorney Toshio Nakao and 1 other person
8. I’m sorry”

Claims (1)

[Claims] The electrode wiring includes an electrode wiring formed in the field region, a side wall having a predetermined thickness formed on the side surface of the electrode wiring, and an interlayer insulating film formed on the electrode wiring, and one end of the electrode wiring is located in the field region. a contact located at a distance within the thickness of the side wall from the end of the interlayer insulating film, including one end of the electrode wiring, and formed so as to span the electrode wiring and the source/drain. A semiconductor device equipped with a window.