JPS5835970A - Manufacturing method of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the area of an active region by conducting the introduction of an inpurity and the draw-out of an electrode from the side surface of the active region demarcated by a field insulating film. CONSTITUTION:When the region demarcated by the field oxide film of an N type Si epitaxial layer 13 is selectively etched by Si3N4 18 and the mask of a photo-resist 19, a groove 20 is formed to the film and a B ion implanting layer 21a is shaped, an Si exposed section is deeply molded and the section under the film 18 is shallowly formed. Poly Si 22' not added is stacked through a CVD method, B is implanted in high concentration, and a P<+> layer 21b is shaped. A base electrode 22 is formed through lift-off, and conductivity is given through annealing while a P<+> base connecting layer 23 is shaped. The surface is coated with poly Si 24 not added, an Si3N4 mask 25 is molded selectively, B<+> ions are implanted, and a P type external base 27 is formed through annealing. The layer 24 is selectively oxidized 28 up to its bottom, the layers 25, 24, 18 are removed through etching, B and successively As ions are implanted from a window 26, a P type internal base 29 and an N<+> emitter 30 are shaped through annealing, and an Al electrode 31 is formed. According to this constitution, the active region demarcated by the insulating film is reduced, and the density of elements can be increased.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a bipolar semiconductor device, and more particularly to a method for forming functional regions and electrodes in a bipolar semiconductor device having a structure in which side surfaces of an active region are defined by field insulating films. .

Semiconductor integrated circuit (I)
Section 4 is important in improving the operating speed and degree of integration of C).

Bipolar semiconductor device! In 11iK, an iso-planar structure in which an active region is defined by a field insulating film is often used as a structure for miniaturization of elements. In this isoplanar structure, the element isolation region, collector/contact region, and base region are formed in a self-aligned state using a single photo-i-sphere, so the positions when forming these regions are There is no need to check the alignment margin, and therefore it is possible to miniaturize the element.

However, in the conventional isoplanar structure, as shown in FIG. 1, the base electrode window 1 and the emitter diffusion window/electrode window 2 are arranged side by side on the base region 3 through another alignment process. , the length L of the base region, which is the active region, the alignment margin α of the electrode window, the width t of the base electrode window 10, and the width t of the Eitsuta electrode window! There is a problem that the electrode window spacing t cannot be reduced to less than the sum (L=α+1B+L!+Lm) of the electrode window interval t, which takes into account the positioning margin of the electrode wiring formed on these electrode windows. In order to eliminate the above-mentioned problems, a method for manufacturing a bipolar semiconductor device is provided in which the area of the active region is reduced by introducing impurities and leading out electrodes from the @ plane of the active region defined by the field insulating film.

That is, the present invention provides a method for manufacturing a bipolar semiconductor device in which the side surfaces of an active region are defined by a field insulating film, in which a groove is formed in the field insulating film to expose an edge side surface of the active region; The method is characterized by the step of introducing an impurity into the active region from the groove, and then forming an electrode on the groove to be in contact with the impurity introduced region.

The following is a cross-sectional structural diagram of an example of a semiconductor substrate to be processed shown in FIG. 2, and FIGS.
This will be explained in detail using process sectional views of the first embodiment shown in )K and process sectional views of the implementation row of FIG. 2 shown in FIGS.

When forming a Pibo 2 type semiconductor device by applying the present invention, the substrate to be processed may be, for example, embedded! - Diffusion.

A structure as shown in FIG. 2 is formed through regular steps such as epitaxial growth, selective thermal oxidation, and selective introduction of impurities. In other words, in Fig. 2, 11 is P-type silicon (Sl
) substrate, 12 is N+fjS, buried 14.13 is N-type silicon/(Si) epitaxial layer (collector region),
14 is the P1 type cordon separation region, 15 is N+f! l! Collector contact area, 16m, 16b, 16c.

16d and 16. indicate field silicon dioxide (Sin film).

The cross-sectional views of FIGS. 3(a) to 3(j) show an embodiment in which the present invention is applied only to the base region.

That is, first, as shown in FIG. 3(a), field S10. A first silicon nitride film (150-200 (A) 8 degrees
SisNa) #18 is formed. Next, as shown in FIG. 3 (6), a photoresist film 19 and a 5lsN+ film 18 are formed.
Selective etching is performed using the mask as a mask, and the field S1
0*0, 2 to 0.3 where the side surface of the NaSi epitaxial layer 13 is exposed on the film 16b. A base contact groove 20 with a depth of approximately (μm) is formed, and then, using the photoresist film 19 as a mask, implantation energy of, for example, 30 μm is formed.
(KeV ) injected iic 2 X 103' (at
Ion implantation of boron CB) is performed under conditions of about 100 m/-].

In this ion implantation, the boron ion B+ implantation region νa is formed deep in the 81-plane exposed region and shallow in the 5IIIN4 film-coated region (the globs indicate boron ions). Next, Figure 3 (
As shown in e), chemical vapor deposition (CV) is performed on the substrate to be processed.
D) A first non-doped polycrystalline St layer 22' having a thickness of about 0.5 [μ] is formed using the method, and then a skeleton layer 22' is formed.
For example, if the implantation energy is 'f-
High concentration boron ion implantation (21b) is performed under conditions of approximately 60 (KeV) and an implantation amount of 5 x 10'' (ate/at).
(B+ implanted region) 0 Then lift-off is performed and the third
As shown in Figure (d), a polycrystalline 81 base electrode wiring 22 is formed in a region covering the base contact groove 20, and a desired high temperature annealing treatment is performed to impart conductivity to the polycrystalline 81 base electrode wiring 22. At the same time, the boron B in the wiring is diffused into the Si epitaxial layer exposed in the base contact groove 20 to form a P+ type base contact region 23 in this region. Then Figure 3(e)
As shown in FIG. 2, a second non-doped polycrystalline St layer 24 having a thickness of about 500 mm is formed on the substrate to be processed including the surface of the base electrode line 220 using the CVD method. A second 81.N film 25' having a thickness of approximately fi2000 (λ) is formed by the KCVD method. Next, the second 5isN+ film 25' is patterned by the usual 7-to-etching method. As shown in FIG. 3(a), an 8isNa pattern 25 covering the emitter electrode window forming region 26 is formed, and using the 85N+ pattern 25 as a mask, the implantation energy is 40 (KeV)*implantation density 2×10 (
Boron (6) ions are implanted under conditions of approximately ala/I:11), and a desired high temperature annealing process is performed to form the P outdoor base region 27. Then 81aN+pattern 2
5 as an oxidation-resistant mask, the second polycrystalline Si layer 24 is selectively thermally oxidized to the bottom, and as shown in FIG. .

Then, as shown in FIG.
5 and the second polycrystalline 81 layer 24 below it and the first 8
The 11N4 film 18 is selectively etched away to form the 81
0*After forming the constructional ivy electrode window 26 on the insulating film 27, for example, injection energy 30 (K
Boron * (B) ions were implanted under conditions of approximately 5×10” (mtll/cd) to form an 8% human region 29' with a desired depth in the in-type s1 epitaxial layer, and then, as shown in FIG. As shown in (1), from the emitter electrode window 26, for example, the implantation energy is 60 (KeV)y, the implantation amount is 5.times.1
Arsenic ions (A
After implanting the B+ implanted region 29' at a high concentration, a desired high temperature annealing process is performed to form the P type internal space region 29 and the N0 type emitter region 30. Next, through normal vapor deposition and patterning steps, as shown in FIG. 3(j), a metal such as aluminum (A t>-81 alloy, etc.) is deposited on the electrode window 26.
Emitter electrode wiring 31 is formed. As mentioned above, the surface of the polycrystalline Sl space electrode wiring 22 is coated with the 5101 insulating film 2.
8, the emitter electrode wiring 31a can be formed over the space electrode wiring 22 by two layers.Next, although not shown, a wall insulating film is formed, etc., and a semiconductor device is provided. Ru.

Also, what is shown in the process cross-sectional views of FIGS. 4(a) to (e) is as follows.
This is an embodiment in which the present invention is applied to both the base region and the emitter region.

That is, as shown in FIG. 4(a), the polycrystalline Sl base electrode wiring on the semiconductor substrate to be processed is formed through the same steps as in the first embodiment and in the same structure as in FIG. 3(d). First, on the surface of 22, an Si, N, insulating film 32 with a thickness of 15 cF-200 [mu] is formed using a direct snow formation method (in Fig. 4, 13 is a NmSi epitaxial layer; 16b,
16c is a field stow film, 17 is an active region, 18
is the first St, N, film, 20 is the base contact groove,
23 indicates the P-type space contact region 0) then photoresist as shown in 1g4(b)K)Ill
Field Sin with 9 as a mask.

The exposed area of the film 16c is selectively etched, and an N-type 81 pitaxial layer 13 is formed on the field Sin and the film 16c.
An ivy contact 11133 with a depth of about 0.2 to 0.3 (Jlm) is formed to expose the side surface of the wafer, and then using the photoresist film 19 as a mask, for example, an implantation energy of 30 (Key) and an implantation amount are applied. 5 x 10” (ats
Selective implantation of boron ions (B+) is performed under conditions of approximately s/- to form a boron ion (B+) implanted region 34' of a desired depth in the N- type S1 epitaxial layer 13. Next, as shown in FIG. 4(e), the photoresist film 19 is
Then, using the first 5isN+ film 18 as a mask, the same region is implanted with an implantation energy of 20 [K·■] and an implantation amount of 5XI.
Arsenic ions (A I +) are selectively implanted at a high concentration under conditions of approximately OI" (ate/aA), and the B+ implanted region 3 is
An A8+ implantation region 35', which is shallower than the region 4', is formed within the region 4'.

After removing the photoresist film 19, a high-temperature annealing process is performed at a temperature of about 70% to form the P+ type space contact region on the upper part of the N type pitaxial layer 13, as shown in FIG. 4(d). A P-type internal space region 34 adjoining the P-type internal base region 23 is then deposited to form an i-processed region 35 within the P-type internal base region 34 .

As shown in FIG. 4(e)K through processes such as patterning, a metal/etched electrode wiring 31 made of At alloy or the like is formed on the contact groove 33 of the field 5ift film 16c, and then, although not shown, A semiconductor device is provided by forming a cover insulator and the like. As mentioned above, the surface of the polycrystalline S1 base Wi wiring 22 is 511N.
4, the metal emitter electrode wiring 31 can be formed to overlap the polycrystalline 81 base electrode wiring 22.

As is clear from the description of the above embodiments, when the present invention is applied only to the base region, the connection region between the base and the electrode wiring is formed on the side surface of the active region defined by the field insulating film. The length of the active region can be reduced by that amount.

Furthermore, when the present invention is applied to both the base region and the emitter region, both the connection slope of the pace electrode wiring and the connection region of the emitter electrode wiring are formed on the side surface of the active region defined by the field insulating film. , the length of the active region can be further reduced by that amount.

As explained above, according to the present invention, the area of the active region in a pibo-2 type semiconductor device such as an iso-planar structure in which the sides of the active region are defined by an insulating film can be reduced, so that the density of the device can be increased. Note that the method of the present invention can also be applied to semiconductor devices of opposite conductivity type.In addition to At alloys, wiring materials such as high-melting point metals, high-melting point metal silicides, and polycrystalline silicon can also be used for the emitter electrode wiring.

[Brief explanation of the drawing]

FIG. 1 is a schematic top view of a conventional iso-planar structure, FIG. 2 is a cross-sectional structural diagram of an example of a semiconductor substrate to be processed used in the method of the present invention, and FIGS. the first of
FIG. 4(a) to (・
) is a process sectional view in a second embodiment of the present invention. In the figure, 13 is an N-type silicon layer*
16 b @ 16 c is a field silicon dioxide film. 17 is an active region, 18 is a first silicon nitride film, 19 is a photoresist film, and 20 is a space contact groove. 21a, 21b, 29', and 34' are boron ion implanted regions. 22 is a polycrystalline silicon base electrode wiring, 23 is a P+ base φ contact region, 24 is an fa2 non-doped polycrystalline silicon layer, 25' is a second silicon nitride film, 2
5 is a silicon nitride pattern, 26' is an emitter electrode window forming region, 26 is an emitter electrode window, 27 is a P external space area, 28 is a silicon dioxide insulating film, and 29.34 is a P
Type internal pace area * go, s is T-type Niotsuta area,
31 is a metal/emitter electrode wiring, 32 is a silicon nitride insulating film, 33 is an emitter contact groove, 35' is an arsenic ion implantation region, B+ is a boron ion, and Aa+ is an arsenic ion. 1st 11th 3rd Kasumi 3rd Senhaya 1 Rod 4th Sen

Claims (1)

[Claims] In a method of manufacturing a bipolar semiconductor device having a structure in which the side surfaces of an active region are defined by a field insulating film, a groove is formed in the field insulating material to expose the edge side surface of the active region, and the inside of the active region is formed from the groove. 1. A method for manufacturing a semiconductor device, comprising the steps of introducing an impurity into the region, and then forming an electrode on the vaginal groove in contact with the impurity-introduced region.