JPS61154157A - semiconductor integrated circuit - Google Patents
semiconductor integrated circuitInfo
- Publication number
- JPS61154157A JPS61154157A JP59277343A JP27734384A JPS61154157A JP S61154157 A JPS61154157 A JP S61154157A JP 59277343 A JP59277343 A JP 59277343A JP 27734384 A JP27734384 A JP 27734384A JP S61154157 A JPS61154157 A JP S61154157A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- voltage
- input
- well
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 11
- 230000000295 complement effect Effects 0.000 claims abstract description 6
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 6
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 6
- 230000010355 oscillation Effects 0.000 claims description 7
- 239000003990 capacitor Substances 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 3
- 230000004075 alteration Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
- H10D84/85—Complementary IGFETs, e.g. CMOS
- H10D84/854—Complementary IGFETs, e.g. CMOS comprising arrangements for preventing bipolar actions between the different IGFET regions, e.g. arrangements for latchup prevention
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
- H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Logic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は半導体集積回路、特に相補型金属酸化膜半導体
装置を含んで構成される入力論理回路を有する半導体集
積回路に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit having an input logic circuit including a complementary metal oxide film semiconductor device.
（従来の技術）
従来、相補型金属酸化膜半導体装置（以下０ＭＯ８装置
と記す）を用いて構成される入力回路においては、入力
信号のア／ダーシ為−トまたはオーバーシェードにより
ラッチアップが発生するという問題がある。(Prior Art) Conventionally, in an input circuit configured using a complementary metal oxide film semiconductor device (hereinafter referred to as 0MO8 device), latch-up occurs due to input signal alteration or overshading. There is a problem.
第３図は従来の入力回路の一例の回路図である。FIG. 3 is a circuit diagram of an example of a conventional input circuit.
入力端子ｌより入力抵抗２ｔ−介して入力論理回路３の
ゲート４に接続され、４からは入力保護ダイオード５，
６ｔ−介してそれぞｆ’Ｌ ＶＤＤ端子７．Ｖ、。The input terminal l is connected to the gate 4 of the input logic circuit 3 via the input resistor 2t, and from 4 to the input protection diode 5,
6t- respectively through the f'L VDD terminal 7. V.
端子８ｖｃ接続されでいる。抵抗２及びダイオード５．
６の静電気印加時のそれぞれの働きについては公知であ
るため説明を省略する。Terminal 8vc is connected. Resistor 2 and diode 5.
Since the respective functions of No. 6 when static electricity is applied are well known, their explanations will be omitted.
（発明が解決しようとする問題点）
゛ この入力回路において、入力端子１ｖｃ（ｖＤＤ端
子電圧）＋（ダイオード５０順方向電圧）以上の電圧ま
たは（Ｖｓｓｆｌｆｌ子電圧）−（ダイオード６の順方
向電圧）以下の電圧が加わった場合、ダイオード５．６
に電流が流れ、ラッチアップを発生するという問題が生
じる。(Problems to be Solved by the Invention) ゛ In this input circuit, a voltage greater than or equal to input terminal 1vc (vDD terminal voltage) + (diode 50 forward voltage) or (Vssflfl child voltage) - (diode 6 forward voltage) If the following voltage is applied, the diode 5.6
A problem arises in that current flows through the circuit, causing latch-up.
本発明の目的ａ、ＣＭＯ８装置金用い装置成用れる入力
論理回路と入力保護ダイオードとを含む入力回路を有し
、入力信号がアンダーシェードまたはオーバーシェード
になっても入力保護ダイオードに電流が流ルないように
し、ラッチアップ耐量を向上させた半導体集積回路を提
供することにある。An object of the present invention is to have an input circuit including an input logic circuit and an input protection diode for use in a CMO8 device, and to prevent current from flowing through the input protection diode even if the input signal is undershaded or overshaded. An object of the present invention is to provide a semiconductor integrated circuit with improved latch-up resistance.
（問題点を解決するための手段）
本発明の半導体集積回路は％ＰウェルまたはＮウェル金
有する相補型金属酸化膜半導体装置を含んで構成される
入力論理回路と、発振回路と、該発振回路の出力信号全
直流に変換し、得らルた出力電圧全前記Ｐウェルまたは
Ｎウェルに供給する整流回路と金含んで構成される。(Means for Solving the Problems) The semiconductor integrated circuit of the present invention includes an input logic circuit including a complementary metal oxide film semiconductor device having a P-well or an N-well, an oscillation circuit, and the oscillation circuit. The rectifier circuit converts all of the output signals into direct current and supplies all of the obtained output voltage to the P-well or N-well.
（実施例） 次に５本発明の実施例について図面を用いて説明する。(Example) Next, five embodiments of the present invention will be described with reference to the drawings.
第１図に本発明の第１の実施例の回路図である。FIG. 1 is a circuit diagram of a first embodiment of the present invention.
この実施例は、°Ｐウェル１２ｔ”Ｗする相補現金属酸
化膜半導体装［１に含んで構成される入力論理回路１１
と１発振回路１３と１発振回路１３の出力信号ｔ−直流
に変換し、得らｎた出力電圧’ｔＰウェル１２に供給す
る倍電圧整流回路１５とｔ含んで構成さｎる。In this embodiment, an input logic circuit 11 included in a complementary metal oxide semiconductor device [1] having a °P well 12t''W is used.
and a voltage doubler rectifier circuit 15 which converts the output signal t of the oscillation circuit 13 into DC and supplies the obtained output voltage to the well 12.
次に、この実施例の動作について説明する。Next, the operation of this embodiment will be explained.
発振回路１３にエリ（ｖＤＤ端子電圧） −（Ｖｓａ端
子電圧）を振幅とする信号を発振させ、この信号をコ／
デノサ１４、ｖＳＳ端子１６につながった倍電圧整流回
路１５ｔ”通すことに工りＶ８Ｓ端子電圧エリ低い一定
の電圧を作る。倍電圧整流回路１５の出力を入力論理回
路１１のＰウェル１２につなぐことＶｃＪ：す、Ｐウェ
ル１２の電位はＶ８８端子電圧より低くすることができ
る。この働きにＬり入力端子ｌの電位が（Ｐウェル１２
の電位）−（ダイオード６の従万同電圧）以下に下がら
ないと。The oscillation circuit 13 is caused to oscillate a signal whose amplitude is ERI (vDD terminal voltage) - (Vsa terminal voltage), and this signal is
The output of the voltage doubler rectifier circuit 15 is connected to the P well 12 of the input logic circuit 11 by passing the voltage doubler rectifier circuit 15t'' connected to the denosa 14 and the vSS terminal 16 to create a constant voltage with a low voltage at the V8S terminal. VcJ: The potential of the P well 12 can be made lower than the V88 terminal voltage.
The voltage must fall below - (potential of diode 6) - (potential of diode 6).
ダイオード６には電流は流れないという効果がある。The diode 6 has the effect that no current flows.
第２図は本発明の第２の実施例の回路図である。FIG. 2 is a circuit diagram of a second embodiment of the invention.
この実施例は、Ｎウェル２２に倍電圧整流回路２３の出
力電圧を供給する例である。入力端子１の電圧が（Ｎウ
ェル２２の電位）十（ダイオード５の順方＠電圧）以上
に上らないとダイオード５には電流は流れないという効
果がある。その他の動作に第１の実施例と同様である。This embodiment is an example in which the output voltage of the voltage doubler rectifier circuit 23 is supplied to the N well 22. There is an effect that no current flows through the diode 5 unless the voltage at the input terminal 1 rises to (the potential of the N well 22) or more (the forward @ voltage of the diode 5). Other operations are similar to those in the first embodiment.
（発明の効果）
以上説明したように、本発明に工ｎば、入力信号のアン
ダーシェードまたはオーバーシェードとがありでも入力
保護ダイオードに電流が流詐ず、ラブチアツブ耐量全向
上させ７’？、＃Ｐ導体集積回路が得られる。(Effects of the Invention) As explained above, by incorporating the present invention, even if there is undershading or overshading of the input signal, current will not flow to the input protection diode, and the love-chip withstand capability will be completely improved. , #P conductor integrated circuit is obtained.
第１図は本発明の第１の実施例の回路図、第２図は本発
明の第２の実施例の回路図、第３図は従来の入力回路の
一例の回路図である。
ｌ・・・・・・入力端子、２・・・・・・抵抗、３・・
・・・・入力論理回路、４・・・・・・ゲート％ ５．
６・・・・・・ダイオード、７・・・・・・ＶＤＤ端子
、８・・・・・・ＶＳＳ端子、１１・・・・・・入力論
理回路、１２・・・・・・Ｐウェル、１３・・・・・・
発振回路。
１４・・・・・・コツプ／す、１５・・・・・・倍電圧
整流回路、１６・・・・・・ＶＳＳ端子、２１・・・・
・・入力論理回路、２２・・・・・・Ｎウェル、２３・
・・・・・倍電圧整流回路。
代理人 弁理士 内 原 晋 ゛牛１つFIG. 1 is a circuit diagram of a first embodiment of the present invention, FIG. 2 is a circuit diagram of a second embodiment of the present invention, and FIG. 3 is a circuit diagram of an example of a conventional input circuit. l...Input terminal, 2...Resistor, 3...
...Input logic circuit, 4...Gate% 5.
6...Diode, 7...VDD terminal, 8...VSS terminal, 11...Input logic circuit, 12...P well, 13...
Oscillation circuit. 14...Cop/su, 15...Voltage doubler rectifier circuit, 16...VSS terminal, 21...
...Input logic circuit, 22...N well, 23.
...Voltage doubler rectifier circuit. Agent Patent Attorney Susumu Uchihara ゛One cow
Claims (1)
導体装置を含んで構成される入力論理回路と、発振回路
と、該発振回路の出力信号を直流に変換し、得られた出
力電圧を前記ＰウェルまたはＮウェルに供給する整流回
路とを含むことを特徴とする半導体集積回路。An input logic circuit including a complementary metal oxide semiconductor device having a P-well or an N-well, an oscillation circuit, and an output signal of the oscillation circuit that is converted into direct current, and the resulting output voltage is applied to the P-well. or a rectifier circuit that supplies an N-well.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59277343A JPS61154157A (en) | 1984-12-27 | 1984-12-27 | semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59277343A JPS61154157A (en) | 1984-12-27 | 1984-12-27 | semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61154157A true JPS61154157A (en) | 1986-07-12 |
Family
ID=17582201
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59277343A Pending JPS61154157A (en) | 1984-12-27 | 1984-12-27 | semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61154157A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS647554A (en) * | 1987-06-29 | 1989-01-11 | Nec Corp | Semiconductor integrated circuit device |
| JPH0336229U (en) * | 1989-08-18 | 1991-04-09 | ||
| JPH03501669A (en) * | 1987-12-23 | 1991-04-11 | シーメンス、アクチエンゲゼルシヤフト | Integrated circuit with latch-up protection circuit |
| JPH03501792A (en) * | 1987-12-23 | 1991-04-18 | シーメンス、アクチエンゲゼルシヤフト | Integrated circuit with “latch-up” protection circuit using complementary MOS circuit technology |
| JPH03194965A (en) * | 1989-12-22 | 1991-08-26 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
-
1984
- 1984-12-27 JP JP59277343A patent/JPS61154157A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS647554A (en) * | 1987-06-29 | 1989-01-11 | Nec Corp | Semiconductor integrated circuit device |
| JPH03501669A (en) * | 1987-12-23 | 1991-04-11 | シーメンス、アクチエンゲゼルシヤフト | Integrated circuit with latch-up protection circuit |
| JPH03501792A (en) * | 1987-12-23 | 1991-04-18 | シーメンス、アクチエンゲゼルシヤフト | Integrated circuit with “latch-up” protection circuit using complementary MOS circuit technology |
| JPH0336229U (en) * | 1989-08-18 | 1991-04-09 | ||
| JPH03194965A (en) * | 1989-12-22 | 1991-08-26 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5512844A (en) | Output circuit with high output voltage protection means | |
| JPS61154157A (en) | semiconductor integrated circuit | |
| JPH0563943B2 (en) | ||
| JPH0316648B2 (en) | ||
| JPS60141020A (en) | Cmos logic circuit | |
| JPS63132527A (en) | Cmos logic circuit | |
| JPH0335497A (en) | Output buffer circuit | |
| JPH0244914A (en) | Input circuit for semiconductor device | |
| JPS60215223A (en) | Dc voltage generating circuit | |
| JPH036664B2 (en) | ||
| JPS61126820A (en) | Ternary input circuit | |
| JPH02192218A (en) | Cmos integrated circuit | |
| JPS6334798A (en) | Latch circuit | |
| JPH05152530A (en) | Semiconductor integrated circuit | |
| JPH03103025A (en) | Semiconductor integrated circuit device | |
| JPS60189322A (en) | Semiconductor circuit device | |
| JPS62259292A (en) | Semiconductor integrated circuit device | |
| JPH03145921A (en) | Semiconductor integrated circuit device | |
| JPH03222515A (en) | Two phase clock generating circuit | |
| JPS61255048A (en) | Internal supply voltage generating circuit in semiconductor integrated circuit | |
| JPS6216616A (en) | Semiconductor integrated circuit | |
| JPH0457358A (en) | Integrated circuit device with plurality of power supplies | |
| JPS63169121A (en) | Multi-value threshold logical circuit | |
| JPS62159914A (en) | Ecl compatible output circuit | |
| JPH01115218A (en) | Semiconductor device |