JPS6334798A - Latch circuit - Google Patents

Abstract

PURPOSE:To suppress current consumption as low as possible by providing a transistor (TR) whose threshold voltage is near 0V to a 2nd inverter in series and connecting the input of the TR to the input of the 1st inverter. CONSTITUTION:If an input voltage is 'H' when a CLK is 'H', a TR 3 is turned on, a TR 4 is turned off, an output is turned to 'H', and a through current flows from a TR 5 to the TR 3. When the input voltage is 'L', the TR 3 is turned off, the TR 4 is turned on and the output is turned to 'L'. At that time, a TR 7 also is turned off, so that no through current flows TRs 7 6 4 if the threshold voltage of the TR 7 is >=0V, and in case of <=0V, only a fine current determined by the threshold voltage of the TR 7 flows.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a latch circuit, and particularly to a latch circuit suitable for reducing the power consumption of a shift register when the latch circuit is used to configure the shift register.

[Conventional technology]

FIG. 2 shows a conventional latch circuit that constitutes one bit of a shift register. In the figure, 1 to 4 are enhancement type N-channel transistors, 5.6 is a depletion type N-channel transistor, and transistors 1, 5, and 6 are depletion type N-channel transistors. 2
According to the 1st. The second transmission gate includes transistors 3 and 5.
and 4 and 6, the first and second inverters 10 and 2
0 is configured respectively.

Note that IN is an input terminal, OUT is an output terminal, cI2 is τ
Finished T is the 1st. This is the second clock input terminal.

Next, the operation will be explained. Clock c i! k′
When the voltage is "H", transistor 1 is turned on and the input voltage is read. When the input voltage is “H”, transistor 3 is turned on and the input of transistor 4 is “L”, which is “1”.
When the input voltage is "L", the transistor 3 is turned "off" and the transistor 4 is "on", and a "L" signal is output.

Next, when the clock cAk becomes "L2", the transistor 1 turns off, but at this time, the transistor 2 turns on, so the output of the inverter 10 is returned to the input of the inverter 10 via the transistor 2, and the feedback loop The above input voltage is latched.

[Problem that the invention seeks to solve]

Since the conventional launch circuit is configured as described above, when the input voltage is "H", a through-am current flows through the transistor 5-3, and when the input voltage is "L", an am current flows through the transistor 5-3. A through current flows through the transistor 6→4. Therefore, in the case of a mask slave type shift register formed by connecting two such latch circuits in series, the output voltage is 21 ds (
There is a problem that a through current of Ids (through current flowing through one inverter) always flows.

This invention was made to solve the above-mentioned problems, and aims to obtain a notch circuit whose design goal is to reduce current consumption as much as possible.

[Means for solving problems]

In the launch circuit according to the present invention, a transistor having a threshold voltage near OV is provided in series with the second inverter, and its input is connected to the input of the first inverter.

[Effect]

In this invention, the input of the transistor connected in series to the second inverter and having a threshold voltage near O■ is connected to the first inverter.
is connected to the input of the inverter, and the input voltage is “L”.
”, the transistor is “off”, so not only the first inverter but also the second inverter has 1ff.
i Current stops flowing.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure shows a latch circuit according to an embodiment of the present invention. In the figure, 1 to 4 are enhancement-type N-channel transistors, 5 and 6 are depletion-type N-channel transistors, and 7 is an N-channel transistor with a threshold voltage near 0. It is a transistor.

Next, the operation will be explained.

c! When k is "H", if the input terminal is "H", transistor 3 is "on", transistor 4 is "off", and the output becomes "H", and at this time, a through current flows through transistor 5-3. .If the input voltage is “L”, transistor 3
is 1 off,” transistor 4 is on, and the output is “1 off.”
It becomes L''.

At that time, the transistor 7 is also turned off, so if the threshold voltage of the transistor 7 is OV or higher, no through 7ri current flows through the transistor 7-6-4, and if it is 0V or lower, a minute current determined by the threshold voltage of the transistor 7 flows. It only flows.

In this way, according to this embodiment, the VC of the second inverter
An N-channel transistor with a threshold voltage near 0V is installed between the node that should become the C terminal and the VCC terminal, and the input is L.
Since no through current is allowed to flow through the second inverter when ``, the through current is halved, which is extremely advantageous especially when used in a shift register to reduce its power consumption.

In addition, although the above embodiment shows the case of N-channel type,
A p-channel type may be used, and the same effects as in the above embodiment can be achieved.

〔Effect of the invention〕

As described above, according to the launch circuit 1 according to the present invention, the through current of the inverter can be significantly reduced, so that it can be advantageously used in a shift register.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a latch circuit according to an embodiment of the present invention;
FIG. 2 is a diagram showing a conventional latch circuit. In the figure, 1 and 2 are the first. second transmission gate, 10.
20 is the first. The second inverter, 7 is a transistor, V
CC is a high voltage power supply, cj! , TTT is the first. This is the second clock input terminal. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) The drain of the first transmission gate is the input of this latch circuit, the source is connected to the drain of the second transmission gate and the input of the first inverter, and the output of the first inverter is connected to the input of the second inverter. The output of the second output inverter is connected to the input, and the output of the second output inverter is the output of this latch circuit, and the source of the second transmission gate is connected to the gate of the first and second transmission gates. In a latch circuit connected to first and second clock input terminals to which signals are respectively input, a node to which a higher potential power supply of the first and second power supplies of the second inverter is connected is connected. A latch circuit characterized in that a transistor having a threshold voltage of approximately 0V is inserted between the high potential power source and the gate thereof is connected to the input of a first inverter.