JPH03194965A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent a current from flowing through a depletion layer development region of a complementary logical circuit without lowering of integration even if a high voltage is supplied from the outside in a state of high impedance by inserting a step-up circuit between the depletion layer development region of a first transistor and a first power supply of an output buffer circuit. CONSTITUTION:In a semiconductor integrated circuit device having a plurality of output buffer circuits, each output buffer circuit has a first transistor 1 of a first conductivity type and a second transistor 2 of a second conductivity type which are inserted one by one in series between a first power supply VDD1 to supply a relatively high voltage and a second power supply VSS to supply a relatively low voltage. An output terminal 5 is connected to a connecting part of the first and second transistors 1, 2. In at least a part of the plurality of output buffer circuits, a step-up circuit 30 is inserted between a depletion layer development region 15 of the first transistor 1 and the first power supply VDD1 to thereby supply a voltage which is higher than the first power supply VDD1 to the depletion layer development region 15.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device configured with complementary logic circuits.

[Conventional technology]

Semiconductor integrated circuit devices (hereinafter referred to as ``low voltage LS IJ'') use a power supply voltage lower than the conventional standard power supply voltage (5V) in order to alleviate the high electric fields within integrated circuits that occur with higher integration. ) is used.

FIG. 7 is a circuit diagram showing a complementary circuit (hereinafter referred to as an rcMoS circuit) which is an output buffer circuit of such a low voltage LSI and is directly connected to an external circuit. Moreover, FIG. 8 is a schematic cross-sectional view of the semiconductor device.

In these figures, a source 11 of a p-channel MOS transistor 1 (hereinafter referred to as [PMOSTJ) is connected to a power supply potential V 1 .

DI Also, n-channel MOS transistor 2 (rNM
It is called oSTJ. ) is connected to the ground potential vss. Furthermore, the drain 12 of NMOS T1
and the drain 22 of PMO3T2 are connected to each other and to an output terminal 5 for connection to an external circuit. Furthermore, the gate 13 of NMOS T1 and the gate 23 of PMO3T2 are connected to different gate input terminals 3 and 4, respectively.

As shown in FIG. 8, the power supply potential V 1 is connected not only to the n-type diffusion region 11 which is the source of PMDI OSTI, but also to the n-type diffusion region 14 formed adjacent thereto. This allows n-well 1 of PMO3TI to
A power supply potential V is applied to DI. On the other hand, the ground potential Vss is connected not only to the n-type diffusion region 21 which is the source of the NMOS T 2, but also to the n-type diffusion region 24 formed adjacent to it, which makes it a p-type head region. A ground potential V83 is applied to the substrate region 25 of NMO3T2.

Figure 9 shows the output buffer of a low voltage LSI and the standard voltage L
FIG. 2 is a circuit diagram showing a state in which an SI output buffer is connected. In the figure, the output terminal 5 of the low voltage LSI 100 and the output terminal 205 of the standard voltage LSI 200 are connected. The buffer circuit at the output end in the standard voltage LSI 200 has a similar configuration to the buffer circuit at the output end in the low voltage LS I 1100, but the power supply potential V in the standard voltage LSI 200 is different from the power supply potential in the low voltage LSI 100. It is higher than the potential D2. Note that the ground potential "ss" in the standard voltage LDI SI 200 and the ground potential v88 in the low voltage LSI 100 are the same potential.

[Problem to be solved by the invention]

In FIG. 9, PMO3TI in the low voltage LSI 100
Apply H level to gate input terminal 3 of NMOS T
When an L level is applied to the gate input terminal 4 of No. 2, this CMO8 circuit enters a high impedance state. At this time, when an L level is applied to the gate input terminal 203 of the PMO3T201 and the gate input terminal 204 of the NMO3T202 in the standard voltage LSI 200, the output terminal 205
．． 5, the power supply voltage V is outputted. As can be seen from FIG. 8, the power supply voltage V is applied to the well 15 (also called the depletion layer generation region) of the NMOS T1, so a fairly high voltage V is applied to the output terminal 5. Then, the p-type drain 12 and the n-type well 15
is the forward bias. Therefore, during this time the standard voltage LSI
There is a problem that current continues to flow from LSI 200 to low voltage LSI 100.

Conventionally, low voltage LSI output buffers and standard voltage LSI
Since the above-mentioned problem would occur if the output buffer of the output buffer was directly connected, it was necessary to take measures such as connecting the two via a level conversion IC.

This has caused problems such as a significant reduction in the degree of integration on the board on which the LSI is mounted.

This invention was made to solve the above-mentioned problems in the prior art, and it is possible to prevent depletion of a complementary logic circuit even when a high voltage is supplied from the outside in a high impedance state without reducing the degree of integration. An object of the present invention is to obtain a semiconductor integrated circuit device in which no current flows through a layer generation region.

[Means to solve the problem]

According to the present invention, in a semiconductor integrated circuit device including a plurality of output buffer circuits, each output buffer circuit is connected in series between a first power supply that provides a relatively high voltage and a second power supply that provides a relatively low voltage. A first transistor of a first conductivity type and a second transistor of a second conductivity type are sequentially inserted into the transistor, and an output terminal is connected to a connection portion between the first and second transistors; In at least some of the output buffer circuits among the plurality of seven output buffer circuits, a booster circuit is inserted between the depletion layer generation region of the first transistor and the first power supply, so that the A voltage value higher than the first power supply is supplied to the depletion layer generation region.

[Effect]

Since a high voltage is applied to the depletion layer generation region of at least some of the buffer circuits, the degree of integration is not excessively reduced, and even if these buffer circuits are in a high impedance state, the depletion layer region is No current flows from the external circuit through the

〔Example〕

FIG. 1 is a circuit diagram showing a buffer circuit according to an embodiment of the present invention. Moreover, FIG. 2 is a schematic cross-sectional view of the semiconductor device.

In these figures, the source 11 of PMO3TI is connected to the power supply potential V 2 . Further, the source 21 of the NDI MO5T2 is connected to the ground potential v88. Furthermore, the drain 12 of NMOS T1 and PMO
The drains 22 of 5T2 are connected to each other and to the output terminal 5 for connection to an external circuit. Also, the gate 13 of NMOS T1 and PMO3
The gate 23 of T2 is a separate gate input terminal 3.
．． Connected to 4.

As shown in Figure 2, p as the source of PMO5TI
An n-type diffusion region 14 is formed adjacent to the type diffusion region 11, and this n-type diffusion region 14 is connected to a power supply potential V DI via a booster circuit 30 . On the other hand, the ground potential vs8 is NMOS T 2
It is connected to the p-type diffusion region 24 formed adjacent to the n-type diffusion region 21 which is the source of the n-type diffusion region 21 . As a result, the ground potential v88 is applied to the substrate region 25 of the NMOS T 2, which is a p-type head region.

FIG. 3 is a circuit diagram showing the internal configuration of the booster circuit 30. This booster circuit 30 is a circuit conventionally known as a charge pump circuit. Two diodes 33 are connected between the input terminal 31 and the output terminal 32 of the booster circuit 30.
34 are inserted in series. Further, a capacitor 35 and a ring oscillator 37 are connected in series to a node 38 between the two diodes 33 and 34. This ring oscillator 37 is composed of an odd number of inverters 36.

The input terminal 31 of the booster circuit 30 is supplied with the power supply potential V 1 , and the charge of the AC component generated by the ring oscillator 37 is stored in the capacitor 35 . While the AC component of the ring oscillator 37 is positive, the output terminal 32
The charge is sent out at voltage v2 from .

On the other hand, while the alternating current component is negative, the diodes 33 and 34 prevent the charge from flowing back toward the input terminal 31 side.

The voltage V2 generated at the output terminal 32 is connected to the diode 33.3.
The voltage DI is higher than the power supply potential V by a voltage approximately equal to the sum of the four threshold voltages. For example, when the power supply potential V is approximately 3.3V, the threshold voltage of the DI diodes 33 and 34 is approximately 0.8V.
When the voltage is 5V, the voltage V2 generated at the output terminal 32 is approximately 5V.
(-3,3+0.85+0.85). Note that the booster circuit 30 is configured so that the standard voltage V2 is higher than the standard voltage of a general LSI (for example, 5V).

The output terminal 32 is connected to the n-type diffusion region 14 of PMOS T 1 shown in FIG. That is, n of PMO8T
A boosted voltage v is applied to the type diffusion region 14 and the well 15.
2 is applied.

FIG. 4 is a circuit diagram showing a state in which the output buffer of the low voltage LSI 300 and the output buffer of the standard voltage LSI 200 are connected. In the figure, a low voltage LSI 300
Output terminal 5 of , and output terminal 205 of standard voltage LSI 200
are connected. The buffer circuit at the output end in the standard voltage LSI 200 has a similar configuration to the buffer circuit at the output end in the low voltage LSI 300, but its PMO3
A circuit such as the booster circuit 30 is not connected to T201. In addition, the power supply voltage V9 in the standard voltage LSI 200,
2 is higher than the power supply voltage V in the low voltage LS 1300. In addition, the ground potential vss in the standard voltage LDI SI 200 and the low voltage LS I
The ground potential within 300 is the same potential.

In FIG. 4, PMO8 in the low voltage LSI 300
Applying H level to gate input terminal 3 of T1, NMOS
When an L level is applied to the gate input terminal 4 of T2,
This buffer circuit enters a high impedance state. At this time, PMO9T20 in standard voltage LSI 200
When an L level is applied to the gate input terminal 203 of NMOS T 1 and the gate input terminal 204 of NMOS T 202, the power supply voltage V 2 is outputted to the output terminal 205.5. By the way, like D2 mentioned above, the standard voltage L is applied to the well 15 of NMOS T1.
A voltage V2 higher than the power supply voltage V of the SI 200 is applied from the D2 booster circuit 30. Therefore, in FIG. 2, even when the voltage V 2 is applied to the output terminal 5 and D2, forward bias does not occur between the p-type drain 12 and the n-type well 15. Therefore, during this time, the current does not continue to flow from the standard voltage LSI 200 to the low voltage LSI 300.

FIG. 5 is a schematic plan view showing the entire chip of a low voltage LSI 300 manufactured by the master slicing method. When output buffers of a low-voltage LSI and a standard-voltage LSI are connected, at least one of the buffers is often a buffer that takes a hi-bindance state. FIG. 5 shows a low voltage LSI 3 in which a buffer circuit in a high impedance state is configured as shown in FIG.
00 is a diagram showing an example. In the figure, the periphery of the chip 300 has 110,871 columns 41 to 41, 42 n 1 to 42.43 to 43.44, to 44. and n
1 n buffer cell rows 51-51.521-52n.

n 53-53.541-54'n is formed. Each buffer in the buffer cell column has a well region 6
1~61.62 ~61.63□~1
n I n63.641
~64n are provided. These well areas are
Well 15 in the figure and PMO formed within its surface
This corresponds to a region including STl. Furthermore, an internal logic element area 60 is formed in the center of the chip.

Regions 71, 72, and 73 indicated by broken lines in the figure are regions including a buffer in a high impedance state and its I10 pad. Of these, well regions 61 and 61j in regions 71 and 72 at the upper stage of the chip in the figure are connected by wiring 81 to a booster circuit 30a formed at the upper left corner of the chip. In addition, the area 73 at the bottom of the chip
The inner well region 63 is connected to the booster circuit 30b formed in the same region 73 by a wiring 82. That is, the buffer circuits in these regions 71, 72, and 73 are formed as shown in FIGS. 1 and 2.

As mentioned above, this low voltage LSI 300 is created using the master slice method.

That is, first, the internal logic element area 6 buffer rows 51 to 51, 52 . ~52n.

n 53 to 53.54 to 54, and booster port 1
In the areas where the n i n paths 30a are to be formed, transistors and other elements necessary to complete them are formed. Note that at this time, especially the lower buffer rows 531 to
Elements necessary to configure the booster circuit 30b are formed in each region 53n.

Next, in a wiring process, each element is connected to each other to form a desired circuit, and an LSI as shown in FIG. 5 is completed. Note that the wiring process is the process of drilling contact holes and peer holes and laying the necessary wiring.
It is also called the slicing process.

Area 71 including a buffer that assumes a high impedance state
, 72, 73 are determined before the wiring process. In the wiring process, the booster circuits 30a and 30b are wired and configured as shown in FIG. 3, and wirings 81 and 82 are formed as shown in FIG.

A buffer circuit as shown in FIG. 2 is formed.

Note that the buffer circuits other than the areas 71, 72, and 73 do not take a high impedance state, so they are configured as shown in FIGS. 7 and 8 (that is, PMOSTl
The well 15 is supplied with a power supply voltage V for low voltage LSI). Dl Oh, in this way, in order to be able to individually change the configuration of each buffer circuit in the buffer row, each well region 611 to 61n, 62 to
62.63 ~53.54□1 n
1. n~64 are separated from each other.

The booster circuits 30a and 30b may be formed anywhere within the chip. That is, it may be formed as an independent region, like the booster circuit 30a in the upper left corner of FIG. Further, it may be formed in each region where a buffer circuit is formed, such as the booster circuit 30b.

In the above embodiment, the voltage v2 is always supplied to the well 15 of the PMOST1 in the buffer circuit, which may assume a zero impedance state.

However, the voltage v2 may be supplied from the booster circuit 30 only when the buffer circuit is in a high impedance state. FIG. 6 is a circuit diagram showing a three-state buffer configured as such a buffer circuit.

This three-state buffer is obtained by adding an NMO5T91, a two-man powered NAND circuit 92, a two-man powered NOR circuit 93, and an inverter circuit 94 to the buffer circuit shown in FIG. The NMOS T 91 is connected in parallel with the booster circuit 30, and its substrate area is connected to the ground potential ■
88. Furthermore, the gate of NMO3T91 is connected to the control terminal 96 of the 3-state buffer.

This control terminal 96 is also connected to one input terminal of the two-man power NAND circuit 92. 2 person NA
The other input terminal of the ND circuit 92 is connected to the data input terminal 95 of the 3-state buffer. 2 person power ANAD
The output terminal of circuit 92 is connected to the gate of PMO3TI.

One input terminal of the two-man power NOR circuit 93 is connected to a data input terminal 95, and the other input terminal is connected to a control terminal 96 via an inverter 94.

In addition, the output terminal of the two-man power NOR circuit 93 is NMOS T
It is connected to gate 2.

In the 3-state buffer shown in FIG. 6, when an H level is input to the control terminal 96, the L level or H level signal input to the data input terminal 95 is directly output to the output terminal 5. Also, at this time, NMO
Since the 3T91 is turned on, the power supply voltage V 1 is applied to the well 15 of the PMO3TI.

DL On the other hand, when an H level signal is input to the control terminal 96, even if an L level or H level signal is input to the data input terminal 95, the two-person NAND circuit 92 and the two-person NAND circuit 92
The OR circuits 93 always output H level and L level, respectively. Therefore, PMO3TI and NMOS T
2 are both in an off state, and the output terminal 5 is in a high impedance state. However, at this time, 8MO8T
Since 91 is also turned off, well 15 of 2MO8T1
is a voltage V2 higher than the standard voltage vD02 from the booster circuit 30.
is applied. In such a zero impedance state, even if an output signal with a voltage value of the standard voltage V is applied from the external LSI to the output terminal 5, the drain 12 and well of the PMO3TI are
5, there is no forward bias. Therefore, it is possible to prevent current from flowing from the power supply side of the standard voltage LSI to the power supply side of the low voltage LSI. In addition, when it is not in a high impedance state, the power supply voltage V is applied to the well 15 of PMO5TI.
is applied, there is an advantage that the operating characteristics of the DI PMO3T1 can be made the same as those of the PMO8T in a buffer circuit without a booster circuit as shown in FIG.

In addition, in FIG. 6 above, 8MO8T is connected in parallel with the booster circuit 30.
An example in which 91 is connected is shown. However, when the signal is output from the buffer circuit, the power supply voltage y is applied to the well 15 of 2MO8T1, and when the impedance state is DI, the voltage v2 is applied to the well 15 from the booster circuit 30. Other configurations may be used as long as the circuit is suitable.

Further, the booster circuit 30 is not limited to the circuit shown in FIG. 5, and may be any circuit that can supply a voltage v2D2 higher than the power supply voltage V of the external circuit. Of course, the booster circuit may be constructed of elements other than CMOSFETs, such as bipolar transistors.

Although the CMOS circuit of the above embodiment has an n-well formed on a p-type substrate and a PMO5T formed within the n-well, the CMOS circuit may be configured in other configurations. That is, it is sufficient that the DI is configured to apply a predetermined voltage V2 higher than the power supply voltage V2 to the region below the gate of the PMO3T (depletion layer generation region) when the buffer circuit is in a high impedance state.

Note that when a voltage v2 higher than the power supply voltage V2 is applied to the depletion layer generation region of PMO5T, the threshold voltage of PMO3T changes due to the substrate bias effect. However, for example, the power supply voltage V is 3.3V.

When DI voltage v2 is 5V, the change in threshold voltage is approximately 1
It is about v. Therefore, unless the voltage V2 is made excessively high, the voltage level to be applied to the gate will not change.
PMOST with a booster circuit is replaced by a PMOS without a booster circuit.
It is possible to control it in the same way as T.

〔Effect of the invention〕

As explained above, according to the present invention, a high voltage is applied to the depletion layer generation region of at least some of the buffer circuits, so that the degree of integration is not excessively reduced, and these buffer circuits are kept in a high impedance state. Even if it is like this, it has the effect of preventing current from flowing from the external circuit through the depletion layer generation region.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a buffer circuit in an embodiment of the present invention, FIG. 2 is a schematic cross-sectional view showing the semiconductor device,
3 is a circuit diagram showing a booster circuit, FIG. 4 is a circuit diagram showing a connection state between a low voltage LSI according to an embodiment of the present invention and a standard voltage LSI, and FIG. 5 is a circuit diagram showing a low voltage LSI according to an embodiment of the invention. A plan view showing a voltage LSI, FIG. 6 a circuit diagram showing another buffer circuit according to an embodiment of the present invention, FIG. 7 a circuit diagram showing a conventional buffer circuit, and FIG. 8 a schematic cross section showing the semiconductor device. 9 are circuit diagrams showing a connection state between a conventional low voltage LSI and a standard voltage LSI. In the figure, 1 is PMOST and 2 is NMO8T. 5 is an output terminal, 30 is a booster circuit, ■ is a power supply type D1, and vss is a ground potential. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] (1) A semiconductor integrated circuit device including a plurality of output buffer circuits, each output buffer circuit having a connection between a first power supply that provides a relatively high voltage and a second power supply that provides a relatively low voltage. A first transistor of a first conductivity type and a second transistor of a second conductivity type are sequentially inserted in series, and an output terminal is connected to a connection portion between the first and second transistors. In at least some of the output buffer circuits of the plurality of output buffer circuits, a booster circuit is inserted between the depletion layer generation region of the first transistor and the first power supply, and this A semiconductor integrated circuit device, wherein a voltage value higher than that of the first power supply is supplied to the depletion layer generation region.