JPS61150352A - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS61150352A JPS61150352A JP59275351A JP27535184A JPS61150352A JP S61150352 A JPS61150352 A JP S61150352A JP 59275351 A JP59275351 A JP 59275351A JP 27535184 A JP27535184 A JP 27535184A JP S61150352 A JPS61150352 A JP S61150352A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- package
- silver paste
- cavity
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 45
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 19
- 229910052709 silver Inorganic materials 0.000 claims description 19
- 239000004332 silver Substances 0.000 claims description 19
- 239000000853 adhesive Substances 0.000 description 6
- 230000001070 adhesive effect Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 230000003313 weakening effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes)
- H01L23/4827—Materials
- H01L23/4828—Conductive organic material or pastes, e.g. conductive adhesives, inks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
- H01L2924/15155—Shape the die mounting substrate comprising a recess for hosting the device the shape of the recess being other than a cuboid
- H01L2924/15156—Side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Die Bonding (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体チップのパッケージの構造に係わり、
半導体チップをパックするパッケージと、半導体チップ
との接合を、高信頼化するために行うものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to the structure of a semiconductor chip package,
This is done to increase the reliability of the bond between the package that packs the semiconductor chip and the semiconductor chip.
通常、半導体チップはパッケージに収納されて固着され
るが、固着方法は銀ペーストを用いて行うことがある。Usually, a semiconductor chip is housed in a package and fixed, and the fixing method is sometimes performed using silver paste.
然しながら、パ・７ケージのキャビティ底面は平面であ
るために、コーナ邪の断面が直角になり、この部分に盛
られる銀ペーストは殆どが半導体チップの底面にのみ被
着してしまうので、強度的に不利があり、その改善が要
望されている。However, since the bottom surface of the cavity of the P.7 cage is flat, the cross section of the corner is at a right angle, and most of the silver paste applied to this part will adhere only to the bottom surface of the semiconductor chip, which will result in poor strength. There are disadvantages, and improvements are desired.
第２図は、従来の半導体チップをパッケージに収納した
状態の断面図である。FIG. 2 is a sectional view of a conventional semiconductor chip housed in a package.
例えば、セラミックのパッケージ１があり、そのパッケ
ージにはリード２が配置され、パッケージ内部のキャビ
ティ部分に半導体チップ３が収納されていて、半導体チ
ップの底面部とパフケージのキャビテイ面４とは銀ペー
スト５によって接合されているが、双方を接合する際の
銀ペーストの熱処理温度は約２００℃程度である。For example, there is a ceramic package 1, in which leads 2 are arranged, a semiconductor chip 3 is housed in a cavity inside the package, and a bottom surface of the semiconductor chip and a cavity surface 4 of a puff cage are connected to each other by a silver paste 5. However, the heat treatment temperature of the silver paste when joining both is about 200°C.
又、半導体チップとリードとの接続はボンデングワイヤ
６によってなされている。Further, the semiconductor chip and the leads are connected by bonding wires 6.
本来、銀ペーストとシリコンを基板とする半導体チップ
との接着強度は比較的弱いため、接着強度を大きくする
ことが必要であるが、従来はパッケージのキャビティ底
面が平面であるために、キャビティコーナ７の形状はほ
ぼ直角であり、パッケージ１の側面７と半導体チップ２
との間隔ｄは０．５ ｍｍ程度であるが、接合に寄与す
る銀ペーストは半導体チップの底面と僅かに底面に近い
側面に被着している程度に躍定されている。Originally, the adhesive strength between silver paste and a semiconductor chip with a silicon substrate is relatively weak, so it is necessary to increase the adhesive strength. The shape is almost a right angle, and the side surface 7 of the package 1 and the semiconductor chip 2
The distance d between the semiconductor chip and the semiconductor chip is approximately 0.5 mm, but the silver paste that contributes to bonding is determined to be attached to the bottom surface of the semiconductor chip and the side surfaces slightly close to the bottom surface.
この対策として、例えばパッケージ１の側面と半導体チ
ップ２との間隔ｄを０．５ ｍｍ程度よりも小にして、
銀ペーストをその間隙に充填することが考えられるが、
実際には、パッケージに半導体チップを挿入する際に、
通常コレット治具と称する半導体チップを真空チャック
で吸引し、パッケージに配置する治具を操作して作業を
行うが、このコレット治具を操作するのに必要なスペー
スｄがあって、最小でｄ＝０．１〜０．２ｎ＋ｍが必要
であるので、それ以上に間隙を縮小することは不可能で
ある。As a countermeasure for this, for example, the distance d between the side surface of the package 1 and the semiconductor chip 2 is made smaller than about 0.5 mm.
It is possible to fill the gap with silver paste, but
In reality, when inserting a semiconductor chip into a package,
Normally, work is carried out by manipulating a jig called a collet jig, which suctions the semiconductor chip with a vacuum chuck and places it in the package.There is a space d required to operate this collet jig, and the minimum =0.1 to 0.2n+m is necessary, so it is impossible to reduce the gap further.
上記の楕成のパッケージでは、パッケージキャビティの
底面が平面であるために・パッケージキャビティと半導
体チップとの銀ペーストによる接着面積が小であること
が問題点であり、そのために半導体チップの接着力が弱
くなるという不具合を生ずる。In the above-mentioned oval package, since the bottom surface of the package cavity is flat, the problem is that the adhesive area between the package cavity and the semiconductor chip using the silver paste is small, which causes the adhesive strength of the semiconductor chip to decrease. This causes the problem of weakening.
本発明は、上記問題点を解消した半導体装置のパッケー
ジ構造を提供するもので、その手段は、半導体チップを
収納するパンケージのキャビィティのコーナに傾斜を設
け、銀ペーストによる半導体チップとキャビィティの壁
面との接着面積を大きくした半導体装置のパンケージに
よって達成できる。The present invention provides a package structure for a semiconductor device that solves the above-mentioned problems.The present invention provides a package structure for a semiconductor device that solves the above-mentioned problems. This can be achieved by using a semiconductor device pancage with a large adhesion area.
本発明は、パッケージキャビティと半導体チップとの銀
ペーストによる接着面積を大きくするために半導体チッ
プを収納するパフケージのキャビィティのコーナ部分に
傾斜を設け、銀ペーストを半導体チップが押圧すること
により盛り上がる銀ペーストによって半導体チップの側
面部分をも銀ペーストで接着するものである。In order to increase the adhesion area between the package cavity and the semiconductor chip using the silver paste, the corner part of the cavity of the puff cage that houses the semiconductor chip is sloped, and the silver paste rises when the semiconductor chip presses the silver paste. In this method, the side surfaces of the semiconductor chip are also bonded using silver paste.
第２図は、本発明の半導体チップをパッケージに収納し
た状態のパッケージコーナの主要断面図である。FIG. 2 is a main sectional view of a package corner in which the semiconductor chip of the present invention is housed in a package.
パッケージ１１があり、その内部のキャビティ部分に半
導体チップ１２が収納されて、半導体チップとパンケー
ジのキャビティ底面１３とが銀ペースト１４によって接
合されているが、本発明では銀ペーストの接着面積を大
きくするために、キャビティコーナ１５に傾斜を設け、
はぼ４５度の角度としである。There is a package 11, a semiconductor chip 12 is housed in a cavity inside the package, and the semiconductor chip and the bottom surface 13 of the cavity of the pancage are bonded by a silver paste 14. In the present invention, the adhesion area of the silver paste is increased. Therefore, the cavity corner 15 is sloped,
The angle is approximately 45 degrees.
従って、従来と同様に半導体チ・ノブをパッケージに挿
入して、銀ペーストにより接着する際に、銀ペーストは
半導体チップの押圧によって側面に押し出され、半導体
チップの底面は勿論であるが、半導体チップの側面部ま
で銀ペースト１６が被着し、半導体チップの接着面積が
増加する。Therefore, when a semiconductor chip knob is inserted into a package and bonded with silver paste as in the past, the silver paste is pushed out to the sides by the pressure of the semiconductor chip, and the bottom surface of the semiconductor chip as well as the bottom surface of the semiconductor chip are The silver paste 16 adheres to the side surfaces of the semiconductor chip, increasing the bonding area of the semiconductor chip.
実測によれば、従来の半導体チップの接着強度に比較し
て、本発明になる接着強度は、約１．５倍に増加するこ
とが判明し、品質向上に大きく寄与することになる。According to actual measurements, it has been found that the adhesive strength of the present invention is approximately 1.5 times greater than that of conventional semiconductor chips, which greatly contributes to quality improvement.
以上詳細に説明したように、本発明の半導体装置のパッ
ケージは、半導体チップの接着強度を増大して高品質の
半導体装置を供し得るという効果大なるものがある。As described above in detail, the semiconductor device package of the present invention has the great effect of increasing the adhesive strength of the semiconductor chip and providing a high quality semiconductor device.
第１図は本発明の半導体装置のパッケージの断面図、
第２図は従来の半導体装置のパッケージの断面図、
図において、
１１はパッケージ、 １２は半導体チップ、１３は
パフケージのキャビティ底面、
１４は銀ペースト、
１５はキャビティコーナ、１６は銀ペースト、をそれぞ
れ示す。FIG. 1 is a sectional view of a semiconductor device package according to the present invention, and FIG. 2 is a sectional view of a conventional semiconductor device package. 15 represents a cavity corner, and 16 represents a silver paste.
Claims (1)
ーナ部分に傾斜を設け、銀ペーストによる半導体チップ
とキャビイテイの底辺との接着面積を大きくしたことを
特徴とする半導体装置。A semiconductor device characterized in that a corner portion of a cavity of a package for storing a semiconductor chip is sloped to increase the bonding area between the semiconductor chip and the bottom of the cavity using silver paste.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59275351A JPS61150352A (en) | 1984-12-25 | 1984-12-25 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59275351A JPS61150352A (en) | 1984-12-25 | 1984-12-25 | semiconductor equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61150352A true JPS61150352A (en) | 1986-07-09 |
Family
ID=17554260
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59275351A Pending JPS61150352A (en) | 1984-12-25 | 1984-12-25 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61150352A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4926240A (en) * | 1989-03-28 | 1990-05-15 | Motorola, Inc. | Semiconductor package having recessed die cavity walls |
-
1984
- 1984-12-25 JP JP59275351A patent/JPS61150352A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4926240A (en) * | 1989-03-28 | 1990-05-15 | Motorola, Inc. | Semiconductor package having recessed die cavity walls |
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