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JPS61296743A - Chip carrier - Google Patents

Chip carrier

Info

Publication number
JPS61296743A
JPS61296743A JP60141044A JP14104485A JPS61296743A JP S61296743 A JPS61296743 A JP S61296743A JP 60141044 A JP60141044 A JP 60141044A JP 14104485 A JP14104485 A JP 14104485A JP S61296743 A JPS61296743 A JP S61296743A
Authority
JP
Japan
Prior art keywords
semiconductor element
metal base
cap
metal
seal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60141044A
Other languages
Japanese (ja)
Inventor
Shigenari Takami
茂成 高見
Jiro Hashizume
二郎 橋爪
Tatsuhiko Irie
達彦 入江
Hajime Sugiyama
肇 杉山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP60141044A priority Critical patent/JPS61296743A/en
Publication of JPS61296743A publication Critical patent/JPS61296743A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To provide reliable wet-proof sealing and to improve the radiation of heat by connecting the cap that coats a semiconductor element to a metal base by means of a hermetic seal without an intermittent insulative layer. CONSTITUTION:The seal of a semiconductor element 3 which is mounted on the circuit surface of a printed circuit substrate 1 with a metal base is harmetically connected with the skirt of a base cap 2 which is sealed by exposing a metal base from the insulative layer 10 around the semiconductor element 3 and covering the semiconductor element 3 on it. That is, the skirt section of the metal cap 2 is hermetically connected by utilizing the exposed section of the metal base 18 at the end surface of the metal base circuit substrate. The sealing material is solder, glass silver solder and glass resin.

Description

【発明の詳細な説明】 〔技術分野〕 本発明は半導素子のチップキャリアに関する。[Detailed description of the invention] 〔Technical field〕 The present invention relates to a chip carrier for semiconductor devices.

〔背景技術〕[Background technology]

従来のチップキャリアには、第５図乃至第３図に示す各
従来例の様に、セラミックベースまたはエポキシ樹脂ベ
ースのプリント回路基板（１）が用いられている。そし
て、その上に実装された半導体素子（３）の風封止方法
には第１図に示すように対土用枠（１８）と上蓋（１９
）を接着剤（１６）で半導体素子（３）を覆うようにプ
リント回路基板（１）に配置したもの、第３図の例のよ
うに、接着材（１６）によるキャンプ（２）の接着によ
る冠着、あるいは第２図の例のように、エポキシ樹脂等
の合成樹脂（１０）で、直接半導体素子を樹脂封止する
方法がとられている。Conventional chip carriers use ceramic-based or epoxy resin-based printed circuit boards (1), as in the conventional examples shown in FIGS. 5 to 3. The air sealing method for the semiconductor element (3) mounted thereon includes the anti-soil frame (18) and the top cover (19) as shown in Figure 1.
) is placed on the printed circuit board (1) so as to cover the semiconductor element (3) with adhesive (16), as shown in the example in Fig. 3, by adhering camp (2) with adhesive (16). A method of directly encapsulating the semiconductor element with a synthetic resin (10) such as epoxy resin is used, as shown in the example shown in FIG.

一方、チップキャリアの一つであるピングリッドアレイ
の回路基板には、主にセラミック基板が用いられておた
、その封止値は封止用キャップを用いガラスシールによ
り行われている。これによれば、封止の信組性は非常に
優れたものとなる。On the other hand, a ceramic substrate is mainly used as a circuit board of a pin grid array, which is one of the chip carriers, and its sealing is performed by using a glass seal using a sealing cap. According to this, the credit union property of sealing becomes extremely excellent.

しかし最近、半導体素子の放熱性、さらには′チップキ
ャリアとしてのコストの面から、金属ベースのプリント
回路基板をビングリッドアレイに用いることが検討され
ている。ところが、第１図及び第３図に示した従来例と
同じ構造で、金属ベースのプリント回路基板のピングリ
ントアレイを封止しようと第４図に示すように、上に、
回路面を形成するため金属ベース上に設けたｖ１３縁層
（１０）と金属ベース（１８）との接着部及び絶縁層（
１０）自体から湿気が侵入する。これは接着部や絶縁層
を形成するエポキシ樹脂等が吸湿性に富むこと等を理由
としている。半導体素子にとって湿気は悪く影響を与え
、半導体素子の性能の劣下にも及ぶため、このタイプの
ピングリッドアレイは封にかんして耐湿性に劣る欠点が
あった。However, recently, from the viewpoint of the heat dissipation of semiconductor elements and also the cost of chip carriers, the use of metal-based printed circuit boards for bin grid arrays has been considered. However, when trying to seal the pin print array of a metal-based printed circuit board with the same structure as the conventional example shown in FIGS. 1 and 3, as shown in FIG.
The adhesive part between the V13 edge layer (10) and the metal base (18) provided on the metal base to form a circuit surface and the insulating layer (
10) Moisture intrudes from itself. The reason for this is that the epoxy resin and the like that form the adhesive portion and the insulating layer are highly hygroscopic. Moisture has a negative effect on semiconductor devices, leading to deterioration in the performance of the semiconductor devices, so this type of pin grid array has the drawback of poor moisture resistance in terms of sealing.

〔発明の目的〕[Purpose of the invention]

本発明は、金属ベースの回路基板を用いたチップキャリ
アに実装する半導休業の封止に関して耐湿性を向上させ
ることを目的とする。An object of the present invention is to improve moisture resistance with respect to the sealing of a semiconductor chip mounted on a chip carrier using a metal-based circuit board.

〔発明の開示〕[Disclosure of the invention]

本発明は、金属ベースのプリント回路基板（１）の回路
面上に絶縁層（１０）を介して実装した半導体素子（３
）の封止を、半導体素子（３）のまわりの絶縁層（１０
）より金属ベースを露出させ、その部分に半導体素子（
３）にかぶせて封止する基キャップ（２）のスカート部
をハーメチッにより接合してなることを要旨とするもの
である。The present invention provides a semiconductor element (3) mounted on the circuit surface of a metal-based printed circuit board (1) via an insulating layer (10).
) is sealed with an insulating layer (10) around the semiconductor element (3).
) to expose the metal base, and place the semiconductor element (
3) The skirt portion of the base cap (2) which is placed over and sealed is hermetically joined.

以下、本発明の実施例を、第５図乃至第７図に示す実施
例に基づいて説明する。Embodiments of the present invention will be described below based on the embodiments shown in FIGS. 5 to 7.

まず第５図及び第６図において各々示すピングリフトア
レイの場合について説明する。First, the case of the pin lift array shown in FIGS. 5 and 6 will be explained.

上記の従来例どおり、金属ベース回路基１（１）上のダ
イボンド部（７）に半導体素子（ＩＣチップ）　（３）
をダイボンドし、ボンディングワイヤ（４）によりＩＣ
チップ（３）と回路基板（１）上の端子（８）とボンデ
ィングするまでの状態は従来のものとかわりがない、第
６図の例は、金属ベース回路基板１の端面の金属ベース
（１日）の露出部分を利用し、金属キャンプ２のスカー
ト部とのハーメチックシールによる接合を行う、（３）
はシール部である。ハーメチックシールのシール材は、
ハンダ、ガラス銀ろう及びガラス樹脂である。　第６図
の例では、金属ベース回路基板部（１）においてピン（
５）の外側の部分の絶縁層（１０）をキャップ（２）の
スカート部に対応するようにエツチング、機械研削等に
より取り除き金属ベース（１８）を露出させ、その露出
部分とキャップ２をハーメチックシールにて封止したも
のである。As in the conventional example above, a semiconductor element (IC chip) (3) is attached to the die bond part (7) on the metal base circuit board 1 (1).
die-bond and connect the IC with bonding wire (4).
The state until bonding between the chip (3) and the terminal (8) on the circuit board (1) is the same as in the conventional case. In the example shown in FIG. (3) Use the exposed part of the metal camp 2 to connect it with the skirt part of the metal camp 2 using a hermetic seal.
is the seal part. The hermetic seal material is
These are solder, glass silver solder, and glass resin. In the example shown in Fig. 6, the pin (
5) Remove the outer part of the insulating layer (10) by etching, mechanical grinding, etc. to correspond to the skirt part of the cap (2) to expose the metal base (18), and hermetically seal the exposed part and the cap 2. It is sealed in.

なお、上記実施例では、チップキャリアをビングリッド
アレイとしたが、それに限定されるものでなく、リード
レスチップキャリアとしてもよい。また第７図に示す実
施例のように、両面プリント回路基板（１）を使用した
ハイブリッドＩＣにも応用できる。この例では裏面側に
抵抗（１４）及びコンデンサ（１５）をランド（９）に
実装しているが、表面側の封止構造は上記二つの例と同
じである。表裏面の回路はスルホールを利用して接続さ
れている。In the above embodiment, the chip carrier is a bin grid array, but the present invention is not limited thereto, and a leadless chip carrier may be used. It can also be applied to a hybrid IC using a double-sided printed circuit board (1), as in the embodiment shown in FIG. In this example, a resistor (14) and a capacitor (15) are mounted on the land (9) on the back side, but the sealing structure on the front side is the same as in the above two examples. The circuits on the front and back sides are connected using through holes.

〔発明の効果〕。〔Effect of the invention〕.

本発明では、絶縁層を介さずにハーメチックシールによ
り半導体素子を被覆するキャンプを金属ベースに接合す
るので、半導体基素子はキャップにより外部と確実に遮
断され耐湿信鯨性の高い封止ができ、またさらに、金属
ベース基板を用いるため放熱性も良好なのである。In the present invention, since the camp covering the semiconductor element is bonded to the metal base by a hermetic seal without using an insulating layer, the semiconductor element is reliably isolated from the outside by the cap, and can be sealed with high moisture resistance. Furthermore, since a metal base substrate is used, heat dissipation is also good.

【図面の簡単な説明】[Brief explanation of drawings]

第１図乃至第４図は従来例の断面図、第５図乃至第７図
は各々この発明の一実施例を示す断面図である。 １・・・回路基板、２・・・封止用キャップ、３・・・
ＩＣチップ、４・・・ボンディングワイヤ、５・・・ピ
ン、６・・・スルーホール、７・・・ダイボンド部、８
・・・端子、９・・・ランド、ｌＯ・・・絶縁層、 １１・・・対土用樹脂、１２・・・接合部、工３・・・
ハーメチックシールによる接合部。1 to 4 are sectional views of a conventional example, and FIGS. 5 to 7 are sectional views each showing an embodiment of the present invention. 1... Circuit board, 2... Sealing cap, 3...
IC chip, 4... Bonding wire, 5... Pin, 6... Through hole, 7... Die bonding part, 8
...terminal, 9...land, lO...insulating layer, 11...resin for soil, 12...junction, work 3...
Joints with hermetic seals.

Claims (1)

【特許請求の範囲】[Claims] （１）、金属ベース（１８）のプリント回路基板（１）
の回路面上に絶縁層（１０）を介して実装した半導体素
子（３）の封止を、半導体素子（３）のまわりの絶縁物
（１２）より金属ベース（１８）を露出させ、その部分
に、半導体素子（３）にかぶせて封止するキャップ（２
）のスカート部をハーメチックシールにより接合して成
ることを特徴とするチップキャリア。(1), printed circuit board (1) with metal base (18)
The semiconductor element (3) mounted on the circuit surface of the semiconductor element (3) via the insulating layer (10) is sealed by exposing the metal base (18) from the insulator (12) around the semiconductor element (3). Then, a cap (2) is placed over the semiconductor element (3) to seal it.
) is formed by joining the skirt portions of the chips with a hermetic seal.
JP60141044A 1985-06-25 1985-06-25 Chip carrier Pending JPS61296743A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60141044A JPS61296743A (en) 1985-06-25 1985-06-25 Chip carrier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60141044A JPS61296743A (en) 1985-06-25 1985-06-25 Chip carrier

Publications (1)

Publication Number Publication Date
JPS61296743A true JPS61296743A (en) 1986-12-27

Family

ID=15282941

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60141044A Pending JPS61296743A (en) 1985-06-25 1985-06-25 Chip carrier

Country Status (1)

Country Link
JP (1) JPS61296743A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5093282A (en) * 1988-04-13 1992-03-03 Kabushiki Kaisha Toshiba Method of making a semiconductor device having lead pins and a metal shell
WO2014133838A1 (en) * 2013-02-28 2014-09-04 Cooper Technologies Company External moisture barrier package for circuit board electrical component

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5093282A (en) * 1988-04-13 1992-03-03 Kabushiki Kaisha Toshiba Method of making a semiconductor device having lead pins and a metal shell
WO2014133838A1 (en) * 2013-02-28 2014-09-04 Cooper Technologies Company External moisture barrier package for circuit board electrical component

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