JPS6114913B2 - - Google Patents
Info
- Publication number
- JPS6114913B2 JPS6114913B2 JP52154021A JP15402177A JPS6114913B2 JP S6114913 B2 JPS6114913 B2 JP S6114913B2 JP 52154021 A JP52154021 A JP 52154021A JP 15402177 A JP15402177 A JP 15402177A JP S6114913 B2 JPS6114913 B2 JP S6114913B2
- Authority
- JP
- Japan
- Prior art keywords
- solder
- layer
- solder layer
- spherical
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229910000679 solder Inorganic materials 0.000 claims description 44
- 238000000034 method Methods 0.000 claims description 12
- 230000004907 flux Effects 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 2
- 239000000853 adhesive Substances 0.000 claims 1
- 230000001070 adhesive effect Effects 0.000 claims 1
- 238000002844 melting Methods 0.000 claims 1
- 230000008018 melting Effects 0.000 claims 1
- 239000004020 conductor Substances 0.000 description 10
- 239000000758 substrate Substances 0.000 description 9
- 239000000919 ceramic Substances 0.000 description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
- B23K35/02—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape
- B23K35/0222—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape for use in soldering, brazing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
Landscapes
- Engineering & Computer Science (AREA)
- Mechanical Engineering (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Description
【発明の詳細な説明】
本発明は、半田層の形成方法に関し、特に形成
される半田層の厚さを制御する方法に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming a solder layer, and more particularly to a method for controlling the thickness of a formed solder layer.
従来から微少な電気的回路等、例えば厚膜集積
回路において、セラミツク等の絶縁基板上の導体
配線の上に回路素子を接続する方法として、導体
配線上に予め設けられた半田層の再溶融によつて
行なわれている。しかし、この半田層の形成は一
般に溶融した半田中へ浸漬するという方法で行な
われているため、均一な厚さの半田層を得ること
が難しく、半田層が薄くなりすぎると、接続強度
と電気的特性が得られず、又厚すぎると、再溶融
時に隣接した回路とシヨートするという欠点があ
る。 Conventionally, in minute electrical circuits, such as thick film integrated circuits, a method for connecting circuit elements onto conductor wiring on an insulating substrate such as ceramic has been used to remelt a solder layer previously provided on the conductor wiring. It is carried out by However, since this solder layer is generally formed by dipping it into molten solder, it is difficult to obtain a solder layer of uniform thickness, and if the solder layer becomes too thin, the connection strength and electrical In addition, if it is too thick, it has the disadvantage that it will shoot into adjacent circuits when it is remelted.
本発明は、従来の半田層形成方法の欠点を解決
した新しい方法であり、その特長は、半田層は均
一な球径をもつた球状半田の再溶融によつて作ら
れるため、厚さが均一であり、かつその厚さを球
状半田の径を変えることによつて容易に制御でき
るようにしたことにある。 The present invention is a new method that solves the shortcomings of conventional solder layer forming methods.The feature is that the solder layer has a uniform thickness because it is created by remelting spherical solder with a uniform diameter. and its thickness can be easily controlled by changing the diameter of the spherical solder.
以下、実施例につき、図面に従つて説明する。
第１図は、本発明による半田層形成方法の一実施
例を示すものである。同図において、１はセラミ
ツク等からなる絶縁基板であり、２は基板１上の
銀、パラジウム等の導体層であり、蒸着、焼成等
によつて基板１上に被着されている。この導体層
２の表面に薄い半田層を形成する場合には、導体
層２の表面にスクリーン法等を用いて、フラツク
ス層３をつくり、次に、フラツクス層３の粘着性
を利用して、比較的径の小さい球状半田４を導体
層２の表面に付着させる。そして、このようにし
て付着した球状半田４を基板１を熱板上に置く等
して溶融させると、第２図に示すごとく、薄い半
田層５が導体層２の表面に形成される。又、厚い
半田層を形成する場合には、第３図に示すごと
く、基板１上の導体層２の表面にフラツクス層３
をつくり、導体層２の表面に比較的径の大きい球
状半田４を付着させ、次に、球状半田４を熱して
溶融すれば、第４図に示すように、厚い半田層５
が形成される。 Examples will be described below with reference to the drawings.
FIG. 1 shows an embodiment of the solder layer forming method according to the present invention. In the figure, 1 is an insulating substrate made of ceramic or the like, and 2 is a conductive layer of silver, palladium, etc. on the substrate 1, which is deposited on the substrate 1 by vapor deposition, firing, or the like. When forming a thin solder layer on the surface of the conductor layer 2, a flux layer 3 is formed on the surface of the conductor layer 2 using a screen method or the like, and then, using the adhesiveness of the flux layer 3, A spherical solder 4 having a relatively small diameter is attached to the surface of the conductor layer 2. When the thus adhered spherical solder 4 is melted by placing the substrate 1 on a hot plate, etc., a thin solder layer 5 is formed on the surface of the conductor layer 2, as shown in FIG. In addition, when forming a thick solder layer, a flux layer 3 is placed on the surface of the conductor layer 2 on the substrate 1, as shown in FIG.
If a spherical solder 4 with a relatively large diameter is attached to the surface of the conductor layer 2, and then the spherical solder 4 is heated and melted, a thick solder layer 5 is formed as shown in FIG.
is formed.
たとえば、セラミツク基板上の銀焼付け導体層
表面に半田層を形成する時、直径１mm、重量で錫
60％、鉛40％の球状半田を用い、220℃で10秒加
熱すると約0.4〜0.5mmの半田層厚さとなり、直径
1.4mmの球状半田を用いると、約0.9〜1.0mmの厚さ
の半田層となつた。 For example, when forming a solder layer on the surface of a silver-baked conductor layer on a ceramic substrate, a tin layer with a diameter of 1 mm and a weight of
When using 60% lead and 40% lead spherical solder and heating it at 220℃ for 10 seconds, the solder layer thickness becomes approximately 0.4 to 0.5 mm, and the diameter
Using 1.4 mm spherical solder resulted in a solder layer with a thickness of approximately 0.9 to 1.0 mm.
以上の説明から明らかなように本発明の半田層
形成方法によれば、球状半田の径を変えるだけで
任意の半田層厚さを得られ、半田付け不良のな
い、きわめて安定した半田付けが実現できる。
又、従来の方法では、余分な所に半田層が形成さ
れないように半田レジストを施こしていたが、本
発明方法ではその必要がない。又、球状半田の径
を選ぶことにより同一基板上に異なつた厚さの半
田層も得られる。 As is clear from the above explanation, according to the solder layer forming method of the present invention, any solder layer thickness can be obtained by simply changing the diameter of the spherical solder, and extremely stable soldering without soldering defects is realized. can.
Furthermore, in the conventional method, a solder resist was applied to prevent the formation of a solder layer in unnecessary areas, but this is not necessary in the method of the present invention. Furthermore, by selecting the diameter of the spherical solder, solder layers of different thicknesses can be obtained on the same substrate.
第１図は、本発明の半田層形成方法の一実施例
における半田層形成前の要部断面図、第２図は同
実施例における半田層形成後の要部断面図、第３
図は本発明方法の実施例における半田層形成前の
要部断面図、第４図は第３図に示す実施例におけ
る半田層形成後の要部断面図である。
１…基板、２…導体層、３…フラツクス層、４
…球状半田、５…半田層。
FIG. 1 is a cross-sectional view of a main part before forming a solder layer in an embodiment of the solder layer forming method of the present invention, FIG. 2 is a cross-sectional view of a main part after forming a solder layer in the same embodiment, and FIG.
The figure is a sectional view of a main part before forming a solder layer in an embodiment of the method of the present invention, and FIG. 4 is a sectional view of a main part after forming a solder layer in the embodiment shown in FIG. DESCRIPTION OF SYMBOLS 1...Substrate, 2...Conductor layer, 3...Flux layer, 4
... Spherical solder, 5... Solder layer.
Claims (1)
フラツクスの粘着力によつて球状半田を付着させ
た後、加熱溶融して半田層を形成させ、前記球状
半田の径を調整することによつて、半田層の厚さ
を制御することを特徴とする半田層形成方法。1. After applying flux on the surface to be soldered and adhering spherical solder using the adhesive force of the flux, heating and melting it to form a solder layer, and adjusting the diameter of the spherical solder. , a solder layer forming method characterized by controlling the thickness of the solder layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15402177A JPS5485155A (en) | 1977-12-20 | 1977-12-20 | Forming method for solder layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15402177A JPS5485155A (en) | 1977-12-20 | 1977-12-20 | Forming method for solder layer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5485155A JPS5485155A (en) | 1979-07-06 |
| JPS6114913B2 true JPS6114913B2 (en) | 1986-04-21 |
Family
ID=15575164
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15402177A Granted JPS5485155A (en) | 1977-12-20 | 1977-12-20 | Forming method for solder layer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5485155A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998009328A1 (en) * | 1996-08-27 | 1998-03-05 | Nippon Steel Corporation | Method of partially plating electronic component board |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0263221A1 (en) * | 1986-10-08 | 1988-04-13 | International Business Machines Corporation | Method of forming solder bumps on metal contact pads of a substrate |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5193762A (en) * | 1975-02-14 | 1976-08-17 | Sogosetsuzokutaino seizohoho | |
| JPS51121772A (en) * | 1975-04-18 | 1976-10-25 | Hitachi Ltd | Method of soldering wiring |
-
1977
- 1977-12-20 JP JP15402177A patent/JPS5485155A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5193762A (en) * | 1975-02-14 | 1976-08-17 | Sogosetsuzokutaino seizohoho | |
| JPS51121772A (en) * | 1975-04-18 | 1976-10-25 | Hitachi Ltd | Method of soldering wiring |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998009328A1 (en) * | 1996-08-27 | 1998-03-05 | Nippon Steel Corporation | Method of partially plating electronic component board |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5485155A (en) | 1979-07-06 |
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