JPS60226156A - Hybrid ic - Google Patents
Hybrid icInfo
- Publication number
- JPS60226156A JPS60226156A JP8485184A JP8485184A JPS60226156A JP S60226156 A JPS60226156 A JP S60226156A JP 8485184 A JP8485184 A JP 8485184A JP 8485184 A JP8485184 A JP 8485184A JP S60226156 A JPS60226156 A JP S60226156A
- Authority
- JP
- Japan
- Prior art keywords
- wiring conductors
- wiring conductor
- internal wiring
- substrate
- silver
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 claims abstract description 53
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 238000013508 migration Methods 0.000 claims abstract description 14
- 230000005012 migration Effects 0.000 claims abstract description 14
- 239000007769 metal material Substances 0.000 claims abstract description 5
- 229910052709 silver Inorganic materials 0.000 abstract description 8
- 239000004332 silver Substances 0.000 abstract description 8
- SWELZOZIOHGSPA-UHFFFAOYSA-N palladium silver Chemical compound [Pd].[Ag] SWELZOZIOHGSPA-UHFFFAOYSA-N 0.000 abstract description 7
- 229910001252 Pd alloy Inorganic materials 0.000 abstract description 6
- 229910052751 metal Inorganic materials 0.000 abstract description 5
- 239000002184 metal Substances 0.000 abstract description 5
- 238000005476 soldering Methods 0.000 abstract description 5
- 238000000034 method Methods 0.000 abstract description 4
- 229910045601 alloy Inorganic materials 0.000 abstract description 2
- 239000000956 alloy Substances 0.000 abstract description 2
- 239000000463 material Substances 0.000 abstract 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 7
- 239000011521 glass Substances 0.000 description 4
- 238000007650 screen-printing Methods 0.000 description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/16—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of types provided for in two or more different subclasses of H10B, H10D, H10F, H10H, H10K or H10N, e.g. forming hybrid circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【発明の詳細な説明】
発明の分野
この発明は、ハイブリッドＩＣに関するもので、特に、
集積麿を上げるための改良に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention This invention relates to hybrid ICs, and in particular:
This relates to improvements to increase the amount of stock.
先行技術の説明
ハイブリッドＩＣにおいて、従来より行なわれている高
集積度のための手法として、
■ セラミックグリーンシート積層基板を用いる方法、
■ スルーホールを有する両面配線基板を用いる方法、
などが挙げられる。しかしながら、■の手法では、内部
配線を施した後にセラミックを焼結させる必要があるた
め、内部配線用金属には、融点の高いモリブデン、タン
グステン等を使用する必要がある。そのため、配線抵抗
が高いという欠点を有していた。また、■の手法では、
配線抵抗の低いたとえば銀を用いて配線導体を形成する
と、このような配線導体が空気に対して露出しているの
で、適宜の電子部品とのはんだ付は等において、導体に
マイグレーションが生じるので好ましくない。Description of Prior Art Conventionally used methods for achieving high integration in hybrid ICs include (1) using a ceramic green sheet laminated board, (2) using a double-sided wiring board with through holes, and the like. However, in the method (2), it is necessary to sinter the ceramic after forming the internal wiring, so it is necessary to use molybdenum, tungsten, etc., which have a high melting point, as the metal for the internal wiring. Therefore, it had a drawback of high wiring resistance. In addition, in the method of ■,
When wiring conductors are formed using silver, which has low wiring resistance, for example, such wiring conductors are exposed to the air, and migration occurs in the conductors when soldering with appropriate electronic components, so it is preferable. do not have.
そこで、このようなマイグレーションを防ぐため、睨在
、銀−パラジウム合金を用いることが主流となっている
。しかしながら、このような銀−パラジウム合金による
配線導体にも、やはり配線抵抗が高いという欠点があっ
た。Therefore, in order to prevent such migration, it has become mainstream to use silver-palladium alloys. However, such a wiring conductor made of a silver-palladium alloy also has the drawback of high wiring resistance.
発明の目的
それゆえに、この発明の目的は、配線抵抗が低く、かつ
耐マイグレーション性に優れるとともに、はんだ耐熱性
を満足する、ハイブリッドＩＣの特に基板側の構成を提
供することである。OBJECTS OF THE INVENTION Therefore, an object of the present invention is to provide a configuration of a hybrid IC, particularly on the substrate side, which has low wiring resistance, excellent migration resistance, and satisfies soldering heat resistance.
発明の構成
この発明は、簡単に言えば、厚膜磨を用いて擬似的に多
層構造とし、電子部品と接続されるべき表面に現われる
配ｗＡＳ体のみを耐マイグレーション性のある金属材料
から構成した、ハイブリッドＩＣである。Structure of the Invention To put it simply, this invention uses thick film polishing to create a pseudo multilayer structure, and only the distributed AS body that appears on the surface to be connected to electronic components is made of a migration-resistant metal material. , a hybrid IC.
より詳細には、ハイブリッドＩＣの基板の主面上の所定
の領域にまず内部配線導体が形成される。More specifically, an internal wiring conductor is first formed in a predetermined region on the main surface of the substrate of the hybrid IC.
この内部配線導体の表面の少なくとも一部を覆うとども
ｔこ内部配線導体から露出した基板の主面の少なく仁も
一部を覆うように絶縁層がたとえばスクリーン印刷によ
って形成される。この絶縁層には、内部配線導体の表面
に連通ずるスルーホールが形成されている。そして、絶
縁層の表面上に前記スルーホールを介して内部配線導体
に接触するように外部配線導体が形成される。この外部
配線導体は、電子部品と接続されるべき領域を提供する
ものである。この外部配線導体は、内部配線導体とは異
なる導電材料であって耐マイグレーション性のある金属
材料から構成される。An insulating layer is formed, for example, by screen printing, so as to cover at least a portion of the surface of the internal wiring conductor and at least a portion of the main surface of the substrate exposed from the internal wiring conductor. A through hole communicating with the surface of the internal wiring conductor is formed in this insulating layer. Then, an external wiring conductor is formed on the surface of the insulating layer so as to contact the internal wiring conductor via the through hole. This external wiring conductor provides an area to be connected to electronic components. The external wiring conductor is made of a conductive material different from that of the internal wiring conductor, and is made of a migration-resistant metal material.
発明の効果
この発明によれば、内部配線導体が絶縁層によって保護
されるので、この内部配線導体としては、耐マイグレー
ション性を考慮することなく、銀のようなＳ電率の高い
導体を使用することができる。Effects of the Invention According to this invention, since the internal wiring conductor is protected by the insulating layer, a conductor with high S conductivity such as silver can be used as the internal wiring conductor without considering migration resistance. be able to.
したがって、配線抵抗が問題となる配線は、すべて、内
部配線導体によって達成すればよい。また、マイグレー
ションが問題となる外部配線導体は、電子部品を接続す
るための最小の面積とし、しかもある程度配線抵抗を無
視しながら、耐マイグレーション性にのみ着目して金属
材料を選ぶことができるので、マイグレーションの問題
も有利に解決できる。さらに、基板が予め用意された状
態で、ここに絶縁層を形成することになる。したがって
、絶縁層としては、たとえば結晶化ガラスを用いる口と
により、比較的低温で絶縁層を定着させることができる
ので、その意味でも、内部配線導体として、融点の高い
金属を用いる必要がな（、銀などの高導電率の金属を用
いることが可能となる。Therefore, all wiring in which wiring resistance is a problem can be achieved using internal wiring conductors. In addition, for external wiring conductors where migration is a problem, the metal material can be selected by focusing only on migration resistance, while minimizing the area for connecting electronic components, and ignoring wiring resistance to some extent. Migration problems can also be solved advantageously. Furthermore, an insulating layer is formed on the substrate with the substrate prepared in advance. Therefore, since the insulating layer can be fixed at a relatively low temperature by using, for example, crystallized glass as the insulating layer, there is no need to use a metal with a high melting point as the internal wiring conductor. , it becomes possible to use metals with high conductivity such as silver.
実施例の説明
図面は、この発明の一実施例となるハイブリッドＩＣの
基板およびこの基板上に構成される各要素を断面図で示
したものである。The explanatory drawing of the embodiment is a cross-sectional view showing a substrate of a hybrid IC according to an embodiment of the present invention and each element configured on the substrate.
以下、製造方法を説明しながら、図面に示したｍ造を明
らかにする。Hereinafter, while explaining the manufacturing method, the structure shown in the drawings will be clarified.
まず、たとえばアルミナからなる基板１が用意される。First, a substrate 1 made of, for example, alumina is prepared.
次に、この基板１の一方主面上の所定の領域に内部Ｖ線
導体２が形成される一内部り一絢瑯体２としては、比抵
抗の低い金属、たとえば銀などが用いられる。そのよう
な銀のペーストは、スクリーン印刷により基板の主面上
の所定の領域に形成され、その後、焼成される。Next, a metal having a low specific resistance, such as silver, is used for the inner V-line conductor 2 formed in a predetermined region on one main surface of the substrate 1. Such a silver paste is formed on a predetermined area on the main surface of the substrate by screen printing, and then fired.
次に、内部配ｍ導体２の表面の少なくとも一部を覆うと
ともに内部配線導体２から露出した基板１の主面の少な
くとも一部を覆うように、絶縁層３が形成される。絶縁
層３としては、たとえば、結晶化ガラスを含むペースト
をスクリーン印刷し、その後、口れを焼成することによ
って、ガラスを結晶化させることによって形成されるこ
とができる。このような絶縁層３の厚みは、４０μ程度
である。絶縁層３として、結晶化ガラスを用いた場合、
８５０〜９００℃の温度で焼成されるため、前述のよう
に、内部配線導体２として銀を用いても、何ら問題は生
じない。絶縁層３には、内部配線導体２の表面に連通ず
るスルーホール４が適宜形成される。このスルーホール
４は、たとえば、０．３〜０．５ｍｍの径を有する円形
または四角形等の穴として形成される。Next, an insulating layer 3 is formed to cover at least a portion of the surface of the internal wiring conductor 2 and to cover at least a portion of the main surface of the substrate 1 exposed from the internal wiring conductor 2. The insulating layer 3 can be formed, for example, by screen printing a paste containing crystallized glass and then firing the edges to crystallize the glass. The thickness of such an insulating layer 3 is about 40 μm. When crystallized glass is used as the insulating layer 3,
Since it is fired at a temperature of 850 to 900°C, no problem occurs even if silver is used as the internal wiring conductor 2, as described above. A through hole 4 communicating with the surface of the internal wiring conductor 2 is formed in the insulating layer 3 as appropriate. The through hole 4 is formed as a circular or square hole having a diameter of 0.3 to 0.5 mm, for example.
次に、絶縁Ｒ３の表面の一部を覆うとともにスルーホー
ル４を介して内部配線導体２に接触するように外部配線
導体５が形成される。外部配線導体５は、表面に現われ
かつ適宜の電子部品６．７や抵抗体８のような素子と直
接接続されるものである。この外部配線導体５は、した
がって、耐マイグレーション性やはんだ耐熱性等の優れ
た銀−パラジウム合金などで構成されるのが好ましい。Next, an external wiring conductor 5 is formed to cover a part of the surface of the insulation R3 and to contact the internal wiring conductor 2 via the through hole 4. The external wiring conductor 5 appears on the surface and is directly connected to appropriate electronic components 6.7 and elements such as resistors 8. Therefore, the external wiring conductor 5 is preferably made of a silver-palladium alloy or the like having excellent migration resistance and soldering heat resistance.
銀−パラジウム合金を含むペーストが、スクリーン印刷
され、その後焼成されることによって、外部配線導体５
を形成することができる。なお、銀〜パラジウム合金と
しては、たとえば、パラジウム含有量２０〜３０ｗｔ％
を含む合金が用いられる。A paste containing a silver-palladium alloy is screen printed and then fired to form the external wiring conductor 5.
can be formed. Note that the silver-palladium alloy has a palladium content of 20 to 30 wt%, for example.
An alloy containing the following is used.
このようにして得られたハイブリッドＩＣの配線導体に
よれば、従来、銀−パラジウム（面積抵抗：約３０〜５
０ｍΩ／口）を使用していた配線の大部分を銀（面積抵
抗：約２〜３ｍΩ／口）に置換えられるので、大幅に配
線抵抗が下がり、かつ、それゆえに設計の自由度も増す
。According to the wiring conductor of the hybrid IC obtained in this way, silver-palladium (area resistance: about 30 to 5
Most of the wiring that used to be 0 mΩ/hole) can be replaced with silver (area resistance: about 2 to 3 mΩ/hole), so the wiring resistance is significantly reduced and the degree of freedom in design is also increased.
なお、内部配＃ｉ！導体は、スルーホールを有する絶縁
層を介して複数層に形成されてもよい。In addition, internal arrangement #i! The conductor may be formed in multiple layers with an insulating layer having through holes interposed therebetween.
図面は、この発明の一実施例となるハイブリッドＩＣの
基板１およびその上に形成される各要素を断面図で示し
たものである。
図において、１は基板、２は内部配線導体、３は絶縁層
、４はスルーホール、５は外部配線導体、６．７は電子
部品、８は抵抗体である。The drawing shows a cross-sectional view of a substrate 1 of a hybrid IC according to an embodiment of the present invention and each element formed thereon. In the figure, 1 is a substrate, 2 is an internal wiring conductor, 3 is an insulating layer, 4 is a through hole, 5 is an external wiring conductor, 6.7 is an electronic component, and 8 is a resistor.
Claims (1)
、複数個の素子が配置されたハイブリッドＩＣにおいて
、 前記基板の主面上の所定の領域に内部配線導体が形成さ
れ、 前記内部配線導体の表面の少なくとも一部を覆うととも
に前記内部配線導体から露出した前記基板の主面の少な
くとも一部を覆うように絶縁層が形成され、当該絶縁層
には、前記内部配線導体の表面に連通ずるスルーホール
が形成され、前記絶縁層の表面上に前記スルーホールを
介して前記内部配線導体に接触するように外部配線導体
が形成され、当該外部配線導体は、前記内部配線導体と
は異なる導電材料であって耐マイグレーション性のある
金属材料から構成されたことを特徴とする、ハイブリッ
ドＩＣ。[Claims] A hybrid IC in which a plurality of elements are arranged electrically connected to a wiring conductor formed on a substrate, wherein an internal wiring conductor is provided in a predetermined area on the main surface of the substrate. an insulating layer is formed to cover at least a part of the surface of the internal wiring conductor and to cover at least a part of the main surface of the substrate exposed from the internal wiring conductor; A through hole communicating with the surface of the wiring conductor is formed, an external wiring conductor is formed on the surface of the insulating layer so as to contact the internal wiring conductor via the through hole, and the external wiring conductor is connected to the internal wiring conductor. A hybrid IC characterized in that it is made of a migration-resistant metal material that is a conductive material different from a wiring conductor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8485184A JPS60226156A (en) | 1984-04-25 | 1984-04-25 | Hybrid ic |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8485184A JPS60226156A (en) | 1984-04-25 | 1984-04-25 | Hybrid ic |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60226156A true JPS60226156A (en) | 1985-11-11 |
Family
ID=13842299
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8485184A Pending JPS60226156A (en) | 1984-04-25 | 1984-04-25 | Hybrid ic |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60226156A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5757062A (en) * | 1993-12-16 | 1998-05-26 | Nec Corporation | Ceramic substrate for semiconductor device |
-
1984
- 1984-04-25 JP JP8485184A patent/JPS60226156A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5757062A (en) * | 1993-12-16 | 1998-05-26 | Nec Corporation | Ceramic substrate for semiconductor device |
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