JPS61113262A - Integrated circuit device - Google Patents

Abstract

PURPOSE:To contrive to eliminate the generation of failure such as short-circuit and disconnection due to recrystallizing in an integrated circuit device in the multilayer wiring structure by a method wherein the wiring width of the metal wiring layer is regulated in such a wiring width that the wiring sectional area thereof becomes 20mum<2> or less and the wiring width is split into a band shape or a lattice type. CONSTITUTION:When the wiring width of the metal wiring layer is regulated in such a way that the wiring sectional area thereof becomes 20mum<2> or less, it follows that the generation of a hillock can be prevented. This nature is positively applied and when the wiring width of the first metal wiring layer located at the lower layer is splitted into a lattice type or a band shape in such a way that the wiring sectional area thereof becomes 20mum<2> or less at a region of the first metal wiring layer, where the second metal wiring layer located at the upper layer or the metal wiring layer located at the layer lower than the second metal wiring layer superposes on the first metal wiring layer located at the lower layer is splitted into a lattice type or a band shape in such a way that the wiring sectional area thereof becomes 20mum<2> or less at a region of the first metal wiring layer, where the second metal wiring layer located at the upper layer or the metal wiring layer located at the layer lower than the second metal wiring layer superposes on the first metal wiring layer located at the lower layer, the generation of a hillock, which is generated by recrystallizing, can be suppressed.

Description

[Detailed Description of the Invention] Industrial Application Fields In recent years, as semiconductor integrated circuits have become increasingly highly integrated, there has been an increase in not only two-dimensional high density but also three-dimensional high density, that is, multilayer wiring. It is being done. .

Conventional technology At present, polycrystalline silicon layers, aluminum layers, etc. are often used in multilayer wiring, but multilayers of up to 2 or 3 layers in the case of polycrystalline silicon layers and 2 layers in the case of aluminum layers are used. in a practical situation. In addition, silicide and polycide, which are intended to lower the resistance of polycrystalline silicon, have been put into practical use to some extent, but in terms of lowering the resistance of interconnects, it is clear that metal interconnects, mainly aluminum interconnects, are overwhelmingly used. It's advantageous.

Problems to be Solved by the Invention However, recrystallization of the metal in the metal wiring layer is promoted by heat treatment after the wiring layer has been resistant to adhesion. If there is only one metal wiring layer on the top layer, slight recrystallization will not induce electrical failure, but if there are two or more metal wiring layers, recrystallization of the lower metal wiring will occur. This causes a short circuit with the upper metal wiring layer. Figure 3 shows the cross-sectional structure in this state, where 1 is the wiring in the lower layer (first layer), 2 is the interlayer insulating layer, 3 is the wiring in the upper layer (second layer), and 4 is the recrystallized wiring. This is a representation of the lower hillock that occurred in the area. Although this is a fatal flaw in integrated circuit formation, the present invention provides a means to easily solve this problem.

The only way to solve the problem is to recrystallize the metal wiring layer by heat treatment after adhesion.
Experience has shown that the wider the width of the metal wiring layer, the higher the probability of this occurring. In the experimental example, the film thickness was 1 with a wiring width of 50 microns.
In micron aluminum wiring, so-called hillocks due to recrystallization were observed at a rate of approximately one spot per square micron of the SOO, but none were detected in wiring with a line width of 20 microns. The film thickness of the aluminum wiring layer at this time was 1 micron, but it can be easily inferred that as the film thickness increases, the maximum permissible line width that can suppress the occurrence of hillocks will decrease.

According to the present invention, hillocks can be prevented by regulating the wiring width so that the cross-sectional area of the wiring is 20 square microns or less. By actively applying this property, in the region where the first metal wiring layer located in the lower layer and the second or subsequent metal wiring layer located in the upper layer overlap, the first metal wiring layer located in the lower layer The wiring cross-sectional area is 20
It is possible to prevent the formation of hillocks due to recrystallization by dividing it into lattice or band shapes so that the size is less than square micrometers. Here, if the first metal wiring layer is wired by a single wire having the minimum dimension width, no matter how much the metal wiring layer is used, the electrical resistance cannot be ignored if it is used for power supply wiring or the like.

In this case, it is necessary to use a wider wiring layer. Here, if an attempt is made to make the wiring width as necessary and sufficient as described above, the problem arises that hillocks are likely to occur due to recrystallization.

Embodiment Next, an embodiment of the present invention is shown in FIGS. 1 and 2. FIG. 1 shows an example in which the wide lower wiring layer 5 is divided into strips at the location where it overlaps with the upper wiring layer 6.
The figure shows an example in which the lower wiring T is divided into a lattice pattern, and the upper wiring layer 8 is formed thereon. In addition to this example,
Needless to say, in order to satisfy the above purpose, the first wiring layer may be hollowed out in a diamond shape or a circular shape.

Effects of the Invention According to the present invention, a metal wiring layer is divided into wiring widths with a cross-sectional area of 20 μm or less and formed into strips or lattice shapes, thereby eliminating defects such as short circuits and disconnections due to recrystallization in a multilayer wiring structure. be able to.

[Brief explanation of the drawing]

FIGS. 1 and 2 are plan views of essential parts of each embodiment of the present invention, and FIG. 3 is a sectional view of essential parts of a conventional apparatus. 5, Completed... Lower layer (1st layer) wiring, 6, 8...
...Upper layer (second layer) wiring.

Claims (1)

[Claims] In an integrated circuit having two or more metal wiring layers, a first metal wiring in a lower layer and a second or subsequent metal wiring in a layer above the first metal wiring layer via an insulating layer. The integrated circuit device is characterized in that the first metal wiring is divided and wired in a band shape or a lattice shape with a wiring width such that the cross-sectional area of the metal wiring layer is 20 square microns or less in a region where the metal wiring layers overlap.