JPS61102819A - 2/3 frequency divider - Google Patents

Abstract

PURPOSE:To divide easily a reference clock of 50% duty by 2/3 and 1/3 by constituting such that the clock signal of the reference clock divided by 2/3 and that of the reference clock divided by 2/3 can be obtained from the 1st 1/2 frequency divider circuit and the 2nd 1/2 frequency divider circuit, respective ly. CONSTITUTION:A data selector 1 selects a signal impressed to an input terminal A. The 1st FF2 catches the 1st and next rises of an output Y, and its output Q1 goes to a high (-Q1). The 2nd FF3 detects the rise of the signal -Q1 and sets an output Q2 to a high (-Q2). Afterward, the data selector 1 selects and outputs a clock given to an input terminal B. After the FF1 acts in such a way, it raises the -Q1. After repeating the same action, the signal obtained by dividing the clock by 2/3 can be obtained from an output terminal out 1. The signal obtained by dividing the clock by 1/3 can be obtained from an output terminal out 2.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a frequency dividing circuit that performs frequency division by 2/3 using a 50% duty clock as an input target.

(Prior art) Dividing the reference frequency by 1/2 can be easily achieved with a single flip-flop, and if this is combined with a counter,
1/n (n-2, 3, 4, . . . ) frequency division can also be obtained surprisingly easily.

(Problems to be Solved by the Invention) However, a/b frequency division other than 1/n usually requires a complicated and expensive configuration. In particular, there was no simple structure for 2/3 frequency division, which is the subject here.

In view of these points, the object of the present invention is to reduce the duty to 50%.
An object of the present invention is to provide a frequency dividing circuit having a simple configuration that divides the frequency of a clock signal by 2/3.

(Means for solving the problem) In order to achieve such an object, the present invention provides a data selector that selectively selects either a reference clock with a duty of 50% or a clock obtained by inverting the phase of this clock. , a first 1/2 frequency divider that divides the output signal of this data selector by 1/2, and a first 1/2 frequency divider that divides the output signal of this first 1/2 frequency divider by 1/2 to control the data selector. The second 172 frequency divider circuit for obtaining the signal is broken down, and the first 1i
The clock signal obtained by dividing the reference clock by 2i3 is obtained from the 2 frequency divider circuit, and the clock signal obtained by dividing the reference clock by 2i3 is obtained from the second 1i2 frequency divider circuit. .

(Example) The present invention will be described in detail below using the drawings. FIG. 1 is a block diagram of main parts showing an embodiment of a 2i3 frequency divider circuit according to the present invention. In the figure, 1 is a data selector that selectively selects and outputs signals applied to input terminals Δ and B. The signal applied to the input terminal A is a reference clock having a frequency f and a duty of 50%. The clock is applied to the input terminal B via the inverter 4.

Reference numeral 2 designates a first 1i2 frequency divider circuit, for example, a flip-flop (hereinafter referred to as FF) is used. FF2 receives the output clock from the output terminal Y of data selector 1 and converts it to 1.
Divide by i2. The output Q1 is led to the output terminal out1, and the output Q1 is led to the second 1i2 frequency divider circuit 3.

For example, an FF is used as the second 1i2 frequency divider circuit 3.
Divide the frequency of the F2 extended positive output signal by 172.

The Q2 output of this FF3 is given to the output terminal our'a and the data selector 1. The data selector 1 selects one of the input signals using this signal (select signal).

The operation in such a configuration will now be described with reference to the time chart in FIG. In the initial state, when the output Q2 of FF3 is in a low state as shown in FIG.
Select (a) in the figure, and the output Y will be as shown in (d) in Figure 2.

The first FF2 catches the first rising edge and the next rising edge of this signal, and its Q1 output becomes High as shown in FIG. 2 (E). The Q1 output is an inverted signal of the Q1 signal, as shown in (C) of the same figure, and the second FF3 detects the rising edge of this Q1 signal and converts the output Q2 to l as shown in (C) of the same figure. -1-1i.

From this point on, the data selector 1 selects and outputs the clock (FIG. 2 (b)) applied to the 8 input terminals.

The FFI starts up its 01 again through the same operation as above. As a result, the select signal becomes 1ow, and from that point on, the data selector 1 again selects the clock at the input terminal and outputs Y.

The same operation is repeated below. When performing such an operation, the lock obtained from the output terminal 00 is the first F.
This is the 01 output of F2, and as is clear from FIG. 2, it is the clock divided by 2i3. Also output terminal out2
The clock obtained is the 02 output of the second FF3, which is obtained by dividing the clock by 1i3.

Note that when Q2 is High in the initial state, the signal at the 8 input terminals is selected first and becomes the Y output, and the same outputs as above are obtained from the output terminals 0utl and out2.

(Effects of the Invention) As explained above, according to the present invention, a reference clock with a duty of 50% can be easily converted to 2i with a simple circuit configuration.
The frequency can be divided into 3 and 1i3, which has great practical effects.

For example, in a system using a microprocessor, 6 MH for the CPU of the microprocessor
4 MHz, which was previously difficult to obtain from the Z clock.
When simultaneously obtaining clock signals of 2 MHz or 2 MHz, the use of the frequency divider circuit of the present invention has the advantage that these clocks can be easily obtained without preparing a new lock generator.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a main part configuration diagram showing an embodiment of a frequency dividing circuit according to the present invention, and FIG. 2 is a time chart for explaining the operation. 1...Data selector, 2...First FF, 3...
-Second FF, 4...inverter.

Claims (1)

[Claims] A data selector that selectively selects either a reference clock with a duty of 50% or a clock obtained by inverting the phase of this clock, and an output signal of this data selector that is
A first 1/2 frequency dividing circuit that divides the frequency by 2, and this first 1/2
A second 1/2 frequency divider circuit is provided which divides the output signal of the frequency divider circuit into 1/2 to obtain a signal for controlling the data selector, and the first 1/2 frequency divider circuit outputs the reference clock signal. 2/3
A 2/3 frequency divider circuit configured to obtain a frequency-divided clock signal, and to obtain a 2/3 frequency-divided clock signal of the reference clock from the second 1/2 frequency divider circuit.