JPS6312424B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to an FSK signal generation circuit.

Conventionally, _this type _of FSK signal generation circuit, as shown in FIG. In this circuit, the output is switched by a switch 104 according to a control signal from the switch 101. In this case, if crystals are used for both oscillators, the oscillation frequency can be made accurately, but there is a drawback that a phase jump occurs at the switching point, which causes jitter when detected.

FIG. 2 is a diagram showing another conventional example, in which a V/F converter (voltage-frequency converter) 201 is used as an oscillator. In this case, unlike the method shown in FIG. 1, a phase jump does not occur, but there is a drawback that it is difficult to accurately match the output of the oscillator.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to eliminate the drawbacks of the prior art and to
It is an object of the present invention to provide an FSK signal generation circuit having a simple configuration, no phase jump, and accurate frequency.

According to the present invention, accurate PCM without phase jump is achieved using ROM (Read Only Memory).
An FSK signal generation circuit that generates an FSK signal can be obtained by generating an FSK signal and further performing D/A.

Next, the present invention will be explained in detail with reference to the drawings showing one embodiment of the present invention. FIG. 3 is a diagram showing an embodiment of the present invention, in which clocks CL from terminal 1,
An address counter 302 receives transmission data D from terminal 2 and delayed transmission data D' which is delayed by one data period from the transmission data from terminal 2 in a delay circuit 301, and generates four types of address data; PCM data representing _L according to PCM data representing change from _L to _H
data, PCM data representing _H or _H to _L
a ROM 303 that outputs one piece of PCM data representing a change in for one data period; a D/A converter 304 that converts the PCM data from the ROM 303 into a PAM signal using a clock CL from terminal 1;
It is composed of a bandpass filter 305 that converts the PAM signal from the D/A converter 304 into an analog signal. In the FSK signal, _{the L} state _{is L.}
The state changing from to _H , the state of _H , and from _H to _L
There are four states that change, but the ROM 303 stores PCM data of the above four states in advance. The selection of these four data is delayed transmission data that is delayed transmission data D by one data period.
A change from D′ to data D, that is, data D,
This is done by a combination of D′.

FIG. 4 is a diagram showing the correspondence between the data stored in the ROM 303 shown in FIG. 3 and address data. PCM data representing _L during 1 data period T ₁ , from _L during 1 data period T ₂
PCM data representing changes in _H , 1 data period T ₃
During one data period T4, PCM data representing _H is shown, and during one data period _T4, PCM data representing a change from _H to _L is shown. Next, to explain the addresses corresponding to each 1 data period, 1 data period
The address data corresponding to T ₁ has a start address of A ₀ and an end address of A ₀₁ . Similarly, for period T ₂ , the start address is
A ₁ , and the end address is A ₁₁ , for period T ₃ the start address is A ₂ , and the end address is A ₂₁ and for period T ₄ the start address is
A ₃ and the end address is A ₃₁ .

Therefore, in the address counter 301, the address data is changed from A ₀ to A ₀₁ , A ₁ to A ₁₁ , A ₂ to A ₂₁ , and A ₃ to A ₃₁ by the combination of the transmission data D and the delayed transmission data D'. Made to change. For example, since one data period is the same, the data DD' is used as a control signal for the load data of the address counter, so that the count amounts loaded first are A ₀ , A ₁ , A ₂ , and A _{3 ,} respectively. Alternatively, four address counters that change the address in the four ways described above may be provided, and only one of the outputs may be selected by data DD'.

Figure 5 shows transmission data D and delayed transmission data.
This is a diagram showing the relationship between D', data stored in the ROM 303, and the start address _.
If you send out _L again this time, data
DD' becomes "00" and the start address is _A0 . Similarly, data when _L last time and _H this time
DD′ is “10”, start address A ₁ , previous _H , current _H , data DD′ is “11”, start address A ₂ , and previous _H , current _L , data DD′ is “01” start address A ₃ It is. In Fig. 5, the transmission data DD' is set to the logical value "0" or "1".
However, it is actually an electrical signal whose level value differs depending on the logical value. Here, the frequency of the clock CL is selected to be more than twice the frequency of the transmitted data. In addition, Fig. 5 shows the frequency change period (T ₂ in Fig. 3,
The frequency change of T ₄ ) is changed according to a sine wave curve.

As described above, the FSK signal generation circuit of the present invention can digitally process everything up to the input of the bandpass filter, so there is no need for adjustment, and the clock CL
If a crystal oscillator is used as the oscillator, the frequency accuracy of the FSK signal can also be included in the accuracy of the crystal oscillator. Furthermore, since the phases of the signals at the fixed frequency region (T ₁ , T ₃ in FIG. 3) and the beginning and end of the frequency changing region of the PCM data stored in the ROM are matched, no phase jump occurs at the frequency changing point. Furthermore, the change curve of the frequency change region can be arbitrarily selected, and if this is made into a sine wave curve, the band used by the output FSK signal can be minimized.

[Brief explanation of the drawing]

1 and 2 are diagrams showing the configuration of a conventional FSK signal generation circuit, FIG. 3 is a diagram showing an embodiment of the present invention, and FIG. 4 is a diagram showing the data and addresses stored in the ROM in FIG. 3. Figure 5 is a diagram showing the relationship between transmission data D and delayed transmission data in Figure 3.
A diagram showing the relationship between D', data stored in ROM, and the start address of the address register. In the figure, 101... _H oscillator, 102...
_L oscillator, 104...Switching circuit, 201...V-
F converter, 301...delay circuit, 302...
Address counter, 303...ROM, 304...
...D/A converter, 305...filter.

Claims (1)

[Claims] 1. A read that stores two data with different frequencies according to two types of logical values and data indicating a change between the two frequencies as PCM data, and makes each of the plurality of data correspond to different addresses. an address counter that receives transmission data consisting of a combination of two types of logical values and outputs different address data depending on the logical value of the transmission data and a change in the logical value, and sends it to the read-only memory;
An FSK signal generation circuit comprising: a D/A converter that converts PCM data from the read-only memory into an analog signal.