JP2679471B2 - Clock switching circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock switching circuit for selecting and outputting one of a plurality of clocks according to a switching signal applied from the outside.

[0002]

2. Description of the Related Art A conventional clock switching circuit is shown in FIG.
As shown in (1), the clock "0" and the clock "1" to be selected are input to the selector 1, and a switching signal from the outside is directly input to the selector 1 for switching control.

[0003]

In this conventional clock switching circuit, when there is a phase difference as shown in the time chart of FIG. 3B between the clock "0" and the clock "1" for switching. The output clock shown in the time chart of FIG. 3B is output depending on the timing of inputting the switching signal. Therefore, when the read counter that determines the read address of the elastic memory is incremented at the rising edge of this output clock, the rising portion occurs in a short cycle in the phase before and after switching, so only the read counter There is a problem in that the data is counted up and data is lost in the read data, resulting in an error.

An object of the present invention is to switch clocks without interruption even if there is a phase difference between clocks "0" and "1" for switching without causing a memory read data error. Is to

[0005]

In order to achieve the above object, the present invention provides a selector for selecting and outputting one of a plurality of clocks according to a switching control signal, and a clock selected by the selector. A flip-flop that inputs a monostable multivibrator and a switching signal to one input end, adds the output of the monostable multivibrator to the other input end via an inverter, and outputs a switching control signal from the output end.
It has a flop.

[0006]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing a first embodiment of the present invention. FIG. 1A shows a block diagram of a first embodiment of the present invention. FIG. 1B is a diagram showing a time chart of the first embodiment of the present invention. In FIG. 1, in the selector 1, which selects the clock “0” when the switching signal is at the low level and selects the clock “1” when the switching signal is at the high level, first selects the clock “0”. The output clock is input to the monostable multivibrator 2. The waveform 3 output from the monostable multivibrator 2 is a pulse of width T triggered by the rising edge of the clock "0".

Next, the switching signal input from the outside is t _0.
At the time of, it is assumed that the level has changed from the low level to the high level. This switching signal is input to the flip-flop 5,
The output of the flip-flop 5 is used as the switching control signal 6 of the selector. However, the switching control signal 6 of the selector 1 is output at the falling edge of the pulse of the width T output from the monostable multivibrator 2 by the inverter 4. Since only this changes, the selector 1 is switched at time t ₁ . Then, as can be seen from FIG. 1B, the output clock is switched without interruption, and the read data can be normally read from the elastic memory as the read counter counts up.

FIG. 2 is a diagram showing a second embodiment of the present invention. The second embodiment uses a changing point delay circuit 7 instead of the monostable multivibrator 2 and the inverter 4 of the first embodiment, and operates in the same manner as the first reference example.

[0010]

As described above, according to the present invention, by delaying the switching control signal for switching the selector with respect to the switching signal, it is not necessary to adjust the phase relationship of the clocks before and after the switching of the switching signal, and the memory read data can be read. The effect that clocks can be switched without interruption without generating an error is obtained.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing a second embodiment of the present invention.

FIG. 3 is a diagram showing a block diagram and a time chart of a conventional clock switching circuit.

[Explanation of symbols]

 1 selector 2 monostable multivibrator 3 waveform output from monostable multivibrator 4 inverter 5 flip-flop 6 switching control signal 7 change point delay circuit

Claims (1)

(57) [Claims] 1. A selector for selecting and outputting one of a plurality of clocks according to a switching control signal, a monostable multivibrator for inputting the clock selected by the selector, and a switching signal for one input end. In addition, a clock switching circuit characterized in that a flip-flop for applying the output of the monostable multivibrator to the other input terminal via an inverter and outputting a switching control signal from the output terminal.