JPH05199088A - Delay circuit - Google Patents

Abstract

PURPOSE:To attain an accurate delay time by delaying a clock signal and an input signal with variable delay means 1, 2 and controlling a delay time of control signal means 1, 2 generated in response to the logic processing of the clock signal and the result of phase comparison of both the delayed signal. CONSTITUTION:A clock signal(CLK) and an input signal(IN) are delayed by 1st and 2nd delay circuits(DLY) 1, 2 whose delay time is changed by a control signal. A phase comparator circuit PHC compares the phase of the signal resulting from the CLK subject to logic processing at an inverter circuit INV and the phase of the signal delayed by the DLY 1 and generates a control signal depending on the result of comparison. The control signal is given to the DLY 1, 2 by a charge pump circuit CHP and an LPF as a voltage signal to control the delay. Thus, a change in the delay due to a power supply voltage and temperature or the like is prevented and a stable accurate delay is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay circuit, and more particularly to a delay circuit suitable for use in an integrated circuit composed of MOS-FET or the like.

[0002]

2. Description of the Related Art Generally, two delay circuits in a digital circuit are known: a method of arranging several stages of inverter circuits to delay a signal and a method of using a flip-flop to delay a signal in synchronization with a clock. There is. Then, for example, in the former method, in order to obtain a large delay amount with a small number of inverter circuit stages, a delay circuit using a resistor and a capacitor may be further combined.

FIG. 3 is a circuit diagram of such a conventional delay circuit device. As shown in FIG. 3, the signal input from the input terminal IN is input to the first inverter circuit INV1. The output of the first inverter circuit INV1 is delayed through an integration system having a large time constant by the resistor R and the capacitor C, and is given to the second inverter circuit INV2. Then, the obtained delay signal is derived from the output terminal OUT to the outside.

That is, the signal input from the input terminal IN is first delayed by the first inverter circuit INV1. Further, the time constant circuit composed of the resistor R and the capacitor C is greatly delayed. Next second inverter circuit IN
Waveform shaping and further signal delay at V2, output terminal OUT
Is output to.

However, in the configuration of FIG. 3, most of the delay amount of the signal is obtained from the time-setting circuit including the resistor R and the capacitor C. Therefore, the amount of signal delay is greatly affected by the characteristics of these elements. Furthermore, there is also a problem that variations in delay amount due to power supply voltage and temperature cannot be ignored.

On the other hand, conventionally, a delay circuit as shown in FIG. 4 has also been proposed. In FIG. 4, the flip-flops FF1 to FFn operate with the clock input from the clock signal terminal CLK. The inputs and outputs of these flip-flops are connected in series. Then, the signal from the input terminal IN is the flip-flop FF1.
Input to the output terminal OUT through the flip-flops FF2 to FFn.

In the above structure, the input terminal IN
The input signal from is held in the flip-flop FF1 based on the clock from the clock signal terminal CLK.
It is transferred to the flip-flop FF2 by the next clock. Further, intermediate flip-flops FF3, FF4, ...
Is transferred to the flip-flop FFn via the output terminal OUT and output from the output terminal OUT.

According to the above-mentioned structure, the delay time until the output signal from the flip-flop FF1 is delayed and output from the flip-flop FFn is accurately defined by the clock input to the clock signal terminal CLK. be able to. However, the time until the input signal from the input terminal IN is taken into the flip-flop FF1 is determined by the phase relationship between the input signal and the clock. Therefore, there is a problem that the delay time cannot be managed accurately.

[0009]

Since the conventional delay circuit device is constructed as described above, the delay time depends on the characteristics of the elements used, the power supply voltage, the temperature, the phase of the clock, and the like. There is a problem. There is also a problem that once the signal delay amount is determined, it is not easy to change it. Therefore, there is a demand for the development of a delay circuit that can accurately manage the delay time.

The present invention has been made in view of the above,
An object of the invention is to obtain a delay circuit whose delay time is accurate and whose delay time can be changed.

[0011]

The first delay circuit of the present invention is capable of changing the delay time according to the input control signal and delaying the input clock signal by the delay time to output the first delay circuit. Means, second delay means capable of changing a delay time by inputting the control signal, delaying the input signal by the delay time and outputting the delayed signal, phase of a signal obtained by logically processing the clock signal, and the first delay means. The phase of the delayed clock signal output from the delay means is compared, a phase control signal corresponding to the comparison result is generated, and the control signals are simultaneously applied to the first delay means and the second delay means. And a phase comparison means added as.

A second delay circuit of the present invention is the first circuit according to the first circuit, wherein the first delay means is a series connection of n first delay units, and each of the first delay units is provided. The control signal is added to each of them, and the second delay means is a series connection of m second delay units of the same configuration as the first delay unit, and each of the second delay units is connected in series. The control signal is added to each of them, and each of the second delay units is configured to have an output end for delaying and outputting the input signal.

[0013]

The first delay means delays the input clock signal and outputs it. The phase comparison means compares the phase of the clock signal with a signal obtained by logically processing the clock signal. A phase control signal corresponding to the phase error is generated. This is given to the first delay means, and the delay time of the first delay means is controlled to the time defined by the clock signal. At the same time, by applying the phase control signal to the second delay means as a control signal, the delay time of the second delay means is kept constant.

[0014]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit configuration diagram of a delay circuit according to an embodiment of the present invention. In FIG. 1, the first delay circuit DL
Y1 is basically composed of an inverter circuit, a resistor, and a capacitor. A clock is input to these clock signal terminals CLK, which is delayed for a predetermined time and given to the phase comparison circuit PHC. The first delay circuit DLY
The delay amount of the signal by 1 is set to be controllable by the control voltage. On the other hand, the clock given to the clock signal terminal CLK is given to the other input of the phase comparison circuit PHC via the inverter circuit INV. The clock from the inverter circuit INV is compared in phase with the clock delayed by the first delay circuit DLY1. The phase difference is fed back to the first delay circuit DLY1 as a voltage signal through the charge pump circuit CHP and the low pass filter circuit LPF, and is also given to the second delay circuit DLY2. Now, the first delay circuit D that receives the voltage signal corresponding to the phase difference from the low-pass filter circuit LPF
LY1 is controlled in delay amount, and is defined as a delay amount such that the total delay amount becomes a half cycle of the clock. In this case, the output voltage signal from the low pass filter circuit LPF is also given to the second delay circuit DLY2. As a result, the second delay circuit DLY2 delays the signal from the input terminal IN by the delay amount corresponding to the voltage signal from the low-pass filter circuit LPF and sends it to the output terminal OUT.

The operation of the above arrangement will be described below.

The signal input from the input terminal IN is the second
Delay circuit DLY2 delays its output terminal OU
It is output to T. The delay amount of the second delay circuit DLY2 is
This depends on the output of the low-pass filter circuit LPF given as a voltage signal. On the other hand, the clock input to the clock signal terminal CLK is directly input to the phase comparison circuit PHC through the first delay circuit DLY1. Further, the input clock is the inverter circuit IN
The signal inverted by V is given to the other input of the phase comparison circuit PHC. Therefore, the first delay circuit DLY1
In the case where the delay amount is equal to the half cycle of the clock, the phase difference between the two inputs to the comparison circuit PHC becomes zero. The phase difference between the two inputs detected by the phase comparison circuit PCH is transferred from the charge pump circuit CHP to the low pass filter circuit LPF.
Is converted into a voltage signal corresponding to the phase difference via
Is fed back to the delay circuit DLY1. As a result, the delay amount of the first delay circuit DLY1 is controlled to the half cycle of the clock. Now, the control voltage obtained here is a voltage that accurately controls the delay amount of the first delay circuit DLY1 to the half cycle of the clock even when the voltage of the circuit drops or the temperature changes. Is. That is, also in the second delay circuit DLY2, the preset delay amount changes with the same tendency as the first delay circuit DLY1 depending on the voltage and the temperature. In this case, the same control voltage as that applied to the first delay circuit DLY1 is applied to the second delay circuit DLY2, so that the delay amount of the second delay circuit DLY2 is changed to the power supply voltage or the temperature. Regardless, it can be controlled to be constant. FIG. 2 is a circuit configuration diagram of a delay circuit according to another embodiment of the present invention. The configuration of FIG. 2 differs from the configuration of FIG. 1 in that the first delay circuit D
LY1 includes a plurality of serially connected delay units U1 to Un
This is because the second delay circuit DLY2 is composed of a plurality of columns, and the second delay circuit DLY2 is composed of a plurality of delay units U1 to Um having exactly the same structure as the delay units U1 to Un forming the first delay circuit DLY1. Each delay unit has exactly the same delay time characteristic with respect to the power supply voltage and the temperature, and the low-pass filter circuit L
It is constructed so as to show exactly the same reaction to the voltage signal from the PF. A plurality of output terminals OUT1 to OUTi are derived from the second delay circuit DLY2, and the delay time can be selected by selecting the terminals.

According to the above-mentioned configuration, the delay time can be freely selected by selecting the output terminals OUT1 to OUT1 from the second delay circuit DLY2. Further, since the delay units having the same characteristics are combined in series, the delay time can be accurately managed.

[0019]

As described above, according to the present invention, the delay amount of the delay circuit is controlled by the cycle of the clock. Therefore, even if the delay amount of the delay circuit is changed due to the power supply voltage or temperature. By controlling this, a stable delay amount can be obtained. Further, an arbitrary delay time can be obtained by switching the clock cycle and the number of delay stages.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a delay circuit according to an embodiment of the present invention.

FIG. 2 is a circuit configuration diagram of a delay circuit according to another embodiment of the present invention.

FIG. 3 is a circuit configuration diagram showing an example of a first conventional delay circuit.

FIG. 4 is a circuit configuration diagram showing an example of a second conventional delay circuit.

[Explanation of symbols]

 IN input terminal OUT output terminal OUT1 output terminal OUTi output terminal CLK clock signal terminal INV inverter circuit INV1 inverter circuit INV2 inverter circuit PHC phase comparison circuit CHP charge pump circuit LPF low-pass filter circuit DLY1 first delay circuit DLY2 second delay circuit FF1 Flip-flop FFn Flip-flop U1 Delay unit Un Delay unit Um Delay unit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroshi Sato 580-1, Horikawa-cho, Sachi-ku, Kawasaki-shi, Kanagawa Stock company Toshiba Semiconductor System Technology Center

Claims (2)

[Claims] 1. A first delay means for changing a delay time by an input control signal, delaying an input clock signal by the delay time and outputting the delayed clock signal, and a delay time for changing the delay time by inputting the control signal. A second delay means for delaying the input signal by the delay time and outputting the delayed signal; a phase of the signal obtained by logically processing the clock signal; and a phase of the delayed clock signal output from the first delay means. And a phase comparison means for generating a phase control signal according to the comparison result and applying the phase control signal to the first delay means and the second delay means at the same time as the respective control signals. Delay circuit. 2. The first delay means is a series connection of n first delay units, wherein the control signal is applied to each of the first delay units, and the second delay unit includes: The delay means is configured by serially connecting m second delay units having the same configuration as the first delay unit, and the control signal is applied to each of the second delay units. The circuit according to claim 1, wherein each of the delay units has an output end that delays and outputs the input signal.