JPS6038669B2 - Interference avoidance radar device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a radar device that avoids interference caused by interference waves by detecting interference waves and automatically switching the transmitting/receiving frequency to a frequency free of interference waves, and in particular, a pulse compression device equipped with this function. Regarding radar equipment.

BACKGROUND ART In recent years, electronic devices have made remarkable progress, and the density of radio waves continues to increase.

Therefore, radio wave interference from other electronic devices to the radar device often occurs, resulting in a decline in the ripening detection ability of the radar device. As an effective means for eliminating this interference, there is a frequency switching transmission/reception method in which a plurality of radar device transmission/reception frequencies are prepared, and when the used transmission/reception wave number receives interference, the frequency is switched to another frequency.

Here, the reception frequency is a frequency that has a certain range around the corresponding transmission frequency as the center frequency, and does not mean a single frequency. In this case, since the number of transmission lines and the reception frequency are set to switch simultaneously, the circuit configuration of the radar device for each transmission and reception frequency is called a channel. Therefore, switching between transmitting and receiving frequencies is also called channel switching. Conventionally, this type of radar equipment has had to rely on the judgment of the operator of the radar equipment based on monitoring of the radar scope in order to detect interference. Further, even if interference is detected in an active channel, there is no means for determining the presence or absence of interference in the pond channel, so a newly selected channel may also be affected by interference. In this case, it is necessary to switch between the third and fourth channels based on the operator's judgment, and it takes a considerable amount of time and effort from the operator to avoid interference. Furthermore, in some types of radar equipment, the time required to avoid interference is shortened by periodically or indiscriminately switching channels, regardless of the presence or absence of interference waves.

However, in that case, interference occurs every time the channel frequency and the frequency spectrum of the interference wave match, which leads to a decline in the target detection ability of the radar system.
The present invention solves the drawbacks of these conventional devices.
An object of the present invention is to provide an interference avoidance radar device that can automatically detect interference in an operating channel and automatically switch to a channel free of interference waves in response to this detection.

According to the present invention, in a radar equipment equipped with a large number of channels, means for always detecting a channel in which no interference waves exist (clear channel), and means for detecting interference waves in an active channel; It is possible to obtain a pulse compression radar device capable of avoiding interference and having means for selecting any clear channel based on this detection.

This clear channel detecting means includes a wideband receiving section that separates the received signal for each receiving frequency of each channel and generates each video signal, and a wideband receiving section that obtains a time-integrated signal of each video signal for each channel and generates this signal. The level discrimination circuit generates a channel status display signal representing the presence or absence of interference waves for each channel by avoiding interference values corresponding to the interference signal level.

Further, the interference wave detection means includes a circuit that pulse-compresses the received signal after intermediate frequency conversion, a first detection circuit that detects the output of this pulse compression circuit, a linear amplification circuit that receives the intermediate frequency signal, and this linear amplification circuit. a second detection circuit for detecting a circuit output; a circuit for subtracting the second detection circuit output from the first detection circuit output; and the second detection circuit for a period in which the subtraction circuit output exceeds a certain amplitude. It consists of a planking circuit that erases the output, and a monostable multipiper that is driven by the output of the planking circuit and generates interference and detection pulses with a fixed time width.

The channel selection means includes a circuit that receives the channel status display signal and determines a clear channel to be selected with priority;
and a circuit for commanding switching of the radar operation channel to the priority selection clear channel in response to the interference detection pulse. The interference avoidance radar device according to the present invention can automatically and quickly and reliably detect interference waves in an active channel and automatically switch to a clear channel in a short time.

Therefore, according to the present radar device, it is possible to easily detect and track a target even in an environment where interference waves exist, and it is possible to reduce burden on the radar operator. Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 1 shows an example of a conventional channel switching type interference avoidance radar system having a pulse compression type transmitting/receiving system.

In Figure 1, 1 is an antenna, 2 is a circulator, 3 is a transmitter, 4 is a channel control circuit, 5 is a trigger generator, 6 is a TR tube, 7 is a local oscillator, 8 is a receiver, and 9 is a display. be. In such a configuration, the transmitter 3 driven by the trigger from the trigger generator 5 generates a high frequency pulse transmission signal.

This transmitted signal is a signal that is received as a reflected signal and then processed to be pulse compressed in the receiver 8. After passing through the circulator 2, this transmission signal is radiated into space from the antenna 1. The reflected signal is reflected by the antenna 1 and is applied to the receiver 8 via the circulator 2 and the TR tube 6. The local oscillator 7 receives a part of the transmission signal and supplies the receiver 8 with a local oscillation signal having a frequency higher than that by the intermediate frequency of the receiver 8 . Therefore, the receiving frequency always changes in line with the transmitting frequency. The receiver 8 obtains a video signal by converting the received high frequency signal to an intermediate frequency, pulse compression and detection, and sends this to the display 9. The transmission frequency is determined by the channel manually designated in the channel selection circuit 4. The radar operator observes the radar scope on the display 9 and, if the presence of interference waves is confirmed, manually switches to another channel to avoid the interference waves. However, the disadvantages inevitable to this conventional method are as described above. FIG. 2 shows an N-channel pulse compression type interference avoidance radar system as an embodiment of the present invention.

Components that are the same as in FIG. 1 are designated by the same reference numerals. This embodiment includes a distribution circuit 10, a broadband receiving section 11, a level discriminator 12, in addition to the same parts as the conventional device, which are constructed from these circuits.
, a channel selection circuit 13 and an interference wave detection circuit 14. The distribution circuit 10 distributes and supplies the received signal to the radar receiver 8 and the broadband receiver 11. The wideband receiving section 11 is
N narrowband filters each having a center pass frequency equal to the transmission frequency of each channel, N detectors each generating a video signal from the output of these filters, and N detectors each amplifying these video signals. It consists of two video amplifiers. Note that instead of obtaining video signals for each channel individually, the wideband receiver 11 uses a single wideband receiver or a wideband frequency discriminator that can generate a single intermediate frequency signal for the frequency range of all channels. , a method of obtaining a video signal for each channel by time-division processing, or any other method can be adopted. The level discrimination circuit 12 also consists of N channels, and the detailed block diagram of each channel is shown in the third section.
As shown in the figure.

The integrating circuit 31 time-integrates the video signal of the corresponding channel of the wideband receiving section 11 and generates a reception level voltage.
The pulsed received signal is smoothed by this integration process. The threshold circuit 32 sets a predetermined reception level voltage slightly higher than the predicted signal level of long-distance clutter and receiver internal noise.
The waveform shaping circuit 33 outputs a constant DC voltage of "1" as the output of the threshold circuit 32 when there is a voltage difference.
” signal, and when the output is zero, it outputs a “0” signal which is a ground potential. The output of this waveform shaping circuit 33 is called a channel height display signal. The “0” indicates that the channel is a clear channel. , "1" indicates that the channel is the operating channel of the radar device or the interference wave reception channel.The interference wave detection circuit 14 receives the trigger signal b,
The channel selection circuit 13 receives the intermediate frequency signal a (signal before pulse compression) extracted from the intermediate frequency amplification stage of the radar receiver 8, detects the presence of interference interference waves in the active channel, and sends the interference detection pulse f to the channel selection circuit 13. Add to.

When the channel selection circuit 13 receives the interference detection pulse f, it selects a predetermined priority channel from among the clear channels indicated by the channel status display signal, and outputs a channel switching signal instructing switching to that channel. The channel switching circuit 4 switches the radar device to a new channel in response to this channel switching signal. Referring to FIG. 4, a detailed block diagram of the interference wave detection circuit 14 is shown.

The intermediate frequency signal a of the radar receiver 8 is applied to two signal processing systems. In the first system, the intermediate frequency signal a is applied to a pulse compression circuit 41. As described above, the transmission signal of the radar device is processed to be pulse compressed after being received. Therefore, in the output of the pulse compression circuit 41, the target signal is relatively emphasized, and interference waves, clutter, and noise are suppressed. The logarithmic amplification and detection circuit 42 amplifies and detects the output of the pulse compression circuit 41 over a wide signal level range to generate a video signal. In the second system, the intermediate frequency signal a is amplified (or attenuated) by a linear amplification (or attenuation) circuit 43, and converted into a video signal by a logarithmic amplification/detection circuit 44 having the same characteristics as the circuit 42. It is added to the delay circuit 45. The first system and the second system have equal gains for unprocessed signals to be pulse compressed. Further, the delay circuit 45 adjusts the signal processing times of both systems so that they match. The differential amplifier circuit 46 extracts and amplifies only the target signal by subtracting the second system video signal from the first system video signal.

The pulse shaping circuit 47 shapes the target signal whose amplitude exceeds a predetermined amplitude into a gate signal having a constant amplitude and a constant time width. This time width is set slightly wider than the transmission pulse width. The clutter removal circuit 48 is a well-known STC (Se
mitiviVTimeControl) circuit,
The main purpose is to suppress ground clutter and sea clutter that exist within a certain period of time from reception of trigger b in the second system video signal. Even if interference waves below the clutter level are eliminated by suppressing clutter for a certain period of time from trigger b, the interference waves do not constitute interference and therefore do not interfere with interference wave detection. Further, since long-range clutter is generally at a lower level than interference waves, it will not be mistaken as an interference wave even if it is not selectively suppressed. The clutter suppression threshold level of this STC circuit is set to decrease depending on the distance, and in addition to the above-mentioned clutter, low-level interference wave signals that cannot become interference,
It also eliminates receiver noise. Therefore, the clutter suppression circuit 48 output includes only the interference wave signal and the target signal. A detailed block diagram of the planking circuit 49 is shown in FIG.

The gate circuit 52 blocks the output of the delay circuit 51 only during the time when the gate signal c exists, and allows it to pass during the other times. The delay circuit 51 provides a time delay to the clutter removal circuit output d so that it coincides with the gate signal c in time. Here, only the interference wave component was extracted as the gate circuit output e. When the interference wave power is high, the target signal video cannot be obtained from the differential amplifier circuit 46 (FIG. 4), but the gate circuit 52 remains open and the interference wave signal e can be extracted without any problem. . Continuing the explanation with reference to FIG. 4 again, the monostable multipipulator 40 is driven by the interference wave signal e and generates an interference detection pulse f.

The pulse width of this interference detection pulse f is determined by the channel selection circuit 1.
3 is set to a value sufficient to generate a channel switching signal in response to the detection pulse f. Interference detection will be explained with reference to FIG. 7, which shows signals from each part of FIG. (herein referred to as a target signal) and interference waves from other radars.

When the signal a is pulse compressed by the pulse compression circuit 41,
Although the target signal is emphasized, other clutter and interference wave levels hardly change (see FIG. 7B). Therefore, if we take the difference between the pulse-compressed signal and the non-pulse-compressed signal in the differential amplifier circuit 46, only the target signal remains (the seventh
(see FIG. C), and the pulse waveform shaping circuit 47 outputs the gate signal C (see FIG. 7) as described above. On the other hand, by performing sensitivity adjustment (STC) in the clutter removal circuit 48, the seventh
Since the clutter in Figure A is suppressed, its output d is shown in Figures 7 and 8. In the planking circuit 49, the gate signal C
The target signal is removed from the signal d to obtain the interference signal e (see FIG. 7F). The monostable multipipulator 40 receives this interference pulse e and outputs an interference detection signal f. Although interference is detected in the manner described above, it goes without saying that clutter removal means such as STC (Other OG/CFAR) may also be used as the clutter removal circuit 48.

In the interference wave detection circuit shown in FIG. 4, a dedicated pulse compression circuit 41 is provided, but this is omitted and a part of the pulse compression circuit output in the radar receiver 8 (FIG. 2) is provided. There is no problem in adding it to the logarithmically amplified detector 42.

Furthermore, the logarithmic amplification detectors 42 and 43 are connected to the interference wave detection circuit 14.
The purpose of this is to expand the operating reception signal range (dynamic range) of the receiver, but if the dynamic range does not need to be that large, it can also be configured with a linear amplifier and a detector. As the clutter removal circuit 48, S. T. C
I gave an example of the circuit, but from trigger b to ground (sea)
It is also possible to employ a gate circuit that blocks all signals during a certain period when clutter is predicted to exist. Furthermore, in an environment where there is almost no clutter, the clutter removal circuit 48 can be omitted. Referring to FIG. 6, the channel selection circuit 13 when the number of channels N=5
A detailed block diagram of is shown.

The channel 1 system consists of an inverter 621, AND gates 631, 641, and a flip-flop 661. The same goes for other channels. As described above, the channel status display signals h, h2, . Now, assuming that channel 1 is an interference wave reception channel, channel 2 is a decoder operation channel, and channels 3, 4, and 5 are clear channels, the outputs of inverters 621 and 622 are ''011, and the outputs of inverters 623, 624, and 625 are It is “1”. At this time, if we receive the interference detection pulse f, then AN
D gate 631, 632 output is “0”, AND gate 6
38, 634, and 635 outputs become "1". The shift register 65 is activated by the interference detection pulse f, generates gate signals g,,, & . Continue until received. Last gate signal &
The time at which f should be generated is the period during which the interference detection pulse f exists. Even if gate pulses g,, & are generated, AND gate 6
41,642 output is ``0'', but gate pulse &
When this occurs, the output of the AND gate 643 becomes 111''.
When the flip-flops 661, 662, . . . , 665 receive the interference detection pulse f in the reset state R, they are reset by the rise of the interference detection pulse f, and the output becomes "0". When the output of AND gate 643 becomes "1", flip-flop 663 is set and its output is held at "1". OR gate 67 receives the output of flip-flop 663 and generates stop pulse i. stop pulse i
As a result, the shift register 65 which has stopped shifting the clock pulse (common to digital circuits of radar equipment) is cleared without generating the gate signal &, and is in a standby state until receiving the next interference detection pulse. Therefore, only the flip-flop 663 of channel 3 is set and the flip-flops of the other channels remain reset. In response to the output of flip-flop 663, channel switching circuit 4 (FIG. 2) switches the transmission/reception frequency of the transceiver to channel 3. Although the present invention has been described above in detail with reference to Examples, it goes without saying that the present invention described in the claims is not limited thereto.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional interference avoidance radar device, and FIG. 2 is a block diagram showing an interference avoidance radar device according to the present invention. This is a diagram. Figures 3, 4, 5 and 6 are block diagrams of the level discrimination circuit, interference wave detection circuit, planking circuit and channel selection circuit, respectively, and Figure 7 is shown in Figures 2 and 4. FIG. 3 is a waveform diagram for explaining the operation of the interference wave detection circuit. In each figure, reference number 1
is an antenna, 2 is a circulator, 3 is a transmitter, 4 is a channel switching circuit, 5 is a trigger generator, 6 is a TR tube, 7
1 is a local oscillator, 8 is a receiver, 9 is a display, 1 is a distribution circuit, 11 is a wideband receiver, 12 is a bell discrimination circuit, 13
14 is a channel selection circuit, 14 is an interference wave detection circuit, 31 is an integration circuit, 32 is a threshold circuit, 33 is a waveform shaping circuit, 40 is a monostable multipipe plate, 41 is a pulse compression circuit, 42 and 44 are logarithms. 4 is an amplification detection circuit, 43 is a linear amplification circuit, 45 is a delay circuit, 46 is a differential amplification circuit, 4
7 is a pulse shaping circuit, 48 is a clutter removal circuit, 49 is a planking circuit, 51 is a delay circuit, 52 is a gate circuit, 65 is a shift register, 67 is an ○R gate, 621-
625 is an inverter, 631-635, 641-645
is an AND gate, and 661 to 665 are shift registers. Figure 1 Chemistry Figure Pu S Figure Age 2 Homme Figure Rubber Figure No. 78

Claims (1)

[Claims] 1. In a pulsed pressure type radar device that can operate on multiple predetermined transmission and reception frequencies (channels),
a first means for removing a clutter signal from a received signal; a second means for pulse-compressing the received signal; and a target signal from the received signal by comparing the pulse-compressed signal with a non-pulse-compressed signal. a fourth means for detecting the presence of an interference wave based on the level of the signal from which the clutter signal and the target signal have been removed by the first and third means; a fifth means for detecting a channel (clear channel) in which there is no interfering interference wave based on the level of the received signal with respect to a predetermined channel of the transmitting/receiving frequency; and sixth means for selectively switching a predetermined channel among the clear channels detected by the fifth means when the presence of the clear channel is detected.