JPS6032340A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To enable to individually design only particularly a wiring portion by varying the configurations of the number of bits and the number of words of a memory by altering only a wiring pattern. CONSTITUTION:A peripheral region 11 includes a bonding pad, an input buffer and output buffer. An internal region 12 has a gate array in which basic element cells 13 are disposed in a matrix shape, and a memory circuit 14. The memory circuit 14 has a basic memory 31, a memory control circuit 32, a wiring pattern region 33 for mutually connecting between the basis memories and the connection to a memory controller in the number of bits and the number of words of the desired memory circuit. The control circuit 32 has an array of basic element cells 13. The size of the array 32 depends upon the types of the size (mXn) of the basic memory, the number of the disposed basic memories, the number of words and the number of bits to be prepared in a master-slice type integrated circuit as the entire memory circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical field to which the invention pertains The present invention relates to an integrated circuit, and more particularly to a master slice type semiconductor integrated circuit device in which only wiring portions are individually designed.

(2) Description of the Prior Art An integrated circuit used specifically for a particular device is generally called a special-purpose integrated circuit, as opposed to a general-purpose integrated circuit. Specialized integrated circuits are characterized by high-mix, low-volume production. Reducing the number of development steps for dedicated integrated circuits that are produced in a wide variety of products and in small quantities is currently a major issue. One way to solve all of these problems is to use the master slice method. In a master slice type integrated circuit, a transistor level (U) that constitutes a logic element or a memory element is set as one or all basic system child cells on the value side.

The feature is that an integrated circuit having any individual function can be realized by simply arranging the cells fixedly on the entire semiconductor substrate and connecting wiring patterns.

By sharing the design and manufacturing process before wiring, it is possible to shorten the design period and manufacturing period.

Next, the configuration of a conventional master slice type integrated circuit will be explained. Most conventional master slice integrated circuits do not have a memory section. In addition, in master slice integrated circuits that have a memory section, the gate array section can obtain various functions depending on the wiring pattern, but the bit and word configuration of the memory section is fixed and cannot be changed depending only on the wiring pattern. However, it has the disadvantage that it cannot accommodate configurations of various numbers of bits and numbers of words required for various devices.

(3) The object of invention q is to solve the above-mentioned drawbacks in a master slice integrated circuit having a memory section by making the number of bits and words of the memory variable by changing only the overall wiring pattern. Completely removed Master Slice Manshiki Kagou episode I! 3 devices.

(4) Structure of the Invention The master slice type integrated circuit W6 device of the present invention includes a total of a plurality of mxn bit basic memories of 4f at address terminals, write data terminals, read data terminals, and storage control terminals, and a basic A memory circuit including a memory control section that controls the memories, and a wiring pattern area for interconnecting the basic memories and the memory control sections according to the desired number of bits and number of words of the memory circuit. The basic element cells were arranged in a wax-like manner. a gate array section functioning partially or fully interconnected with the memory circuit section;
All features are constructed on one chip.

(5) Embodiment Next, an embodiment of the present invention will be described with reference to FIGS. 1 to 7. The number of copies in Figure 1 is 10.

In the overall diagram of one embodiment of the master slice type integrated circuit with memory according to the invention, reference numeral 11 includes a bonding pad, an input buffer 7 and an output balanoa in the peripheral region. 12
1 is an internal region, which consists of a gate array section arranged in an IJ box shape, and a memory circuit section 14, surrounding the basic element cell 13.

FIG. 2t is an explanatory diagram of a specific embodiment of the basic element cell 13 of FIG. 1. 21 is the M (J8) transistor gate of the Pm channel, 22 is N8! ! Chiang Yi, Lu M (JSh
A transistor gate 23 is a P-type diffusion region, and 24 is an N-type diffusion region, which serves as the source or drain of the transistor in the P and N valleys. 25 is an electrode terminal connected to G transistors. The dotted line 26 indicates the position where the eleventh wiring pattern for making connections within the basic element cells or between the basic element cells can be placed.

The chain section 27 indicates a position where a second layer wiring pattern having the same role as the first layer can be placed. Next, FIG. 3 shows an embodiment of a memory circuit section according to the invention. 31 is a basic memo! J-, 32 is a memory control unit;
Reference numeral 33 denotes a wiring pattern area for interconnecting the basic memories and the memory control unit according to the number of bits and words of the desired memory circuit. Figure 4 is a diagram illustrating basic memory. 31 is one embodiment of the basic memory according to the invention. 41 is a memory cell array, mx of 1 normal 6 transistor static memory cell.
An array of n bits (here m==32.n:=9,
42 is an address decoder (5-32 decoder), 43 is a write data control unit (9 bits), 44 is a read data controller, and 44 is a read data controller. ! 1 road (9 pits). The output data latch circuit 44 is necessary when data is extracted from a memory cell at a certain address, latched, and data is transferred to another address while holding the read take value. , if you don't necessarily need this functionality.

This latch circuit can be omitted. 45 is a read data control unit consisting of a sense amplifier and a node circuit (
9 bits) Wl) (9) is 4 of 9 bits! The write data terminal (WENfl) is a 1-bit write control terminal, ADR8 (5) is a 5-bit address terminal, and LAT (1) is a 1-bit latch control terminal. Rl) (9) is a 9-bit protrusion data terminal. That is, 31 is basically a static memory of 32 words x 9 bits.

Since this is a well-known circuit that can be easily designed by a memory circuit engineer, the details will be omitted.

FIG. 5 shows an embodiment of the memory control section, where 32 is the entire memory control section and 32 is an array of basic element cells 13. 32 is a circuit engineer who can construct a desired control circuit by wiring pattern. mxn) and the number of basic memories arranged and the entire memory circuit section should be prepared in a master slice type integrated circuit.

The number of words and number of pits are determined by the type of configuration. 6th
The figure and FIG. 7 show two different embodiments of the wiring pattern configuration of a memory circuit section having four basic memories of 32 words x 9 bits. FIG. 6 shows the entire configuration of a 128 word x 9 bit memory circuit, and FIG. 7 shows the entire memory circuit.

It consists of two memory circuits of 64 words x 9 bits.

14 in FIG. 6 is a memory circuit section, 32 is a memory control section,
31 is basic memory (32 words x 9 bits). 61U
A 9-bit 4-1 selector circuit selects any of the 9-bit data kA6 and A of the four basic memories.
This circuit selects the address of No. 7 based on the decoded signal.

Since it is easy for a logic circuit engineer to realize a 9-bit 4-1 selector circuit, the details will be omitted. 62 is an inverter circuit, 63 is a two-man power NAND circuit, and 64 is a two-man power 1N (JR circuit).

A(5) is a 5-bit lower address signal terminal, L(1
1 is a 1-bit latch control terminal, Wl)'1
'(9) is a 9-bit write data terminal. WE is a 1-bit write control terminal &6. &7 are each 1-bit upper address (i terminal, R, L) T (91 is 9-bit read data terminal. A(5), L(11)
゜Wi)T(91,WE, A6.A7.RDT(
9) is connected to the cable array section 12 in FIG. 1 by a wiring pattern. That is, 32 in FIG. 6 is A6
．． A circuit that decodes the address of A7, a circuit that combines the WE write-in control signal with the decoding result and logic to control the number in each basic memory v write control 1, and a circuit that selects the read data of each basic memory. These can be easily realized by an MO8 integrated circuit engineer using the wiring pattern if the gate array section of the memory control section shown in FIG. 5 is prepared, so the details will be omitted. 14.31°32.64 in Figure 7
is the same as the explanation in FIG. IA(5) and 2Ai5
) are each 5-bit lower address signal terminals. and 2WE are 1 and 2 write control terminals.

IA6 and 2A6 are %1-bit upper address signal terminals. IRDT (9) and 2RDT (9) are 9-bit read terminals No. 1g. 1 from lA15) and 2N5) above
atyr9 and zRDT (up to 91) (0 can terminal is connected to gate array part 12 in Fig. 1 by wiring pattern. Part number 71 is a 9-bit 2-1 selector circuit that handles 9-bit data of two basic memories. This is a circuit that selects the 9-bit data 1lA6, FJ, or 21t6 using the key code that decodes the address. It is easy for a logic circuit engineer to realize the entire 9-bit 2-1 selector circuit. Details are omitted.

(6) Effects of the invention As explained above, in a master slice type integrated circuit with memory, by including a plurality of basic memories, memory control, wiring pattern area and metal in the memory circuit section, The configuration of the number of words and number of bits in the memory circuit section can be changed only by changing the overall wiring pattern, which has the advantage that the master slice type integrated circuit with memory can be applied to a variety of devices.

[Brief explanation of drawings]

FIG. 1 shows an example of a master slice with memory according to the invention, FIG. 2 shows an example of a basic element cell V, and FIG.
An embodiment of a memory circuit section according to the invention, FIG. 4 shows an example of a basic memory, FIG. 5 shows an embodiment of a memory control section, and FIG. 6 shows a memory circuit section with a 128 word x 9 bit configuration. Example. FIG. 7 shows an embodiment of two memory circuits each having a 64 word x 9 bit configuration. In addition, in the figure. 10... Example s of master slice type integrated circuit with memory 11... Peripheral area, 12.
...Internal region, 13...Basic element cell, 1
4...Memory circuit section, 21...P-type channel MO8) transistor gate, 22...N
Type channel MO8) Syndistor gate, 23...
・P-type diffusion region, 24...N-type diffusion region, 25
...... Electrode terminal connected to the gate, 26...
・Possible position for first layer wiring pattern. 27... Second layer wiring pattern possible position, 31.
...Basic memory, 32...Memory control 1tJ-33...Wiring pattern area, 41...
...Memory array, 42...Address decoder, 43...Save data control section,
44... 2-touch circuit, 45... Read data control section (sense amplifier and buffer circuit W5), 6
1...9-bit 4-1 selector circuit. 62... Inverter, 63... Two-man power NANI) circuit. 64...2 manpower N (JR circuit, 71...
9-bit 2-1 selector circuit, WEN (11, WE,
IWE and 2WE・・・1 bit write control terminal, AIJR8 (5L A (5℃I At
5) and 2N5)...5-bit address signal terminal, Wl)+91, Wl)T+91. IWI)
T(9) and 2WJJT(9)...9 bits, data terminal, LAT(1), L(1). January 1) and 2 L(1)...1-bit latch control signal terminal, A6. lA6.2A6 and A7
...1-bit upper address pin No. 8, R month 91
, 1 (1) Tt91 , I RJJT (9) and 2
DT + 9) ... 9-bit bladder supply data end poverty Z ward 3rd ward 4th area 5th flash

Claims (1)

[Scope of Claims] A master slice in which a plurality of basic element cells are arranged in a matrix on a semiconductor substrate and connected within the basic element cells and between the basic element cells by a wiring pattern to form a desired functional circuit. In a semiconductor integrated circuit device, a plurality of basic memories of m rows and n columns (m, where n is a positive integer) bits each having an address terminal, a write data terminal, a read data terminal, a write control terminal, and A memory control unit that controls the memories, and a wiring pattern area for interconnecting the basic memories and the memory control unit according to the number of bits and word size of the desired memory circuits. a memory circuit section including;
A master slice type semiconductor integrated circuit device with a memory, characterized in that the basic element cells include a gate array section that functions by being partially or totally interconnected with the memory circuit section in which the basic element cells are arranged in a matrix.