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JPS62132354A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS62132354A
JPS62132354A JP60273910A JP27391085A JPS62132354A JP S62132354 A JPS62132354 A JP S62132354A JP 60273910 A JP60273910 A JP 60273910A JP 27391085 A JP27391085 A JP 27391085A JP S62132354 A JPS62132354 A JP S62132354A
Authority
JP
Japan
Prior art keywords
cells
basic
array
basic cells
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60273910A
Other languages
Japanese (ja)
Inventor
Haruyo Ueda
植田　治代
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP60273910A priority Critical patent/JPS62132354A/en
Publication of JPS62132354A publication Critical patent/JPS62132354A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To form a desired logic circuit according to combination of functional units by composing an integrated circuit device by disposing a plurality of cells having basic functions in regular arrays different for the respective cells. CONSTITUTION:An address driver 1, a decoder 2, a word driver 3, a memory cell matrix 4, a selector 5 and a 1/0 unit 6 are laid out in a chip 7 of a memory block. The arranging state of the basic cells of the respective sections, i.e., the driver 1 is disposed in an array of 1X6 of basic cells 11, the decoder 2 is disposed in an array of 2X4 of basic cells 12, and basic cells are disposed in a regular array in the other sections to compose function units. A desired logic circuit can be formed by connecting the functional unit time. Since a wiring region is not necessary in this manner, an area efficiency is preferable, and the number of steps of development can be decreased.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、集、遺回路に関し、特に大規模集積回路装置
に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to integrated circuits and circuits, and particularly to large-scale integrated circuit devices.

〔従来の技術〕[Conventional technology]

従来、集積回路の製造方法で、所望の論理回路を短い設
計期間で実現する技術としては単一基本セルを水平・垂
直方向に規則正しく必要なだけ配列上に配置した基本セ
ル間に所望の論理回路を実現するため、配線パターンを
配置する集積回路装置がある。Conventionally, in integrated circuit manufacturing methods, the technology for realizing a desired logic circuit in a short design period is to arrange a desired number of single basic cells horizontally and vertically in an orderly array, and then create a desired logic circuit between the basic cells. To achieve this, there is an integrated circuit device that arranges wiring patterns.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の単一基本セルを配列上に配置し所望の論
理回路を実現する集積回路装置では、所望の論理回路を
実現するために、各基本セル間に配線パタンを配置する
必要があるので、設計が煩雑になる上、配線パタンのた
めの領埴がいるという欠点がある。In the above-mentioned conventional integrated circuit device in which a desired logic circuit is realized by arranging single basic cells in an array, it is necessary to arrange a wiring pattern between each basic cell in order to realize the desired logic circuit. However, there are disadvantages in that the design is complicated and there are additional requirements for the wiring pattern.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の集積回路装置は、複数個の基本的な機能を有す
るセルを各セルごとに異った規則的な配列上に配置し、
て構成された機能単位の組合せにより所望の論理回路を
実現したことを特徴とする。The integrated circuit device of the present invention arranges a plurality of cells having basic functions in a regular array, each cell having a different function,
The present invention is characterized in that a desired logic circuit is realized by a combination of functional units configured as follows.

〔実Ｍｆｌ＋） 次に１本発明について図面を参照して説明する。[Actual Mfl+] Next, one embodiment of the present invention will be explained with reference to the drawings.

第１図は本発明の一実施例のレイアウト図である。第１
図はメモリブロックを実り、シたものであり、チップエ
リア７内にアドレスドライバ一部１゜デコーダ部２．ワ
ードドライバ一部３．メモリセルマトリックス部４．セ
レクタ一部５及び１１０部６がレイアウトされている。FIG. 1 is a layout diagram of an embodiment of the present invention. 1st
The figure shows a completed memory block, in which chip area 7 includes address driver part 1° decoder part 2. Word driver part 3. Memory cell matrix section 4. A selector part 5 and a 110 part 6 are laid out.

第２図は第１ｍの各部分の各基本セルの配列状況を示す
。すなわち、アドレスドライバ一部１は基本セル１１が
ＩＸ６の配列で配置されておシ、デコーダ部２は基本セ
ル１２が２Ｘ４の配列で配置されておシ、他の部分もそ
れぞれ各基本セルが規則的な配列上に配置されることに
よって機能単位を構成している。FIG. 2 shows the arrangement of each basic cell in each part of the 1mth part. That is, in the address driver part 1, the basic cells 11 are arranged in an IX6 arrangement, in the decoder part 2, the basic cells 12 are arranged in a 2x4 arrangement, and in the other parts, each basic cell is arranged in a regular manner. A functional unit is constructed by arranging them in a symmetrical array.

この各機能単位間を接続することによって所望の論理回
路が実現される。A desired logic circuit is realized by connecting these functional units.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明は機能ごとに異った基本セ
ルを配列に配置しその間を接続するだけで所望の論理回
路を実現することが出来、配線領域を必要としないため
面積効率が良く、シかも開発工数が短くなるという効果
がある。As explained above, the present invention can realize a desired logic circuit simply by arranging different basic cells for each function in an array and connecting them, and since no wiring area is required, the present invention is highly area efficient. , it also has the effect of shortening the development man-hours.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例のレイアウト図、第２図は第
１図の各機能部の基本セルの配列を示すレイアウト図。 １・・・・・・アドレスドライバ一部、２・・・・・・
デコーダ部、３・・・・・・ワードドライバ一部、４・
・・・・・メモリセルマトリクス部、５・・・・・・セ
レクタ部、６・・・・・・１１０部、１１・・・・・・
アドレスドライバ一部の基本セル。 １２・・・・・・デコーダ部の基本セル、１３・・・・
・・ワードドライバ一部の基本セル％　１４・・・・・
・メモリセルマトリクス部の基本セル、１５・・・・・
・セレクタ一部の基本セル、１６・・・・・・１１０部
の基本セル。 代理人　弁理士　　内　原　　　１′ 日　ｔ ゝ・−ｍ−。FIG. 1 is a layout diagram of an embodiment of the present invention, and FIG. 2 is a layout diagram showing the arrangement of basic cells of each functional section in FIG. 1. 1... Part of the address driver, 2...
Decoder section, 3... Word driver part, 4.
...Memory cell matrix section, 5...Selector section, 6...110 section, 11...
Address driver some basic cells. 12...Basic cell of decoder section, 13...
・・Word driver part basic cell% 14・・・・
・Basic cell of memory cell matrix section, 15...
- Selector Some basic cells, 16...110 basic cells. Agent Patent Attorney Uchihara 1' day t・-m-.

Claims (1)

【特許請求の範囲】[Claims] 複数の基本的な機能を有するセルを各セルごとに異なっ
た規則的な配列上に配置して構成された機能単位の組合
せにより所望の論理回路を実現したことを特徴とする集
積回路装置。An integrated circuit device characterized in that a desired logic circuit is realized by a combination of functional units formed by arranging cells each having a plurality of basic functions in a regular array that is different for each cell.
JP60273910A 1985-12-04 1985-12-04 Semiconductor integrated circuit device Pending JPS62132354A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60273910A JPS62132354A (en) 1985-12-04 1985-12-04 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60273910A JPS62132354A (en) 1985-12-04 1985-12-04 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS62132354A true JPS62132354A (en) 1987-06-15

Family

ID=17534275

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60273910A Pending JPS62132354A (en) 1985-12-04 1985-12-04 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS62132354A (en)

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