JPS63306641A - Semiconductor integrated circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to semiconductor integrated circuits, and in particular to a base process for CMOS gate arrays.

[Conventional technology]

Conventionally, CMOS gate arrays are arranged in a matrix format, with unit cells (hereinafter referred to as first unit cells) consisting of two-man power NAND (NOR) or three-man power NAND (NOR) of CMOS transistors consisting of a pair of P-channel transistors and N-channel transistors. There are wiring channels between the cell rows of unit cells to obtain the desired theoretical function, and the structure is such that wiring channels and cell rows are alternately provided. The gate channel length and channel width of the P-channel transistor and N-channel transistor of the unit cell are optimum values, and the internal parts except the human output buffer are all composed of the same basic unit cell.

5(a) and 5(b) show a plan view of an example of a chip of a conventional CMOS gate array and an enlarged view of part A thereof, in which 11 is a basic unit cell column, 12 is a wiring channel, 1
3 is a human output buffer circuit group, and 14 is a signal extraction pad. A portion 15 surrounded by a broken line indicates an internal theoretical component.

This enlarged view of part A is an example of a simplified diagram of a mask pattern. 1 is the first basic unit cell, which is a two-manpower NAND (
This is an example of the NOR) system. Two gate polysilicon layers 2 and a P+ diffusion layer 3 or an N+ diffusion layer 4 are provided in a unit cell.
This is the base layer on which two P-channel transistors and two N-channel transistors are constructed. The basic unit cells 1 are arranged in a matrix shape, and the basic unit cells 1 to 1
Dozens of bases, inverters, 2NAND (2NOR)
), 3NAND (3NOR>), decoder, selector, flipflora 1, etc., are basically function blocks connected with metal wiring, and using a CAD tool, desired theoretical functions can be connected with metal wiring.

[Problems to be Solved by the Invention] In the conventional CMOS gate array as described above, a wide variety of function blocks are constructed on the base of one type of optimized basic unit cell l. Therefore, when the delay time must be intentionally slowed down, it is necessary to increase the number of gate stages in order to slow down the speed, and the number of basic unit cells 1 used increases, resulting in very poor efficiency. In recent years, as CMOS has become increasingly faster due to miniaturization and low-temperature use, variations in the maximum and minimum values of delay characteristics due to process variations and variations in usage conditions have become large, making it difficult for buses that require minimum delay times to be guaranteed. The delay circuit function block is one of the causes of increasing the number of gates on the entire chip.

SUMMARY OF THE INVENTION An object of the present invention is to solve such problems and to provide a highly integrated semiconductor integrated circuit that reduces the size of the entire chip by inserting a unique delay circuit.

[Means for solving problems]

The configuration of the present invention includes a unit cell row in which a plurality of first basic unit cells of CMOS gates each having a pair of one to several P-channel transistors and one to several N-channel transistors are arranged, and a unit cell row that has a predetermined theoretical function. In a semiconductor integrated circuit of a CMOS gate array, wiring channels consisting of metal wiring between the first basic unit cells are provided alternately so as to obtain: a P-channel transistor and an N-channel transistor of the first basic unit cell; A second basic unit cell having a predetermined delay amount by having a different channel length or channel width is provided, and this second basic unit cell is placed in the wiring channel or in the first basic unit cell.
It is characterized by being arbitrarily arranged between basic cells.

〔Example〕

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a mask pattern diagram schematically showing a first embodiment of the present invention.6 In this embodiment, a first basic unit cell column 1
1 in the wiring channel 12 between the second basic unit cell 1
6 was inserted.

This second basic unit cell 16 has a gate polysilicon 1
7, P+ diffusion layer 18 and N+ diffusion layer 19
The base structure has one channel transistor and one N-channel transistor. This is because the W/L (W is the channel width, L is the channel length) of the gate polysilicon 17 is made smaller than that of the transistor of the first basic unit cell 1 in order to configure a transistor that slows down the speed. By embedding two basic unit cells 16 in the conventional wiring channel 12, when a delay circuit is required, instead of configuring it with the first basic unit cell 11, an inverter can be configured with the second basic unit cell 16, and this can be chained. You can slow down the delay time. When this second basic unit cell 16 is not required, it can be used as a conventional wiring channel 11 since metal wiring can pass over the cell.

FIG. 2 is a mask pattern diagram of a second embodiment of the present invention. In this embodiment, a second basic unit cell 21 is inserted at an arbitrary location of the first basic unit cell 1, and the gate polygon is It includes silicon 22, P+ diffusion layer 23, and N+ diffusion layer 24, and has a base structure of two each of P-channel and N-channel transistors. In this second basic unit cell 21, a chain of two stages of inverters may be used with metal wiring, or each stage of inverters may be used independently. In this case, the total number of first basic unit cells 1 will be reduced, but a delay circuit This is effective when a large number of unit cells are used, and it is preferable to insert the second basic cells 21 at intervals between the first basic unit cells 1.

FIG. 3 is a mask pattern diagram of a third embodiment of the present invention.
In the wiring channel 12 between the first basic unit cell rows 11,
As the second basic unit cell 31, P with an arbitrary capacitance C
This is an example in which cells having a + diffusion layer 32 and an N+ diffusion layer 33 are arranged. In this example, P" and N+ diffusions are buried, but either one is acceptable. In short, the gate is delayed by connecting as much capacitance C as is not delayed by metal wiring. Therefore, the delay circuit There is no need to prepare a function block as a function block, and since the first basic unit cell 1 does not constitute a delay circuit, it can be used as a public function block, and the first basic unit cell can be used effectively. When not used as a capacitor C, the top of the diffusion layer can be used as a wiring channel, which is no different from the conventional method.

FIG. 4 is a mask pattern diagram of a fourth embodiment of the present invention.
With a certain interval between the first basic unit cell rows 11, the second
A basic unit cell 41 is inserted. In the same machine as in FIG. 3, the second basic unit cell 41 consists of a P" diffusion layer 42 and an N+ diffusion layer 43, and a method is used to delay the gate by adding a capacitance C as much as the desired delay, but in this example, P", N
+Since the diffusion layers 42 and 43 are longer, the number of first basic unit cells is smaller than in the case of FIG.

〔Effect of the invention〕

As explained above, the present invention provides a conventional CMOS gate array with a gate channel length W as a second basic unit cell.
By adding a transistor with a small gate channel width or a P+ diffusion layer or N+ diffusion layer cell with a capacitance C, it is no longer necessary to configure a function block as a delay circuit on the base of the first basic unit cell. The first basic unit cell can be used more effectively than before, and the entire chip can be made smaller and highly integrated.

[Brief explanation of drawings]

1, 2, 3 and 4 are the first and second embodiments of the present invention.
FIGS. 5(a) and 5(b) are plan views showing mask patterns of the second, third and fourth embodiments, and FIGS. 1... Basic unit cell, 2.17.22... Gate polysilicon, 3.18.23.32.42... P+ diffusion layer, 4.19.24.33.43... N1 diffusion layer,
11... Basic unit cell string, 12... Wiring channel, 13... Input/output buffer circuit group, 14... Bad, 15... Internal theory configuration section, 16.21... Second basic unit cell. 2 Keni Tsusokov and -72 Fig. 3 Section 4 Section 5 (α) Fig. 5 (b

Claims (1)

[Claims] 1) A unit cell row in which a plurality of first basic unit cells of CMOS gates each having a pair of one to several P-channel transistors and one to several N-channel transistors are arranged, and In a semiconductor integrated circuit of a CMOS gate array in which wiring channels consisting of metal wiring between first basic unit cells are provided alternately, a P channel transistor of the first basic unit cell and an N
A second transistor having a predetermined delay amount by having a channel length or channel width different from that of the channel transistor.
1. A semiconductor integrated circuit comprising: a basic unit cell; and a second basic unit cell disposed within the wiring channel or arbitrarily between the first basic cells.