JPS60242587A - Dynamic RAM - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a dynamic RAM (random access memory). The present invention relates to a technique that is effective for use in synchronous dynamic RAM.

[Background technology]

Prior to the present invention, the present inventors proposed a pseudo-static RAM that detects changes in address signals and forms various timing signals necessary for the operation of internal circuits (Japanese Patent Application No. 57-164831). ). In other words, a dynamic memory cell is used, which is composed of a capacitor that stores information in the form of charge, and an address selection MOSFET, and its peripheral circuitry is implemented using a CMO3.
(Complementary type MO5) This MO5 is composed of a static type circuit, and by detecting changes in the address signal and obtaining necessary timing signals, it can be treated from the outside in the same manner as a static type RAM.

When using a dynamic memory array in this way,
Since the dynamic type circuit portion is not precharged when the power is turned on, each dynamic type circuit must be operated once before writing or reading.

In order to automatically perform such a dummy cycle, it is conceivable to detect that the power supply voltage rises to a constant voltage higher than the lower limit voltage of operation, and generate a timing pulse to start the dummy cycle.

However, when such an automatic dummy cycle starting circuit is provided, the following problems arise. That is, in a test to measure the lower limit operating voltage of a dynamic RAM, if the power supply voltage is lowered, the cycle automatically shifts to the dummy cycle, so that operation tests such as write/read operations are no longer performed.

[Purpose of the invention]

An object of the present invention is to provide a dynamic RAM that can selectively perform an automatic startup operation when the power is turned on and a lower limit voltage operation test.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, the automatic startup circuit (
This forcibly stops the operation of the dummy cycle starting circuit.

〔Example〕

FIG. 1 shows a circuit diagram of an embodiment of a semiconductor memory device according to the present invention. Each circuit element in the figure is formed on a single semiconductor substrate such as single crystal silicon by a well-known OMO3 (complementary MO3 integrated circuit manufacturing technology).In the following description, unless otherwise specified, MOSFET (insulated gate field effect transistor)
is an N-channel MOS FET. MO3 in the same figure
FETQ7. Q9 etc. are considered to be P-channel type.

The P-channel MO5FET is distinguished from the N-channel MO3FET by the addition of a straight line between its source and drain in the symbol.

The illustrated semiconductor memory device includes a semiconductor substrate made of P-type crystalline silicon, although this is not particularly limited. N
A channel MOS FET is composed of an N-type source and drain region formed on the surface of a semiconductor substrate, and a gate electrode formed on the semiconductor substrate between the source and drain regions with a sapphire film interposed therebetween. Ru. P channel M
The OS FET is formed in an N-type well region formed on the surface of the semiconductor substrate. P channel MO3FE
The substrate gate of T and the well region of T are connected to the power supply voltage Vcc.
be made into The semiconductor substrate serving as the base gate of the N-channel MOS FET is applied with an appropriate level of negative voltage generated from a substrate voltage generation circuit formed on the semiconductor substrate.

In the memory array M-ARY, a pair of rows is shown as a representative, a pair of complementary data lines arranged in parallel, and a plurality of memory arrays D consisting of an address selection MO3FETQm and an information storage capacitor C9. The input/output nodes of the memory cells are distributed and coupled with a predetermined regularity as shown in the figure.

The precharge circuit PCI is MO3 shown as a representative.
Complementary data line like FETQ5.

It is constituted by a switch MO3FETQ14 provided between 6 and 6.

The sense amplifier SA is a P-channel MC) SFETQ7. Q9 and N channel MO3FE
TQ6. Q8, and its pair of input/output nodes are coupled to the complementary data line. In addition, the above launch circuit may include, but is not limited to, a parallel type P-channel MO3FETQI
2. Power supply voltage Vcc is supplied through Ql 3, and N-channel MO3FET QI O,, Ql in parallel form
The ground voltage Vss of the circuit is supplied through 1. These power switches MO3FETQI O, Ql 1 and MO3FETQ12. Although not particularly limited, Q'l3 is commonly used for sense amplifiers SA provided in other similar rows.

Above MO5FETQ10. In the operation cycle, a complementary timing pulse φpal + φpal that activates the sense amplifier SA is applied to the gate of Ql2, and the MO
3FETQI 1. Complementary timing pulses φpa2 and φpa2, which are delayed from the timing pulses φpal and epal, are applied to the gate of Ql3. The reason for this is that when the sense amplifier SA is operated with a minute read voltage from the memory cell, the level drop of the data line is suppressed by the comparatively small conductance characteristic (7) MO3FET.
This is prevented by limiting the current using QI O and Ql 2. Then, after increasing the difference in complementary data line potential by the amplification operation in the sense amplifier SA, the MO3FETQI 1. Ql
3 is turned on to speed up its amplification operation. By performing the amplification operation of the sense amplifier SA in two stages in this manner, high-speed reading can be performed while preventing the complementary data line from falling on the high level side.

The row decoder R-DCR is composed of two divided row decoders R-DCRI and R-DCR2. In the figure, one circuit (four word lines) of the second row decoder R-DCR2 is shown as a representative, and for example, an N-channel MO3FE that receives address signals 72 to T6 is shown as a representative.
TQ32-Q36 and P-channel MO3FETQ37
~ NAND (
The word line selection signals for the four lines mentioned above are formed by the NAND circuit. The output of this NAND circuit is inverted by CMOS inverter IVI and cut MO3FETQ28 to Q31.
Through the transmission gate MO3FE as a switch circuit
TQ9A-Q27(y) is conveyed to y-to.

Further, the first row decoder R-DCR1 receives 2-bit complementary address signals aQ, aQ, and al.

4 types of word line selection timing signals are output from the word line selection timing signal φX through a switch circuit consisting of a MOS FET and a cut MO3FET. φxOO to φxll are formed.

These word line selection timing signals φx00 to φxl
l is the above transmission gate E MO3FET Q24 to Q27
to each word line. Row decoder R-D
By dividing the row decoder into two like CR1 and R-DCR2, the pitch of row decoder R-DCR2 (
Since the pitch of the word lines can be matched with the pitch of the word lines, no wasted space is created.

Note that a MOSFET is connected between each word line and the ground potential.
, Q20 to Q23 are provided, and the above NAN
By applying the output of the D circuit, the word line when not selected is fixed to the ground potential. In addition, the word line has MO3FETs Q1 to Q for reset.
By receiving the reset pulse φpH and turning on these MO3FE and TQI to Q4, the selected word line is reset to the ground level.

Column switch C-5W is M shown as a representative.
O3FETQ42. Like Q43, complementary data line,
D and common complementary data lines CD, CD are selectively coupled. A selection signal from the column decoder C-DCR is supplied to the gates of these MO3FETs Q42 and Q43.

Between the common complementary data line CD and six lines, there is a precharge MO3 which constitutes a precharge circuit PC2 similar to the above.
FETQ44 is provided. A pair of input/output nodes of a main amplifier MA having a circuit configuration similar to that of the sense amplifier SA are coupled to the common complementary data lines CD, CD.

If it is a read operation, the data output cover sofa DO
B becomes operational by the timing signal φrw, amplifies the output signal of the main amplifier MA, and sends it out from the external terminal I10. Note that in the case of a write operation, the output is brought into a high impedance state by the timing signal i'''rtv.

In addition, in the case of a write operation, the data driver cover sofa DIB is activated by the timing signal φrv, and a complementary write signal according to the write signal supplied from the external terminal I10 is transmitted to the common complementary data lines CD, CD. , writes to the selected memory cell. Note that in the case of a read operation, the output is brought into a high impedance state by the timing signal φr11.

Although the automatic refresh circuit REF is not particularly limited,
It includes an address counter that forms a refresh address signal and a timer circuit.

This timer circuit is activated by setting the refresh control signal RESH from an external terminal to a low level. That is, if the refresh control signal RESH is set to low level when the chip selection signal C3 is high level,
The switching signal φref of the multiplexer MPX is output, the multiplexer MPX is switched to the address counter side, and the complementary address signal aO−S8 formed by this address counter is The in-phase address signal aO and the opposite-phase address signal 0 are combined and expressed as a complementary address signal io. This also applies to other complementary address signals.) is transmitted to the address decoder R-DCH. Refresh operation by one word line selection operation (
Auto-refresh). Since the address counter increments every time the refresh control signal RESH is input, all memory cells can be refreshed by repeating the above operation for the number of word lines. Further, if the refresh control signal RESH is kept at a low level, the timer circuit is activated and generates a pulse at regular intervals, so that the address counter is incremented and a continuous refresh operation is performed during this time.

As shown above, MOS FETQ for address selection
In a write operation to a dynamic memory cell consisting of an information storage capacitor Cs and an information storage capacitor Cs, in other words, the information storage capacitor Cs is fully written by the threshold voltage of the address selection MO3FETQm, etc. A word line bootstrap circuit (not shown) activated by the word line selection timing signal φX is provided to prevent a high level loss due to writing to the capacitor Cs. This word line bootstrap circuit uses the word line selection timing signal φX and its delayed signal to set the high level of the word line selection timing signal φX to a high level equal to or higher than the power supply voltage Vcc.

The various timing signals described above are formed by the following circuit blocks.

What is shown by the circuit symbol ATD is, although not particularly limited, receiving address signals aO-a8 (or 80 to 80) and address signals a9 to a14 (or 89 to 14),
This is an address signal change detection circuit that detects a change in the rising or falling edge of the address signal. Although not particularly limited, the address signal change detection circuit ATD can be used for address signals aO to
a14 and its delayed signal, and an OR circuit that receives the output signals of these exclusive OR circuits. That is, an exclusive circuit for receiving an address signal and a delayed signal of that address signal is provided for each address signal. In this case, a total of xs(llil exclusive OR circuits are provided, and the output signals of these 15 exclusive OR circuits are input to the OR circuit. This address signal change detection circuit ATD is , address signal ao-a14 changes, an address signal change detection pulse φ is generated in synchronization with the timing of the change.

The circuit symbol TG is a timing generation circuit, which forms the main timing signals etc. shown as the representative above. That is, this timing generation circuit TG
receives the address signal change detection pulse φ, a write enable signal WE and a chip selection signal CS supplied from an external terminal, and forms the series of timing pulses described above. Further, this timing generation circuit TG includes a dummy cycle starting circuit as described later.

FIG. 2 shows a circuit diagram of an embodiment of a dummy cycle starting circuit (automatic starting circuit when power is turned on).

In this embodiment, although not particularly limited, the power supply voltage Vcc is divided by P-channel MO3FETs Q45 and Q46 connected in series. This divided voltage output is supplied to an input terminal of an inverter circuit IV2 as a voltage detection circuit. This inverter circuit IV2 uses its logic threshold voltage as a reference voltage to identify whether the divided voltage output is high level, low level, or low level. That is, the divided voltage of the predetermined power supply voltage Vcc higher than the lower limit operating voltage of the dynamic RAM is applied to the inverter circuit IV2.
The voltage divider ratio is set to be equal to the logic threshold voltage of

In this embodiment, the voltage dividing circuit is constructed using P-channel MO3FETs for the following reasons.

That is, when an N-channel MO3FET is used, the substrate back bias voltage -VBB generated by a built-in substrate bank bias voltage generator (not shown) fluctuates due to fluctuations in the power supply voltage VCC, and the N-channel MO3FET
Since the threshold voltage of T will be changed, the voltage division ratio will also be changed, so the above P channel M.

5FETQ45. Q46 is used.

The output signal of the inverter circuit IV2 is supplied to the NOR gate circuit G on the one hand, and to the NOR gate circuit G via the delay circuit DL on the other hand. As a result, when the divided voltage of the power supply voltage cc exceeds the logic threshold voltage of the inverter circuit IV2, its output signal changes from high level to low level. At this change timing, a pulse φ' corresponding to the delay time set by the delay circuit DL can be formed (when a chip selection signal C8, which will be described later, is at the normal high level or low level). This pulse φ'' activates the timing generation circuit TG similarly to the address signal change detection circuit φ and generates a series of timing signals, thereby realizing a dummy cycle.

Further, in this embodiment, an N-channel MO3FET Q47 is provided which receives the chip selection signal C3, although this is not particularly limited. , :: MO3FETQ47 is made to have a high threshold voltage by forming its gate insulating film with a thick insulating film such as a field insulating film in an MO3 integrated circuit. For example, when the chip selection signal C8 is set to a high level such as about 10V, the MO3FET Q47 is turned on. This M
By providing a load means R at the source of the O3FET Q47, the O3FET Q47 functions as a source follower circuit receiving the chip selection signal C5. Then, the output signal is used as a gate control signal for the NOR gate circuit G.

For example, if the chip selection signal C8 is at the normal high level or low level, the MOSFET Q47 is turned off and its output is set to the low level (logic "0").
). As a result, the NOR gate circuit G is brought into an open state, so that a timing pulse φ' is generated as described above to start a dummy cycle. On the other hand, when the chip selection signal C8 is set to a high level as described above, the MO3FET Q47 is turned on and its output signal is set to a high level (logic "1"), so the output signal of the NOR gate circuit G is forced to low level (logic “0”)
Therefore, sending out the timing pulse φ' is prohibited.

Thereby, for example, the lower limit operating voltage test operation of the dynamic RAM can be performed by lowering the power supply voltage Vcc. It goes without saying that, prior to such a test operation, the dynamic type circuit is subjected to a necessary precharge operation using the above-mentioned dummy cycle or the like.

Next, with reference to the timing diagram shown in FIG. 3, the operation of the dynamic RAM shown in FIG. 1 will be explained using a read operation as an example.

When the chip selection signal C8 becomes low level, an address buffer circuit (not shown) becomes operational and receives an address signal from an external terminal. When any address signal At supplied from an external terminal changes, an address signal change detection detection pulse φ is generated by the address signal change detection circuit ATD. Timing generation circuit TO once resets the selection circuit of memory array M-ARY in synchronization with this address signal change detection pulse φ. That is,
This timing generation circuit TG generates a timing pulse φpainφpa2'l by the edge detection pulse φ.
c Low level (timing pulse φPal + φpa2 is set to high level), power switch MC of sense amplifier SA) SFET QI O to Q13 is turned off, complementary data line D is set to high level (V
cc level) and low level (■S3 level) are held in a floating state.

Further, by setting the word line selection timing signal φX to a low level and once setting the above-mentioned timing signal φ4 (not shown) to a high level, the selected word line W is brought to a low level and non-selected state.

Next, by setting the precharge pulse φpcII+ to high level and turning on the precharge MO8FETQ5, the complementary data line D is short-circuited to Vcc/2
Precharge to level. After waiting for the time when the complementary data lines D and D both reach the precharge level of Vcc/2, the precharge pulse φpctv is set to the low level. Then, the word line selection timing signal φX is raised to a high level. In synchronization with the rise of this word line selection timing signal φX, the multiplexer MPX
One word line W, which is determined by the complementary address signal 10 to 10'' supplied through the memory cell 10, rises to a high level and is placed in a selected state. As a result, a plurality of memory cells coupled to the selected word line are selected, and the information storage capacitor Cs of each memory cell is connected to the address selection MO.
It is coupled to data line D (or D) via 3FETQm. That is, the input/output node of one memory cell of each complementary data line D is coupled to one data line D (or five). Therefore, a read level appears on the data line D (or D) due to charge dispersion between the accumulated charge in the memory cell and the precharge charge on the data line. In addition,
The other data line D (or D) remains at the precharge level since no memory cell is coupled thereto.

Next, at a relatively early timing, the timing pulse φpa
1 is set to a high level, and a timing pulse 1pa1 (not shown) is set to a low level to operate the sense amplifier SA. As a result, the complementary data line D is at a low level according to the storage charge of the information storage capacitor CS.
amplified to a high level. After the level difference between the complementary data lines and D becomes relatively large due to the amplification operation, the timing pulse φpa2 (φpa2) becomes high level (low level), and a high-speed amplification operation is performed.

Since the amplified signal generated by the operation of the sense amplifier SA is transmitted to the memory cell, the memory information that is about to be lost is rewritten. At this time, since the word line is boosted by the operation of the bootstrap circuit φX-B, the amplified high level is directly transmitted to the information storage capacitor Cs without any level loss.

Note that the subsequent write or read operation is performed at the column switch selection timing (not shown) that is formed later than the word line selection timing signal φX (column switch C-3W is selected by the fi signal φy, and the timing pulses φmal+φ1lla1 and φm a 2 +φm
Due to a2 and φrw, the main amplifier MA and data output buffer DOB operate during reading, and the data input buffer DIB operates during writing (not shown).

As is clear from the above operation, in a read or write operation, a dynamic type circuit such as the memory array M-ARY is once activated and, for example, the complementary data line is
It is necessary that D be at high level or low level. However, immediately after the power is turned on, the level of the dynamic type circuit becomes unstable, and therefore, even if the complementary data line D is shorted due to a change in the address signal, for example, the above-described precharging is not performed. Therefore, a dummy cycle is provided in which a series of timing pulses are generated from the timing generation circuit TG using the timing pulse φ' formed by the rise of the power supply voltage Vcc, and each circuit is temporarily put into an operating state. Further, by stopping the generation of this timing pulse φ° by a signal from an external terminal, the lower limit operating voltage test as described above can be performed.

[Effects] (1) When the power is turned on, the dummy cycle operation is automatically started by detecting that the power supply voltage has reached a predetermined voltage higher than the lower limit operating voltage, and the dummy cycle operation is also started externally. By selectively stopping the operation using a signal from the terminal, it is possible to perform a lower limit operation test.

(2) The control signal for stopping the activation of the dummy cycle operation can be generated by setting the existing control terminal to a predetermined level higher than the normal high level, without increasing the number of external terminals. The effect is that new functions such as the following can be added.

(3) Since the dummy cycle operation can be selectively stopped by an external control signal, when performing only information retention operation such as battery backup, the dummy cycle operation can be performed even if the power supply voltage Vcc is lowered to near the lower limit operating voltage. Since this can be omitted, it is possible to obtain the effect that the information retention operation can be performed with low power consumption.

Although the invention made by the present inventor has been specifically explained based on Examples above, this invention is not limited to the above Examples (although it is possible to make various changes without departing from the gist of the invention). For example, the control signal for stopping the activation of the dummy cycle operation may be provided with an independent external terminal.Furthermore, the precharge level of the data line may be set to the power supply voltage Vcc or Vcc-V.
It may be of a th level. In this case,
The read reference voltage may be formed using a dummy cell. Furthermore, the power supply voltage is lower limit operation 1! Pressure El
The dummy cycle activation circuit that detects that the above predetermined level has been reached and forms a timing pulse for dummy cycle operation can take various embodiments,
Similarly, the circuit for stopping the activation of the dummy cycle operation based on the external control signal can also take various embodiments.

[Application field]

The present invention can be widely used in internally synchronized RAMs in which the memory array C is constituted by a dynamic circuit and detects changes in address signals to form a series of timing signals necessary for internal operations.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of a dynamic RAM according to the present invention, FIG. 2 is a circuit diagram showing an embodiment of a dummy cycle starting circuit, and FIG. FIG. 3 is a timing chart for explaining an example of the operation of the embodiment circuit shown in the figure. M-ARY...Memory array, Pct...Precharge circuit, SA...Sense amplifier, C=SW...Column switch, R-DCR...Row address decoder, C-DC
R: Column address decoder, PC2: Precharge circuit, MA: Main amplifier, AT D: Address signal change detection circuit, TG: Timing generation circuit, R
EF: automatic refresh circuit, DOB: data output noise, DIB: data input buffer, MPX:
・Multiplexer, DL...Delay circuit, G...Nor gate circuit

Claims (1)

[Claims] 1. An internally synchronized dynamic RAM that detects changes in address signals and forms a series of timing signals necessary for internal operations, which detects the rise of a power supply voltage and A dynamic RAM characterized in that it is provided with a starting circuit that starts a dummy cycle for once operating a circuit, and a function that stops starting the gummy cycle in response to a signal from a predetermined external terminal. 2. The external terminal is a chip selection signal, and the activation of the dummy cycle is stopped by setting the chip selection signal to a higher level than a normal high level. Dynamic RAM according to item 1.