JPH01201896A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To enhance the universal applicability of a semiconductor memory without separately providing a clearing terminal by detecting a power source input with a power source initializing circuit, generating a pulse signal, and writing '0' information to the all memory cells with a flash clearing circuit in synchronization with the pulse signal with a flash clearing circuit. CONSTITUTION:A chip selection internal signal the inverse of CS of a power initializing circuit 9 is set at '0' level, and an absolute value VTP of a threshold voltage of a P-type MOSFET Q11 and Q12 and a threshold voltage VTN of an N-type MOSFET Q13-Q15 are set at the relation of VTP<VTN. Next, when a power source VCC rises to be the same as the VTP, the Q11 and Q12 are turned on, a nodal point N1 rises to the VCC, and after a prescribed time, the Q13 and Q15 are turned on. When the signal the inverse of CS changes from '1' to '0' due to the input of the power source, the FETQ3 of a row decoder 2 is turned on, the Q6 is turned off, a word line WL is forcibly set at '1' regardless of an address input and the level of a row decoder activating signal the inverse of XE, and '0' is written to a memory cell 3.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor memory device, in particular, a semiconductor memory device in which all memory cells are set to “0”.
This invention relates to a flash clear circuit for writing information.

[Conventional technology]

First, a conventional flash clear circuit of a semiconductor memory device will be described with reference to the drawings. FIG. 4 shows a conventional flash clear circuit including a memory cell peripheral circuit.

In Fig. 4, 1 is a NAND circuit that receives an address as input, Q1 to Q are P-channel type MO8FETs, and Q, to
Q6 is an N-channel MO3FET.

Xl- is a row decoder activation signal, and D7 is a flash clear internal signal, and the row decoder 2 is configured as described above. Qr, Qs, Ql. is P channel type MO8
FET, Q9 is N-channel type MO8FET, FC'
, F, 7 is a flash clear internal signal, WL is a word line, BL, 100T is a bit line, and 3 is a memory cell. Next, 4 and 5 are inverters, FC is a flash clear input signal, FC' and FC are flash clear internal signals, and the flash clear signal generating circuit 6 is configured as described above.

The operation of the circuit shown in FIG. 4 will be explained. First, FC is “0”
” to “1” level, the output 7 of 4 becomes “
The output FC' of 5 changes from "1" to "0" level, and the output FC' of 5 becomes "0".
” to “1” level.

Since FC is at the "0" level, Q is on and Qs is off. Therefore, regardless of the address input and the level of XE, the word line WL is forced to the "1" level.

Next, since FC' is at the "1" level and FC is at the "0" level, Q v and Q s are off, Q,.

Qro turns on. Therefore, BL is GND level, 100T
becomes the vcc level, and rOJ information is written into the memory cell 3.

As described above, by setting the flash clear input signal FC to the "1" level, it is possible to write "0" information into all memory cells.

[Problem that the invention seeks to solve]

The above-described conventional semiconductor memory device has the disadvantage of lack of versatility because a flash clear input terminal FC must be provided in the flash clear circuit for writing information "0" into all memory cells.

[Means for solving problems]

The semiconductor memory device of the present invention has a power initialization circuit that detects power-on and generates a pulse signal, and has a flash clear circuit that can write "0" information to all memory cells in synchronization with the pulse signal. It is characterized by having a circuit.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is an operation waveform diagram of the embodiment shown in FIG. 1.

In FIG. 1, the row decoder 2, memory cell 3, and their peripheral circuits are the same as those in the conventional example shown in FIG. 4, and therefore their explanation will be omitted. Next, Qr > r Q1□ is P-channel type MOSFET, Qss~QIS is N-channel type MO8FET, and 7.8 is inverter %N
1 is a node, F'C' and FC- are the outputs of the inverter 8.7, and C8 is a chip select internal signal, and the power supply initialization circuit 9 is constructed as described above.

First, the operation of the power supply initialization circuit 9 will be explained using FIG. To simplify the explanation here, C8 is "0".
” level, and the threshold voltage of the N-channel O8FET (hereinafter simply referred to as VTN) is larger than the absolute value of the threshold voltage of the P-channel MO3FET (hereinafter simply referred to as 1VTpl), that is, l Vt.
Assume that there is a relationship p I < VtN.

Power supply Vcc rises more slowly than Ov, and vcc becomes lV?
At time t0 when it becomes equal to Pl, Ql.

Since both Q1□ are turned on, the node N1 rises to a potential equal to Vcc. Next, at time t1 when Vcc becomes equal to 2.VtN-ΔV, in addition to Qll and Q1□, QlS# and Ql5 are also turned on. Here, △V is C13
This is the increase in the threshold voltage of the N-channel MO3FET due to the substrate bias effect. Furthermore, if C13 and Ql, which are connected in series, have an extremely large current capacity compared to Q12, which are connected in series, then at time t1, as shown in FIG. <N, the potential decreases.

As explained above, in the process in which the power supply Vcc rises more slowly than Ov, the node N1 becomes a pulse signal as shown in FIG. Therefore, the pulse signal - passed through the inverter 7 becomes a pulse signal with the phase opposite to that of N1, and the signal FC' passed through the inverter 8 becomes a pulse signal with the same phase as N1.

Next, the clock signal FC' generated upon detecting power-on
, FC7, the circuit operation until "0" information is written into the memory cell will be explained. Y and 7 is rlJ
When the level changes from 0 to 0, C3 is turned on and Qa is turned off, so the word line WL is forcibly set to 1 regardless of the level of the address input. Next F
When C' changes from "0" to "1" level, % Q, Q
L is off, Qs is L. turns on. Therefore, BL is G
The ND level and BL- become the vcc level, and "0" information is written into the memory cell 3. Next, - is "0" in Y
When FC' changes from rlJ to "1" level and from rlJ to "0" level, Qs, Qe, Qlo are off, Q, ~Q,
is turned on, so the row decoder 2 and memory cell peripheral circuits are equivalent to a normal semiconductor memory device, and the Read and W
rite operation becomes possible.

As described above, "0" information is written to all memory cells after power is turned on, and then normal Read or Write operations are performed.
mode.

Next, other embodiments of the present invention will be described.

FIG. 3 is a circuit diagram of a second embodiment of the present invention.

FIG. 3 shows an improvement on the power supply initialization circuit of FIG. 1 of the first embodiment. In Figure 3,
QlllQ12 is P channel type MO8FET,
Q l 3 to Q18 are N-channel type MO8FETs,
7.8 is an inverter, N1 is a node, FC'.

FC'' are the outputs of inverters 8 and 7, respectively, and 37 is a chip select internal signal, and the power supply initialization circuit 10 is configured as described above.

The only difference in FIG. 3 from FIG. 1 is that an N-channel type MOS FET Q 1s is added.

Next, the operation of the circuit shown in FIG. 3 will be explained. Power supply Vcc
When Vcc gradually rises from Ov and Vcc becomes equal to 1vtpl, Qll and C12 turn on, so
Node N1 rises to a potential equal to Vcc. Next, when Vcc becomes equal to 3・VTN+△V', QllI Q+□
In addition to Q, 3. Q,,,Q,.

Also turns on. Here, ΔV' is an increase in the threshold voltage of the N-channel MO8FET due to the substrate bias effect of C13 and C15. Also, compared to Qll and Q+□ which are connected in series, C13 which is connected in series
1 If C151Q+e has an extremely large current capacity, the potential of N1 will be at the "0" level. Note that since the potential of Vcc when the potential of N1 falls is higher than that of the first embodiment in FIG. 1, the pulse width of N1 is wider than that of FIG. 1. As explained above, the power supply V
c c IJ'h In the process of gradually rising from OV, the node N1 becomes a pulse signal with a wider width than in FIG. 1, and similarly, FC' and FC also become pulse signals with a wider width than in FIG.

Therefore, according to FIG. 3 of this embodiment, since FC' and FC are wider pulse signals than in FIG. 1 of the first embodiment, it takes longer to write "0" information into the memory cell. Become,
Stable writing becomes possible. In addition, the row decoder,
Since the operation of the memory cell peripheral circuit is exactly the same as in the case of FIG. 1, its explanation will be omitted.

〔Effect of the invention〕

As explained above, the present invention enables all memory cells to be
0'' information can be written, and there is an advantage that there is no need to separately provide a flash clear input terminal FC as in the conventional case.

In addition, in the embodiment of the present invention, the SRA with 0MO8 configuration
Although the case of M has been described, the present invention is not limited thereto, and it goes without saying that various application examples are possible within the range that satisfies the gist of the present invention.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing a first embodiment of the present invention, Fig. 2 is an operation waveform diagram of Fig. 1, Fig. 3 is a circuit diagram showing a second embodiment of the invention, and Fig. 4 is a circuit diagram showing a second embodiment of the present invention. FIG. 2 is a circuit diagram showing a conventional example. 1... NAND circuit, 2... Row decoder, 3... Memory cell, 4, 5, 7.8...
... Inverter, 6 ... Flash clear signal generation circuit, 9゜10 ... Power supply initialization circuit, FC ... Flash clear input signal,
FC', FC... Flash clear internal signal, XE-... Row decoder activation signal, C8...
...Chip select internal signal, WL...
Word line, BL, BL...bit line. Agent Patent Attorney Oto Uchihara −−=−=−−−I X:Ji Figure 2 Figure 3

Claims (1)

[Claims] A semiconductor memory device having a large number of memory cells arranged in row and column directions includes a power initialization circuit that detects power-on and generates a pulse signal, and in synchronization with the pulse signal, the memory cells are activated. A semiconductor memory device characterized by having a flash clear circuit that can write "0" information to all.