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JPS60160124A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS60160124A
JPS60160124A JP1621884A JP1621884A JPS60160124A JP S60160124 A JPS60160124 A JP S60160124A JP 1621884 A JP1621884 A JP 1621884A JP 1621884 A JP1621884 A JP 1621884A JP S60160124 A JPS60160124 A JP S60160124A
Authority
JP
Japan
Prior art keywords
etching
groove
depth
impurities
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1621884A
Other languages
Japanese (ja)
Inventor
Yoshikazu Ono
大野 吉和
Hideaki Itakura
秀明 板倉
Shuichi Matsuda
修一 松田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP1621884A priority Critical patent/JPS60160124A/en
Publication of JPS60160124A publication Critical patent/JPS60160124A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To provide a groove having a highly accurate depth by a method wherein a groove is formed by etching on the impurity layer having the thickness same as the prescribed groove depth, and the etching is stopped at the point of time when the detection of discharged impurities becomes impossible. CONSTITUTION:An impurity layer is superposed on an Si substrate 1, a mask 2 is provided, and ion plasma 3 is made to irradiate. A groove 1a is etched, impurities are discharged from the impurity layer 10, and these impurities are detected 11. When the groove 1a reached the boundary of the layer 10 and the substrate 1, no impurities are discharged, and the irradiation of ion plasma 3 is stopped at this time. Then, the mask 2 is removed by etching and the titled semiconductor is completed. This method can also be applied to the material other than the Si substrate, other type of vapor-phase etching can be used too, a groove having accurate depth can be formed, the time when etching has reached the prescribed depth can be detected while the etching is being performed, and it has an excellent workability.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は、半導体基板に気相エツチングにより所要深
さの溝を形成する、半導体装置の製造方法に関する0 〔従来技術〕 従来のこの種の半導体装置の製造方法は、第1図に工程
順に示す半導体基板部の断面図のようにしていた。まず
、第1図(a)のように、シリコンなどからなる半導体
基板(1)の上面にマスク(2)を形成する。この状態
の半導体基板(1)部にイオンプラズマ(3)を照射す
る。
[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device in which a groove of a required depth is formed in a semiconductor substrate by vapor phase etching. The method of manufacturing the device was as shown in FIG. 1, which is a cross-sectional view of a semiconductor substrate portion shown in the order of steps. First, as shown in FIG. 1(a), a mask (2) is formed on the upper surface of a semiconductor substrate (1) made of silicon or the like. The semiconductor substrate (1) portion in this state is irradiated with ion plasma (3).

これKより、第1図(b)のように、半導体基板(1)
Kパターンの溝(1a)が形成される。ついで、第1図
(0)のように、マスク(2)をエツチング液などで除
去し、計測器(図示は略す)の触針(4)のとがった先
端で半導体基板(1)上面に当て、水平移動させる。
From this K, as shown in FIG. 1(b), the semiconductor substrate (1)
K pattern grooves (1a) are formed. Next, as shown in FIG. 1 (0), the mask (2) is removed with an etching solution or the like, and the pointed tip of the stylus (4) of a measuring instrument (not shown) is applied to the top surface of the semiconductor substrate (1). , move horizontally.

この触針(4)の上下方向の動きKより、溝(1a)の
深さの測定をする〇 上記従来の方法では、触針(4)を用いて溝(1a)の
深さの測定をしているので、溝(la)幅が触針(4)
の直径より狭い場合は測定することができなかった。
The depth of the groove (1a) is measured by the vertical movement K of the stylus (4). In the above conventional method, the depth of the groove (1a) is measured using the stylus (4). Since the width of the groove (la) is the width of the stylus (4)
It was not possible to measure if it was narrower than the diameter of .

また、エツチングと同時に溝深さの測定を行うことがで
きなく、精度の高い溝深さの形成は困難であった。
Furthermore, it was not possible to measure the groove depth at the same time as etching, making it difficult to form groove depths with high precision.

〔発明の概要〕[Summary of the invention]

この発明は、上記従来方法の欠点を除くためになされた
もので、半導体基板の表面下に所要溝深さと同じ深さに
不純物層を形成し、この半導体基板上にマスクを形成し
、気相エツチングによシェツチング溝を形成していき、
放出する不純物を検出し検出さhなくなった時点で、エ
ツチングを停止するようKL、精度の高い所要深さの溝
が形成され、エツチングをしながら溝の所定深さの検出
ができ、作業性が向上される半導体基板の製造方法を提
供することを目的としている。
This invention was made in order to eliminate the drawbacks of the above-mentioned conventional methods, and involves forming an impurity layer under the surface of a semiconductor substrate to the same depth as the required groove depth, forming a mask on this semiconductor substrate, and forming a vapor phase Forming the etching groove by etching,
KL detects the released impurities and stops etching when they are no longer detected. Grooves of the required depth with high accuracy are formed, and the predetermined depth of the groove can be detected while etching, improving work efficiency. It is an object of the present invention to provide an improved method of manufacturing a semiconductor substrate.

〔発明の実施例〕[Embodiments of the invention]

以下、この発明の一実施例による半導体装置の製造方法
を、第2図に工程順に示す半導体基板部の断面図により
説明する。まず、第2図(、)のように、シリコンなど
からなる半導体基板(1)に必要とする溝深さだけ、イ
オン注入などの方法により不純物層Qlを形成する。不
純物としては、例えば、p形S1基板の場合はよう素を
、n形81基板の場合はひ素を用い、注入量は特性に影
響が小さいように少なくする。つづいて、第2図(b)
のように1半導体基板(1)上面にマスク(2)を形成
する。この状態の半導体基板(1)にイオンプラズマ(
3)を照射する。
Hereinafter, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be explained with reference to cross-sectional views of a semiconductor substrate portion shown in the order of steps in FIG. First, as shown in FIG. 2(, ), an impurity layer Ql is formed in a semiconductor substrate (1) made of silicon or the like by a method such as ion implantation to a required groove depth. As the impurity, for example, iodine is used in the case of a p-type S1 substrate, and arsenic is used in the case of an n-type 81 substrate, and the amount of implantation is made small so as to have little effect on the characteristics. Next, Figure 2(b)
A mask (2) is formed on the upper surface of a semiconductor substrate (1) as shown in FIG. Ion plasma (
3) Irradiate.

これにより、第2図(、)のように1半導体基板(1)
はエツチングが進行し、溝(la)が深くなっていく。
As a result, one semiconductor substrate (1) is formed as shown in Fig. 2 (,).
As the etching progresses, the groove (la) becomes deeper.

このとき、溝深さが所要深さに達していないうちは、エ
ツチングにより不純物層(IIから不純物(10a)が
放出され、これを不純物検知装置0ηにより検出する0 第2図(d)のように、溝(1&)が所要深さに達する
と、不純物層a1のない境界に至っており、不純物(l
oa)が放出されず不純物検知装置1’il)で検知さ
れなくなる。これにより、溝(1a)が所要深さに達し
たことが測定でき、イオンプラズマ(3)の照射を停止
する。このように1イオンプラズマ(3)でエツチング
しながら、溝深さが検知される0 次に、マスク(2)をエツチング液などで除去し、第2
図(、)の状態になる。
At this time, until the groove depth has not reached the required depth, the impurity (10a) is released from the impurity layer (II) due to etching, and this is detected by the impurity detection device 0η as shown in Figure 2 (d). When the groove (1 &) reaches the required depth, it has reached the boundary where there is no impurity layer a1, and the impurity (l
oa) is not released and is not detected by the impurity detection device 1'il). Thereby, it can be determined that the groove (1a) has reached the required depth, and the irradiation of the ion plasma (3) is stopped. While etching with one-ion plasma (3) in this way, the groove depth is detected.Next, the mask (2) is removed with an etching solution and the second etching process is performed.
The state will be as shown in the figure (,).

なお、上記実施例では、気相エツチングとしてプラズマ
エツチングの場合を示したが、リアクティブイオンエツ
チングなど他の種の気相エツチングの場合にも適用でき
るものである0 また、半導体基板はシリコン基板に限らず、他の種の半
導体基板にも適用できるものである。
In the above embodiment, plasma etching is used as vapor phase etching, but it can also be applied to other types of vapor phase etching such as reactive ion etching. However, the present invention can also be applied to other types of semiconductor substrates.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明の方法によれば、半導体基板の
表面下に所要溝深さと同じ深さに不純物層を形成し、こ
の半導体基板上にマスクを形成し、気相エツチングによ
りエツチング溝を形成しながら、放出する不純物を検出
し検出されなくなった時点で、エツチングを停止するよ
うにしたので、溝が精度高い所要深さに形成され、エツ
チングを行いながら溝の所定深さに達する検出ができ、
作業性が向上される0
As described above, according to the method of the present invention, an impurity layer is formed below the surface of a semiconductor substrate to the same depth as the required groove depth, a mask is formed on this semiconductor substrate, and the etched groove is formed by vapor phase etching. Since impurities released during etching are detected and etching is stopped when they are no longer detected, the grooves can be formed to the required depth with high accuracy, and detection of reaching the predetermined groove depth while etching is possible. I can,
Workability is improved0

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の半導体装置の製造方法を示す工程順の状
態の半導体基板部の断面図、第2図はこの発明の一実施
例による半導体装置の製造方法を示す工程順の状態の半
導体基板部の断面図であるOl・・・半導体基板、la
・・溝、2・・・マスク、3・・・イオンプラズマ、1
0・・・不純物層、11・・・不純物検出装置 なお、図中同一符号は同−又は相当部分を示す0代理人
 大岩増雄 第1@
FIG. 1 is a cross-sectional view of a semiconductor substrate portion in the order of steps showing a conventional method for manufacturing a semiconductor device, and FIG. 2 is a sectional view of a semiconductor substrate in the order of steps showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. Ol which is a cross-sectional view of the semiconductor substrate, la
...Groove, 2...Mask, 3...Ion plasma, 1
0... Impurity layer, 11... Impurity detection device Note that the same reference numerals in the figures indicate the same - or corresponding parts 0 Agent Masuo Oiwa No. 1 @

Claims (1)

【特許請求の範囲】[Claims] (1)半導体基板の表面下に所要溝深さと同じ深さに不
純物層を形成し、この半導体基板上にマスクを形成し、
気相エツチングにより溝を形成していき、この溝の形成
によって放出する不純物を不純物検出装置で検出し、検
出されなくなった時点でエツチングを停止する半導体装
置の製造方法。
(1) Forming an impurity layer under the surface of the semiconductor substrate to the same depth as the required trench depth, and forming a mask on this semiconductor substrate,
A method of manufacturing a semiconductor device in which a groove is formed by vapor phase etching, impurities released by the formation of the groove are detected by an impurity detection device, and etching is stopped when the impurities are no longer detected.
JP1621884A 1984-01-30 1984-01-30 Manufacture of semiconductor device Pending JPS60160124A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1621884A JPS60160124A (en) 1984-01-30 1984-01-30 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1621884A JPS60160124A (en) 1984-01-30 1984-01-30 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS60160124A true JPS60160124A (en) 1985-08-21

Family

ID=11910385

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1621884A Pending JPS60160124A (en) 1984-01-30 1984-01-30 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS60160124A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62208634A (en) * 1986-03-07 1987-09-12 Mitsubishi Electric Corp Formation of recess into semiconductor substrate
KR100325598B1 (en) * 1999-05-13 2002-02-25 황인길 method for shallow trench isolation of semiconductor devices
JP2005333875A (en) * 2004-05-27 2005-12-08 Iseki & Co Ltd Combine

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62208634A (en) * 1986-03-07 1987-09-12 Mitsubishi Electric Corp Formation of recess into semiconductor substrate
JPH0548934B2 (en) * 1986-03-07 1993-07-22 Mitsubishi Electric Corp
KR100325598B1 (en) * 1999-05-13 2002-02-25 황인길 method for shallow trench isolation of semiconductor devices
JP2005333875A (en) * 2004-05-27 2005-12-08 Iseki & Co Ltd Combine

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