JPS60142630A - Compensating device of propagation distorsion - Google Patents
Compensating device of propagation distorsionInfo
- Publication number
- JPS60142630A JPS60142630A JP58250099A JP25009983A JPS60142630A JP S60142630 A JPS60142630 A JP S60142630A JP 58250099 A JP58250099 A JP 58250099A JP 25009983 A JP25009983 A JP 25009983A JP S60142630 A JPS60142630 A JP S60142630A
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- Japan
- Prior art keywords
- circuit
- phase
- signal
- data
- wave
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B3/00—Line transmission systems
- H04B3/02—Details
- H04B3/04—Control of transmission; Equalising
- H04B3/06—Control of transmission; Equalising by the transmitted signal
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
fat 発明の技術分野
本発明は伝搬歪補償装置に係り、特に多値ディジタル無
線通信に適用する伝搬歪補償装置に関するものである。Detailed Description of the Invention: fat Technical Field of the Invention The present invention relates to a propagation distortion compensation device, and particularly to a propagation distortion compensation device applied to multilevel digital wireless communication.
(bl 従来技術と問題点
マイクロ波帯を使用して例えば16値直交振幅変調方式
又は64値直交振幅変調方式の様な高能率の多値ディジ
タル無線通信を行う場合、直接波と伝搬路の状態に依っ
て発生した干渉波とを同時に受信すると、ある周波数範
囲で受信レベルが急激に低下する周波数選択性のフェー
ジングを受ける事がある。(bl Prior Art and Problems When performing high-efficiency multilevel digital wireless communication such as the 16-level quadrature amplitude modulation method or the 64-level quadrature amplitude modulation method using the microwave band, the state of the direct wave and the propagation path If interference waves generated by
この様な伝送路に生じたマルチパス・フェージングによ
る伝搬歪は回線品質を劣化させる原因となっている。Propagation distortion due to multipath fading occurring in such a transmission path is a cause of deterioration of line quality.
第1図は伝搬歪補償装置の従来例のブロック接続図で、
第2図は第1図のブロック接続図の動作を説明する為の
周波数特性の図で、第2図(a)は伝搬路の周波数特性
を、第2図(blは伝搬歪補償装置の周波数特性を、第
2図(c)は等化残差をそれぞれ示す。Figure 1 is a block connection diagram of a conventional propagation distortion compensator.
Figure 2 is a diagram of frequency characteristics to explain the operation of the block connection diagram in Figure 1. Figure 2 (a) is the frequency characteristic of the propagation path, Figure 2 (bl is the frequency of the propagation distortion FIG. 2(c) shows the characteristics and the equalization residual.
そこで、第2図を参考にしながら第1図の動作を説明す
る。Therefore, the operation shown in FIG. 1 will be explained with reference to FIG. 2.
先ず、第2図+a)に示す様なマルチパス・フェージン
グに依って発生したディップのあるディジタル変調波が
受信機(図示せず)に入力され、ここで増幅1周波数変
換された後に第1図に示す伝搬歪補償装置9に加えられ
る。First, a digitally modulated wave with dips caused by multipath fading as shown in Figure 2+a) is input to a receiver (not shown), where it is amplified and frequency-converted before being converted into the wave shown in Figure 1. It is added to the propagation distortion compensator 9 shown in FIG.
この伝搬歪補償装置9は直列接続された増幅器1と5と
の接続点とアースとの間に、可変コンデンサ3と線輪4
とから構成された並列共振回路を挿入したもので、周波
数特性を第2図(blに示す様にマルチパス・フェージ
ングによって生じた第2図(alに示す周波数特性の逆
の特性になる様に調整して伝搬歪を補償する。This propagation distortion compensator 9 has a variable capacitor 3 and a wire ring 4 connected between the connection point between the series-connected amplifiers 1 and 5 and the ground.
A parallel resonant circuit consisting of Adjust to compensate for propagation distortion.
この為に、増幅器5の出力信号の一部をスペクトラム検
出器6に加えて例えば伝送帯域中の両端と中心の周波数
に於けるレベルを検出し、それぞれのレベルに差があれ
ば本来レベル差のない伝送路は伝搬歪を持っている事に
なるので制御部8でこの差を補償するための制御信号を
作成する。For this purpose, a part of the output signal of the amplifier 5 is applied to the spectrum detector 6 to detect the levels at both ends and the center frequency of the transmission band. Since a transmission line with no difference will have propagation distortion, the control section 8 creates a control signal to compensate for this difference.
従来、この制御部8にはマイクロプロセッサなどが用い
られている。そして、この制御信号で可変抵抗器2及び
可変コンデンサ3の値を変えて第2図(blの特性にな
る様に調整する。Conventionally, this control unit 8 uses a microprocessor or the like. Then, using this control signal, the values of the variable resistor 2 and variable capacitor 3 are changed to adjust the characteristics as shown in FIG. 2 (bl).
しかし、第1図に示す周波数領域に於ける補償回路では
送信スペクトラムの不均一性、スペクトラムモニターの
有限性などの理由により受信スペクトラムから正しく推
定することが困難であり、又制御上からも並列共振回路
の中心周波数fo、鋭さQを最適の値に設定する事が困
難である等の理由の為に、第2図tc+に示す様に等化
残差が大きく回線品質が充分に改善されないと云う問題
があった。However, with the compensation circuit in the frequency domain shown in Figure 1, it is difficult to estimate correctly from the reception spectrum due to the non-uniformity of the transmission spectrum, the finite nature of the spectrum monitor, etc. Due to reasons such as difficulty in setting the center frequency fo and sharpness Q of the circuit to optimal values, the equalization residual is large, as shown in Figure 2 tc+, and the line quality is not sufficiently improved. There was a problem.
(0) 発明の目的
本発明は上記従来技術の問題に鑑みなされたものであっ
て、伝搬路にマルチパス・フェージングが発生しても回
線品質を劣化させない伝搬歪補償方法を提供する事を目
的としている。(0) Purpose of the Invention The present invention was made in view of the problems of the prior art described above, and an object of the present invention is to provide a propagation distortion compensation method that does not deteriorate line quality even if multipath fading occurs in a propagation path. It is said that
fdl 発明の構成
上記発明の目的は直接波と干渉波の行路差に対応する遅
延量が与えられた受信信号を第1及び第2の信号に分割
する手段と、復調され識別された該第1の信号から同相
データと直交データ及び該同相データから得られた誤差
電圧と該直交データから得られた誤差電圧をそれぞれ取
出す手段と、所定時間遅延させた同相データと該同相デ
ータから得られた誤差電圧及び該遅延させた同相データ
と該直交データから得られた誤差電圧との間の相関をそ
れぞれ取って得られた同相制御信号及び直交制御信号と
、該第2の信号を更に分割して得られた第3の信号及び
第4の信号とを同相制御回路及び直交制御回路でそれぞ
れ混合・合成する混合・合成手段と、該混合・合成手段
の出力を該受信信号に加える手段とを有する事を特徴と
する伝搬歪補償装置を提供する事により達成される。fdl Structure of the Invention The object of the above invention is to provide a means for dividing a received signal given a delay amount corresponding to the path difference between a direct wave and an interference wave into first and second signals, means for respectively extracting in-phase data and quadrature data, an error voltage obtained from the in-phase data, and an error voltage obtained from the orthogonal data from the signal; and in-phase data delayed by a predetermined time and an error obtained from the in-phase data. An in-phase control signal and a quadrature control signal obtained by correlating the voltage and the error voltage obtained from the delayed in-phase data and the quadrature data, respectively, and the second signal are obtained by further dividing the second signal. and a means for adding the output of the mixing/synthesizing means to the received signal. This is achieved by providing a propagation distortion compensator characterized by the following.
(el 発明の実施例
第3図はフェージングの2波モデルに基づく等価回路の
図である。Embodiment of the Invention FIG. 3 is a diagram of an equivalent circuit based on a two-wave model of fading.
図中、12は直接波と干渉波の振幅の比がρとなる回路
を、13は直接波及び干渉波の伝搬路の時間差がτとな
る回路を、14は位相差φを与える回路を、10及び1
1はハイブリッド回路をそれぞれ示す。In the figure, 12 is a circuit where the ratio of the amplitude of the direct wave and the interference wave is ρ, 13 is a circuit where the time difference between the propagation paths of the direct wave and the interference wave is τ, and 14 is a circuit that provides a phase difference φ. 10 and 1
1 indicates a hybrid circuit, respectively.
第3図に於て、入力された波はハイブリッド回路10で
径路■を通る振幅1の直接波と、径路■を通る振幅1の
干渉波に分れる。In FIG. 3, the input wave is separated by the hybrid circuit 10 into a direct wave with an amplitude of 1 passing through the path (2) and an interference wave with an amplitude of 1 passing through the path (2).
直接波はそのまま進んでハイブリッド回路11に加えら
れる。一方、径路■を進んだ干渉波は回路12で振幅が
ρに、回路13で直接波との時間差がτに、回路14で
位相差がφになる様に変化を受けた後にハイブリッド回
路11に加えられ、ここで直接波と干渉波が加算され出
力波として外部に取出される。The direct wave continues as it is and is applied to the hybrid circuit 11. On the other hand, the interference wave that has proceeded along the path ■ undergoes changes such that the amplitude becomes ρ in the circuit 12, the time difference with the direct wave becomes τ in the circuit 13, and the phase difference becomes φ in the circuit 14, and then the interference wave is transferred to the hybrid circuit 11. The direct wave and the interference wave are added here and taken out as an output wave.
この出力波Yは次の様に示される。This output wave Y is shown as follows.
ここで第1項は直接波を、第2項は干渉波をそれぞれ示
す。Here, the first term indicates a direct wave, and the second term indicates an interference wave.
故に、この等価回路の伝送特性■(ω)は次の様になる
。Therefore, the transmission characteristic (ω) of this equivalent circuit is as follows.
従って、これと全く逆な伝送特性を有する回路を受信機
に挿入すれば、このフェージング特性を完全に補償する
事が出来その影響を除去する事ができる事を示している
。This shows that if a circuit with completely opposite transmission characteristics is inserted into the receiver, it is possible to completely compensate for this fading characteristic and eliminate its influence.
そこで、伝搬歪補償装置の伝送特性11c(ω)は下記
の式で表される。Therefore, the transmission characteristic 11c(ω) of the propagation distortion compensator is expressed by the following equation.
(2)式で判る様にρを変える事によりフェージングの
深さくディップ)を、φを変える事により前記のディッ
プの位置を補償する事ができる。As can be seen from equation (2), by changing ρ it is possible to compensate for the depth of the fading (dip), and by changing φ it is possible to compensate for the position of the dip.
第4図は本発明の詳細な説明する為の伝搬歪補償回路の
ブロック接続図で、15及び18はハイブリッド回路を
、16は遅延回路を、17は可変減衰及び可変位相特性
を持った部分である。Fig. 4 is a block connection diagram of a propagation distortion compensation circuit for explaining the present invention in detail, in which 15 and 18 are hybrid circuits, 16 is a delay circuit, and 17 is a part with variable attenuation and variable phase characteristics. be.
本装置の伝送特性が(2)式で表される事は明らかであ
る。It is clear that the transmission characteristics of this device are expressed by equation (2).
第5図は本発明を実施する為のブロック接続図の一例を
示す。FIG. 5 shows an example of a block connection diagram for implementing the present invention.
図中、20は合成回路を、21は遅延回路を、22゜2
3.26及び32はハイブリッド回路を、24,25,
29゜30.33及び34は乗算回路を、27及び28
は積分回路を、38は識別回路を、31は1ビツト遅延
回路を、35及び36は低域ろ波器を、37は搬送波再
生回路を、40.41及び42は端子を、50は復調回
路を、51は同相歪制御回路を、52は直交歪制御回路
をそれぞれ示す。In the figure, 20 is a synthesis circuit, 21 is a delay circuit, and 22°2
3.26 and 32 are hybrid circuits, 24, 25,
29°30.33 and 34 are multiplication circuits, 27 and 28
is an integration circuit, 38 is an identification circuit, 31 is a 1-bit delay circuit, 35 and 36 are low-pass filters, 37 is a carrier recovery circuit, 40, 41 and 42 are terminals, and 50 is a demodulation circuit. , 51 represents an in-phase distortion control circuit, and 52 represents an orthogonal distortion control circuit.
これらの要素は次の様に接続されている。These elements are connected as follows.
ハイブリッド回路26の端子(1)は遅延回路21及び
合成回路20を介して端子40と、端子(2)は復調回
路50と、端子(3)は同相制御回路51及び直交制御
回路52から構成される制御回路を介して合成回路20
とそれぞれ接続される。The terminal (1) of the hybrid circuit 26 is connected to the terminal 40 via the delay circuit 21 and the synthesis circuit 20, the terminal (2) is connected to the demodulation circuit 50, and the terminal (3) is connected to the in-phase control circuit 51 and the orthogonal control circuit 52. The synthesis circuit 20
are connected to each other.
更に、識別回路38の端子(1)及び(6)はそれぞれ
復調回路50と、端子(2)は端子41と、端子(3)
は端子42と、端子(4)は乗算回路30.積分回路2
8を介して同相制御回路51と、端子(5)は乗算回路
29.積分回路27を介して直交制御回路52とそれぞ
れ接続される。Further, terminals (1) and (6) of the identification circuit 38 are connected to the demodulation circuit 50, terminal (2) is connected to the terminal 41, and terminal (3) is connected to the demodulation circuit 50, respectively.
is terminal 42, and terminal (4) is multiplier circuit 30. Integral circuit 2
8 to the in-phase control circuit 51, and the terminal (5) to the multiplier circuit 29.8. They are each connected to an orthogonal control circuit 52 via an integrating circuit 27.
又、遅延回路31の端子(2)は端子41と、端子f1
)は乗算回路29及び30の端子(11とそれぞれ接続
される。Further, the terminal (2) of the delay circuit 31 is connected to the terminal 41 and the terminal f1.
) are connected to terminals (11) of multiplier circuits 29 and 30, respectively.
この様に接続された第5図の回路の動作は次の様である
。The operation of the circuit of FIG. 5 connected in this manner is as follows.
端子40に入力されたディジタル変調波は合成回路20
及び遅延回路21を通った後、ハイブリッド回路26で
2分割される。一部の信号は90度ハイブリッド回路2
3で更に分割された後、それぞれの信号は別々に乗算回
路24及び25に加えられる。The digital modulated wave input to the terminal 40 is sent to the synthesis circuit 20
After passing through the delay circuit 21 and the delay circuit 21, the signal is divided into two by the hybrid circuit 26. Some signals are 90 degree hybrid circuit 2
After further division by 3, each signal is applied separately to multiplier circuits 24 and 25.
一方、ハイブリッド回路26で分割された残りの信号は
公知の復調回路50に加えられ、この回路に含まれるハ
イブリッド回路32で更に2分割され、それぞれの信号
は別々の乗算回路33及び34に加えられる。この乗算
回路33と34には、搬送波再生回路37から入力した
ディジタル変調波の搬送波に同期して互いに位相が90
度異なる搬送波が加えられているので、ここで2つの搬
送波とディジタル変調波とが乗算されて復調信号の同相
分と直交分が得られる。この復調信号の同相分と直交分
はそれぞれ低域ろ波器35及び36を通って公知の識別
回路38に加えられ、この識別回路38から再生された
同相データ及び直交データがそれぞれ端子(2)及び(
3)から、又前記の同相データ及び直交データからそれ
ぞれ得られた誤差電圧が端子(4)及び(5)からそれ
ぞれ取出される。On the other hand, the remaining signal divided by the hybrid circuit 26 is applied to a known demodulation circuit 50, further divided into two by a hybrid circuit 32 included in this circuit, and each signal is applied to separate multiplication circuits 33 and 34. . These multiplier circuits 33 and 34 are synchronized with the carrier wave of the digital modulated wave inputted from the carrier wave regeneration circuit 37 and have a phase difference of 90 degrees.
Since different carrier waves are added, the two carrier waves and the digital modulation wave are multiplied here to obtain the in-phase and quadrature components of the demodulated signal. The in-phase and quadrature components of this demodulated signal pass through low-pass filters 35 and 36, respectively, and are applied to a known identification circuit 38, and the in-phase data and quadrature data reproduced from this identification circuit 38 are sent to terminals (2). as well as(
3) and the error voltages obtained from the in-phase data and quadrature data, respectively, are taken out from terminals (4) and (5), respectively.
尚、誤差電圧は正しい信号レベルの位置からのズレに対
応する電圧である。Note that the error voltage is a voltage corresponding to a deviation from the correct signal level position.
そして、■ビット遅延回路31を通過して1ビツト遅延
させられた同相データは乗算回路30で同相データから
抽出した誤差電圧Eiと、乗算回路29で直交データか
ら抽出した誤差電圧Eqとの相関がそれぞれ取られ、得
られた出力電圧はそれぞれ対応する積分回路28及び2
7に加えて積分される。Then, the in-phase data passed through the bit delay circuit 31 and delayed by 1 bit has a correlation between the error voltage Ei extracted from the in-phase data in the multiplication circuit 30 and the error voltage Eq extracted from the orthogonal data in the multiplication circuit 29. The obtained output voltages are respectively taken by the corresponding integrating circuits 28 and 2.
7 plus is integrated.
この積分回路28及び27の出力は直流に近い信号(以
下同相制御信号及び直交制御信号と云う)で、この同相
制御信号(aとする)は同相歪制御回路51に直交制御
信号(bとする)は直交歪制御回路52に含まれる乗算
回路24と25にそれぞれ加えられる。The outputs of the integrating circuits 28 and 27 are signals close to direct current (hereinafter referred to as in-phase control signals and quadrature control signals), and this in-phase control signal (referred to as a) is sent to the in-phase distortion control circuit 51 as a quadrature control signal (referred to as b). ) are applied to the multiplication circuits 24 and 25 included in the orthogonal distortion control circuit 52, respectively.
ここで、同相歪、直交歪制御回路51.52は第4図の
可変減衰・位相部17に相当する部分である。Here, the in-phase distortion and quadrature distortion control circuits 51 and 52 correspond to the variable attenuation/phase section 17 in FIG. 4.
0
そこで、 この乗算回路24と25には前記の様に位相
が90度異なるディジタル変調波が加えられているが、
今このディジタル変調波を例えばそれぞれ1・Cos
ωを及び1・Sinωtとし、この変調波に前記の制御
信号a及びbがそれぞれ乗算されるとa−cosωtと
bsinωtの2つの信号が得られる。この信号は同相
ハイブリッド回路22でか変化するので振幅及び位相が
変化するが、この合成波が該合成回路20に加えられて
該ディジタル変調波と合成される。0 Therefore, digital modulated waves having a phase difference of 90 degrees are applied to the multiplier circuits 24 and 25 as described above.
Now, for example, each of these digital modulated waves is 1・Cos
Let ω be and 1·Sinωt, and when this modulated wave is multiplied by the control signals a and b, respectively, two signals a-cosωt and bsinωt are obtained. This signal changes in the in-phase hybrid circuit 22, so its amplitude and phase change, but this composite wave is applied to the composite circuit 20 and combined with the digital modulated wave.
この合成回路20、遅延回路21、同相及び直交制御回
路51及び52を含む部分は第4図の回路構成と同じ構
成になっているので、この部分で伝搬路で発生した伝搬
歪は完全に補償する事ができる。Since the section including the synthesis circuit 20, delay circuit 21, and in-phase and quadrature control circuits 51 and 52 has the same circuit configuration as that shown in FIG. 4, the propagation distortion generated in the propagation path is completely compensated for in this section. I can do that.
尚、遅延回路21は2波モデルでの伝搬路の平均行路長
差に相当する遅延量であり、直交制御信号を0にした時
に乗算回路24の入力側での周波数特性の中心が伝送帯
域の中心周波数fと一致する様に微調整する。The delay circuit 21 has a delay amount corresponding to the average path length difference of the propagation paths in the two-wave model, and when the orthogonal control signal is set to 0, the center of the frequency characteristic on the input side of the multiplier circuit 24 is in the transmission band. Make fine adjustments to match the center frequency f.
又、ハイプリント回路23と22とは逆に使用する事が
可能であり、出力信号はハイプリント回路I8の出力に
限らず可変減衰・位相部17、遅延回路16のいずれの
出力から取っても良い。In addition, the high print circuits 23 and 22 can be used in reverse, and the output signal can be taken not only from the output of the high print circuit I8 but also from any output of the variable attenuation/phase section 17 or the delay circuit 16. good.
if) 発明の効果
以」二説明した様に、本発明によればディジタル信号に
適した時間領域でフェージング特性の逆特性を持つ伝搬
歪補償装置を用いて伝送路に発生した伝搬歪を補償する
ので、補償能力が高くしかも補償が高精度で行える。又
、マイクロプロセッサ等を使用する従来の方法に比べて
構成が簡単であり且つ制御も安定に行えるので高い効果
が得られる。As explained in 2.if) Effects of the Invention, according to the present invention, propagation distortion generated in a transmission path is compensated for using a propagation distortion compensator having characteristics inverse to fading characteristics in the time domain suitable for digital signals. Therefore, the compensation ability is high and compensation can be performed with high accuracy. Furthermore, compared to conventional methods that use a microprocessor or the like, the structure is simpler and control can be performed more stably, resulting in higher effects.
第1図は伝搬歪を補償する為の従来例を、第2図は第1
図の動作を説明する為の図を、第3図はマルチパス・フ
ェージングの等価回路を示す図を、第4図は本発明の詳
細な説明する為の図を、第51
図は第4図を用いた伝搬歪補償装置の一例をそれぞれ示
す。
図中、20は合成回路を、21及び31は遅延回路を、
22.23及び26はハイブリッド回路を、24 、2
5 、29及び30は乗算回路を、27及び28は積分
回路を、それぞれ示す。
3
2
寮I 因
η
峯2[1iJ
((1,(b)
(α)Figure 1 shows a conventional example for compensating propagation distortion, and Figure 2 shows a conventional example for compensating propagation distortion.
FIG. 3 is a diagram showing an equivalent circuit of multipath fading, FIG. 4 is a diagram to explain the present invention in detail, and FIG. An example of a propagation distortion compensator using the following is shown below. In the figure, 20 is a synthesis circuit, 21 and 31 are delay circuits,
22.23 and 26 are hybrid circuits, 24, 2
5, 29 and 30 are multiplication circuits, and 27 and 28 are integration circuits, respectively. 3 2 Dormitory I factor η Mine 2 [1iJ ((1, (b) (α)
Claims (1)
受信信号を第1及び第2の信号に分割する手段と、復調
され識別された該第1の信号から同相データと直交デー
タ及び該同相データから得られた誤差電圧と該直交デー
タから得られた誤差電圧をそれぞれ取出す手段と、所定
時間遅延させた同相データと該同相データから得られた
誤差電圧及び該遅延させた同相データと該直交データか
ら得られた誤差電圧との間の相関をそれぞれ取って得ら
れた同相制御信号及び直交制御信号と、該第2の信号を
更に分割して得られた第3の信号及び第4の信号とを同
相制御回路及び直交制御回路でそれぞれ混合・合成する
混合・合成手段と、該混合・合成手段の出力を該受信信
号に加える手段とを有する事を特徴とする伝搬歪補償装
置。means for dividing a received signal given a delay amount corresponding to the path difference between the direct wave and the interference wave into first and second signals; and means for dividing in-phase data, quadrature data and means for respectively extracting the error voltage obtained from the in-phase data and the error voltage obtained from the orthogonal data; and the in-phase data delayed by a predetermined time, the error voltage obtained from the in-phase data, and the delayed in-phase data. An in-phase control signal and a quadrature control signal obtained by correlating with the error voltage obtained from the orthogonal data, and a third signal and a fourth signal obtained by further dividing the second signal. 1. A propagation distortion compensator comprising a mixing/synthesizing means for mixing and synthesizing the signals of the above signals using an in-phase control circuit and an orthogonal control circuit, respectively, and means for adding an output of the mixing/synthesizing means to the received signal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58250099A JPS60142630A (en) | 1983-12-28 | 1983-12-28 | Compensating device of propagation distorsion |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58250099A JPS60142630A (en) | 1983-12-28 | 1983-12-28 | Compensating device of propagation distorsion |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60142630A true JPS60142630A (en) | 1985-07-27 |
Family
ID=17202797
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58250099A Pending JPS60142630A (en) | 1983-12-28 | 1983-12-28 | Compensating device of propagation distorsion |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60142630A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0475376A2 (en) * | 1990-09-12 | 1992-03-18 | General Instrument Corporation Of Delaware | Apparatus and method for linearizing the operation of an external optical modulator |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS561634A (en) * | 1979-06-20 | 1981-01-09 | Nec Corp | Equalizer |
JPS56141625A (en) * | 1980-04-08 | 1981-11-05 | Fujitsu Ltd | Automatic compensation system of propagation distortion |
-
1983
- 1983-12-28 JP JP58250099A patent/JPS60142630A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS561634A (en) * | 1979-06-20 | 1981-01-09 | Nec Corp | Equalizer |
JPS56141625A (en) * | 1980-04-08 | 1981-11-05 | Fujitsu Ltd | Automatic compensation system of propagation distortion |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0475376A2 (en) * | 1990-09-12 | 1992-03-18 | General Instrument Corporation Of Delaware | Apparatus and method for linearizing the operation of an external optical modulator |
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