JP2838962B2 - Carrier recovery method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a carrier recovery system,
In particular, the present invention relates to a carrier recovery system used in combination with a decision feedback equalizer on the receiving side of a digital radio communication system using a multilevel quadrature amplitude modulation system or a polyphase phase modulation system.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram showing an example of a conventional carrier recovery system. In the figure, a digital modulation signal of an intermediate frequency band input from an input terminal 1 is branched into two,
These are supplied to multipliers 4 and 5, respectively. The multiplier 4 multiplies the input digital modulation signal in the intermediate frequency band by the output reproduction carrier of the voltage controlled oscillator (VCO) 17 and outputs a synchronously detected P-channel analog baseband signal. On the other hand, the multiplier 5 multiplies the input digital modulation signal of the intermediate frequency band by a signal obtained by shifting the output signal of the VCO 17 by π / 2 by the phase shifter 3 to obtain a synchronously detected Q-channel analog baseband. Output a signal.

The P-channel analog baseband signal extracted from the multiplier 4 is supplied to an A / D converter 6, where it is sampled and quantized. The Q-channel analog baseband signal extracted from the multiplier 5 is supplied to an A / D converter 7, where it is sampled and quantized.

The digital signals output from the A / D converters 6 and 7 are respectively supplied to a decision feedback equalizer 31, where equalization of intersymbol interference is performed. This decision feedback equalizer 3
The P-channel digital signal sequence after the equalization and the Q-channel digital signal sequence after the equalization output from 1 are input to decision units 9 and 10, respectively, and their logical values are decided.

[0005] The P-channel determination signal output from the determiner 9 is output to an output terminal 14 and the phase error detector 1
1 and the P-channel error signal also output from the decision unit 9 is input to the phase error detector 11. Similarly, the Q-channel determination signal output from the determiner 10 is output to an output terminal 15 and is also input to the phase error detector 11, and the Q-channel error signal output from the determiner 10 is a phase error detector. 11 is input.

Based on the P-channel determination signal, the P-channel error signal, the Q-channel determination signal and the Q-channel error signal, the phase error detector 11 determines the carrier of the input digital modulation signal in the intermediate frequency band, the output signal of the VCO 17 and And outputs a phase error signal of a level corresponding to the phase error. This phase error signal is smoothed by the loop filter 16 and then applied to the VCO 17 as a control voltage. As a result, a signal that is phase-synchronized with the carrier of the input digital modulation signal in the intermediate frequency band, that is, a reproduced carrier is extracted from the VCO 17.

As described above, in the conventional carrier recovery method, the decision feedback equalizer 31 is included in the phase locked loop (PLL) from the detection of the phase error to the control of the phase of the recovered carrier. It has been.

The decision feedback equalizer 31 is a circuit used to equalize intersymbol interference caused by frequency selective fading generated in a propagation path of a digital radio communication system, and is conventionally known (for example, Muroya).・ Written by Yamamoto, “Digital Wireless Communication,” Chapter 6, Publishing Industrial Books. That is, as an example of the decision feedback equalizer, a one-dimensional 5
To describe the tap decision feedback equalizer 200,
The decision feedback equalizer 200 includes a forward equalizer 201, a backward equalizer 202, and a determiner 54.

The forward equalizer 201 multiplies first and second delay circuits 42 and 43 each having a delay time of a symbol interval T by a predetermined tap coefficient.
To the third multipliers 44, 45 and 46 and the forward equalizer 2
And a first adder 47 that outputs an output signal 01.

The operation of the forward equalizer 201 will now be described. The demodulated digital signal sequence input to the input terminal 41 is split into two, and each of the signal sequence is sent to the first delay circuit 42 and the first multiplier 44, respectively. Is entered. The input digital signal sequence delayed by a time equal to the symbol interval T by the first delay circuit 42 is input to the second multiplier 45, while
Are further delayed by a time equal to the symbol interval T and input to the third multiplier 46.

The multiplier 44 multiplies the undelayed input digital signal sequence by a first tap coefficient C _-2 supplied from a control signal generation circuit (not shown) to obtain a first multiplied signal m. Outputs _-2 . Similarly, the multiplier 45 multiplies the input digital signal sequence delayed by the time T by the second tap coefficient C _-1 from the control signal generation circuit, and
6 multiplies the input digital signal sequence delayed by 2T by the third tap coefficient C ₀ from the control signal generation circuit, and converts the second multiplication signal m ₋₁ and the third multiplication signal m _{0 respectively} . Output. The first adder 47 adds and synthesizes the first to third multiplied signals m _-2 , m _-1 and m ₀ and outputs the result.

A backward equalizer 202 multiplies third and fourth delay circuits 48 and 49 each having a delay time of a symbol interval T by a predetermined tap coefficient.
And fifth multipliers 50 and 51, and second and third adders 52 and 53.

To explain the operation of the backward equalizer 202, a signal obtained by determining the digital signal sequence after equalization by the determiner 54 is output to the output terminal 55, while the third delay circuit 48 After being delayed by a time equal to the symbol interval T, the signal is supplied to the fourth multiplier 50, further delayed by the fourth delay circuit 49 by a time equal to the symbol interval T, and input to the fifth multiplier 51.

A multiplier 50 multiplies the output decision signal delayed by the time T by a fourth tap coefficient C _{+ 1} from the control signal generating circuit to output a fourth multiplied signal m _{+ 1.} ,
The multiplier 51 multiplies the output determination signal delayed by a time 2T with the fifth tap coefficient C _{+ 2} from the control signal generation circuit to output a fifth multiplied signal m _{+ 2} . The second adder 52 outputs the fourth and fifth multiplied signals m _{+ 1} and m _{+ 2.}
Are added and synthesized.

The third adder 53 is connected to the first adder 47.
A second adder 52 adds the first addition signal extracted from
Are added to generate a third addition signal, which is output to the decision unit 54 as a digital signal after equalization.

Next, another example of the conventional carrier recovery method will be described. FIG. 3 is a block diagram showing another example of the conventional carrier recovery method. 2, the same components as those in FIG. 2 are denoted by the same reference numerals, and the description thereof will be omitted. In FIG. 3, a quadrature quasi-synchronous detector 101 includes a local oscillator 2, a π / 2 phase shifter 3, multipliers 4 and 5, and frequency-converts an intermediate frequency band digital modulation signal into a base band complex modulation signal. . The local oscillator 2 fixedly oscillates and outputs a predetermined frequency.

Further, the complex multiplier 8 includes a decision feedback equalizer 3.
The multiplication of the real part digital signal sequence and the imaginary part digital signal sequence from 1 is performed in parallel. The carrier regenerator 103 includes a phase error detector 11, a loop filter 12, and a digital voltage controlled oscillator (VCO) 13.

Next, the operation will be described. The input digital modulation signal of the intermediate frequency band inputted from the input terminal 1 is divided into two and inputted to the multipliers 4 and 5, respectively. The multiplier 4 multiplies the intermediate frequency band input digital modulation signal by a local signal from the local oscillator 2 having a frequency substantially equal to the frequency of the carrier of the intermediate frequency band digital modulation signal. The real part signal of the complex modulation signal in the band is output.

On the other hand, the multiplier 5 converts the input digital modulation signal into a local signal from the local oscillator 2 by π / 2.
The imaginary part signal of the quasi-coherently detected baseband complex modulation signal is output by multiplying the signal shifted by π / 2 by the phase shifter 3. The real part signal of the baseband analog complex modulation signal output from the multiplier 4 is supplied to an A / D converter 6 where it is sampled and quantized. Further, the imaginary part signal of the analog complex modulation signal in the baseband output from the multiplier 5 is supplied to the A / D converter 7 where it is sampled and quantized.

The digital signal sequence of the real part output from the A / D converter 6 and the digital signal sequence of the imaginary part output from the A / D converter 7 are supplied to a decision feedback equalizer 31 having the configuration described with reference to FIG. Is used to equalize intersymbol interference. The real part digital signal sequence and the imaginary part digital signal sequence after the equalization output from the decision feedback equalizer 31 are respectively supplied to the complex multiplier 8, where the digital VCO in the carrier regenerator 103 is sent.
Synchronous detection is performed only by multiplying by the baseband reproduced carrier from the baseband 13.

The equalized P-channel digital signal sequence and Q-channel digital signal sequence output from the complex multiplier 8 are input to determiners 9 and 10, respectively, where they are determined, and the P-channel determination signal and the Q-channel determination signal are output. After that, while being output to the output terminals 14 and 15, it is supplied to the phase error detector 11 and the decision feedback equalizer 31.

The decision units 9 and 10 output the P-channel error signal and the Q-channel error signal to the phase error detector 11, respectively. The phase error detector 11 receives the above-mentioned input P-channel determination signal, Q-channel determination signal, P-channel error signal and Q-channel error signal as input signals, and outputs the carrier wave of the baseband complex modulation signal and the digital VCO 13. Phase error with the recovered carrier wave.

The phase error detection signal output from the phase error detector 11 is input to a loop filter 12, integrated, smoothed and applied to a digital VCO 13 as a control voltage. It is controlled to synchronize with the carrier of the complex modulation signal of the band. Therefore, the digital VCO 13 outputs a reproduced carrier wave synchronized with the carrier wave of the baseband complex modulation signal.

As described above, in the other example of the conventional carrier recovery system shown in FIG. 3, the complex multiplier 8 for synchronous detection is connected to the output side of the decision feedback equalizer 31 and the decision units 9 and 1.
It is arranged between 0 input sides. This is because synchronous detection must be performed before input to the determiners 9 and 10 in order to make a correct determination.

[0025]

Among the above-mentioned conventional carrier recovery systems, the former carrier recovery system shown in FIG. 2 includes a decision feedback equalizer 31 in a phase locked loop. The internal delay becomes large and a phase locked loop with a fast response cannot be formed. Further, since the VCO 17 is configured by an analog circuit, it is necessary to adjust the circuit.

On the other hand, in the latter carrier recovery system shown in FIG. 3, the synchronous detection based on the recovered carrier is performed by the decision feedback equalizer 31.
In order to perform between the output side of and the input sides of the decision units 9 and 10, the decision signals obtained by the decision units 9 and 10 determining the signal equalized by the decision feedback equalizer 31 A complex multiplier 8 for synchronous detection is arranged in a loop that returns to the equalizer 31.

However, since the decision feedback equalizer 31 needs to output a signal after equalization and perform the process of equalizing using the signal which is decision feedback, at the symbol interval T, this decision feedback loop In the latter conventional method in which the delay of the complex multiplier 8 is added, high-speed operation becomes difficult, and there is a problem that it cannot be applied to a communication method having a high transmission rate. SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has as its object to provide a carrier recovery system based on all digital processing which forms a fast response phase locked loop and can be applied to a communication system having a high transmission rate. .

[0028]

According to the present invention, an input digital modulation signal is received as an input signal, and the input digital modulation signal is based on a local signal having a frequency substantially equal to a carrier of the input digital modulation signal. A quadrature quasi-synchronous detector that converts the frequency to a complex modulated signal in a band, an A / D converter that converts the output complex modulated signal of the quadrature quasi-synchronous detector to a digital signal, and an output digital signal of the A / D converter Perform forward equalization processing on the
A forward equalizer having a configuration of a forward type transversal filter, a complex multiplier for multiplying the output digital signal of the forward equalizer with a reproduced carrier to perform synchronous detection, and an output synchronous detection signal of the complex multiplier is a decision signal. is input with, by synthesizing the respective signals obtained by filtering the determination signal and the synchronous detection signal and an adder, the line now equalization processing for synchronous detection signal, the rear configuration of the transversal filter Bas Kkuwado type An equalizer, a determiner that generates and outputs a determination signal based on the equalized signal extracted from the rear equalizer, and generates and outputs an error signal; and a determiner.
Based on the judgment signal and error signal
The position of the carrier of the complex modulated signal in the band and the recovered carrier
A phase error detector for detecting a phase error, and a phase error detector.
A loop filter for smoothing the output phase error detection signal,
Receives the output signal of the loop filter as a control voltage, and
Outgoing signal synchronized with carrier of sband complex modulated signal
Frequency output to output to a complex multiplier as
And a decision feedback loop between the decision unit and the rear equalizer.
It is a configuration consisting only of

[0029]

As described with reference to FIG. 4, the decision feedback equalizer includes a front equalizer and a rear equalizer, and the digital signal subjected to the front equalization processing by the front equalizer is transmitted to the rear equalizer. This is a configuration in which input and equalization processing are performed. Therefore, in the present invention, the decision feedback equalizer is separated into a forward equalizer and a backward equalizer, and a complex multiplier for synchronous detection is arranged between the forward equalizer and the backward equalizer. It was done.

The backward equalizer is a backward type transversal filter that combines the signal obtained by filtering the decision signal and the synchronous detection signal from the complex multiplier by an adder and outputs the combined signal to the decision unit. Therefore, the output synchronous detection signal of the complex multiplier is output to the decision unit immediately after being synthesized by the adder without being delayed in the backward equalizer. Therefore, the delay of the carrier in the phase locked loop does not increase. Further, since the decision signal is directly input to the backward equalizer, it is possible to prevent a delay such as a complex multiplier from being added to the decision feedback loop.

[0031]

FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, the same components as those of FIG.
The description is omitted. In FIG. 1, the decision feedback equalizer 102 is separated into a forward equalizer 21 and a backward equalizer 22, and a complex multiplier 18 is disposed therebetween. Also,
The configuration is such that the output determination signals of the determiners 9 and 10 are input to the backward equalizer 22.

Next, the operation of this embodiment will be described.
The real part digital signal sequence and the imaginary part digital signal sequence extracted from the A / D converters 6 and 7 are input to the forward equalizer 21. Although the forward equalizer 21 has a two-dimensional configuration, basically, the one-dimensional forward equalizer 2 shown in FIG.
Similarly to 01, a forwarder including a plurality of delay units at symbol intervals T, a plurality of multipliers for multiplying the output signals of the delay units and the tap coefficients, and an adder for respectively combining the output signals of the plurality of multipliers Transversal filter.

The real part digital signal sequence and the imaginary part digital signal sequence that have been subjected to the forward equalization processing by the forward equalizer 21 are supplied to a complex multiplier 18 where the carrier regenerator 10
The signal is synchronously detected by being multiplied by the reproduced carrier wave from the digital VCO 13 in 3 and converted into a P-channel digital signal sequence and a Q-channel digital signal sequence.
The P-channel digital signal sequence and the Q-channel digital signal sequence that are synchronously detected and extracted by the complex multiplier 18 are input to the backward equalizer 22.

Although the rear equalizer 22 has a two-dimensional configuration, it is basically one-dimensional rear equalizer 202 shown in FIG.
Similarly, a plurality of delay units having a symbol interval T, a plurality of multipliers for multiplying the output signal of the delay unit and the tap coefficient, a first adder for respectively combining the output signals of the plurality of multipliers, A signal obtained by filtering the decision signal extracted from the first adder and a P-channel digital signal sequence and a Q-channel digital signal sequence synchronously detected by the complex multiplier 18 are added by a second adder and output. In the transversal filter, a backward equalization process is performed, and a digital signal sequence that has been subjected to an intersymbol interference equalization process is output together with the forward equalization process.

The equalized P-channel digital signal sequence and Q-channel digital signal sequence extracted from the backward equalizer 22 are input to decision units 9 and 10, respectively, where they are discriminated, and a P-channel decision signal and a Q-channel decision signal are determined. After that, while being output to the output terminals 14 and 15, it is supplied to the phase error detector 11 and the rear equalizer 22, respectively.

The P-channel and Q-channel error signals extracted from the decision units 9 and 10 (which are
And 10 are signals indicating errors between the input signal and the output determination signal. ) Denotes the phase error detector 1 in the carrier regenerator 103.
1 is supplied. Then, a reproduced carrier synchronized with the carrier of the signal input from the digital VCO 13 to the complex multiplier 18 is generated and output to the complex multiplier 18.

As described above, according to the present embodiment, the decision unit 9
And 10, the carrier regenerator 103, the complex multiplier 18, and the backward equalizer 22 to perform a carrier phase locked loop (PLL).
, And reproduces the carrier, so that the backward equalizer 22 is included in the phase locked loop of the carrier.

However, as described above, the backward equalizer 22 filters the signal obtained by filtering the determination signals from the determiners 9 and 10 and the synchronously detected P-channel digital signal sequence and Q-channel digital signal from the complex multiplier 18. A P-channel digital signal sequence and a Q-channel digital signal sequence which are synchronously detected by a transversal filter which adds the sequence and a second adder and outputs the resultant signal after the inter-symbol interference is equalized by the second adder. It is immediately output as a signal after equalization.

Therefore, the carrier does not pass through the delay unit in the rear equalizer 22, so that the delay of the carrier in the phase locked loop does not increase. Therefore, according to the present embodiment, the first type shown in FIG.
In addition to the fact that a phase locked loop having a faster response can be formed as compared with the conventional method, the delay of the rear equalizer 22 does not increase in comparison with the second conventional method shown in FIG. Therefore, according to the present embodiment, a phase-locked loop with a fast response can be formed.

The decision feedback loop which decides the signal after equalization by the decision units 9 and 10 and feeds back the decision signal to the decision feedback equalizer in the present embodiment is connected to the decision units 9 and 10 in the backward direction. 3 does not include a complex multiplier in the decision feedback loop, unlike the conventional system of FIG. 3, and therefore, in the present embodiment, the complex multiplier 18 of the prior art shown in FIG. High-speed operation becomes possible as compared with the system. Therefore, according to the present embodiment, it can be applied to a communication system with a high transmission rate.

Further, according to the present embodiment, all of the decision feedback equalizer 102, the complex multiplier 18, the carrier regenerator 103, the decision units 9, 10 and the like can be performed by digital signal processing. Large-scale integrated circuits (LSI
) Can be easily performed, and when an LSI is used, miniaturization and no adjustment can be performed.

[0042]

As described above, according to the present invention,
By separating the decision feedback equalizer into a forward equalizer and a backward equalizer, and arranging a complex multiplier for synchronous detection between the forward equalizer and the backward equalizer, the carrier Can be prevented from increasing, and a delay such as a complex multiplier can be prevented from being added to the decision feedback loop, so that a fast-locking phase-locked loop can be formed and combined. A carrier recovery system that can be applied to a communication system with a high transmission rate can be realized without lowering the operation speed of the decision feedback equalizer. Further, according to the present invention, since it is easy to implement the LSI, there is a feature that the miniaturization and the non-adjustment by the LSI can be easily performed.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of a carrier recovery system according to the present invention.

FIG. 2 is a block diagram of an example of a conventional system.

FIG. 3 is a block diagram of another example of the conventional system.

FIG. 4 is a diagram showing a basic circuit for explaining the operation of the decision feedback equalizer.

[Explanation of symbols]

 Reference Signs List 1 input terminal 2 local oscillator 3 phase shifter 4, 5 multiplier 6, 7 A / D converter 9, 10 decision unit 11 phase error detector 13 digital voltage controlled oscillator (VCO) 18 complex multiplier 21 forward equalizer 22 Back Equalizer 101 Quadrature Quasi-Synchronous Detector 102 Decision Feedback Equalizer 103 Carrier Regenerator

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04L 27/227 H03H 15/00 H03H 17/00 601 H04B 3/06 H04L 27/38

Claims (1)

(57) [Claims] 1. An orthogonal quasi-synchronization for receiving an input digital modulation signal as an input signal and frequency-converting the input digital modulation signal into a baseband complex modulation signal by a local signal having a frequency substantially equal to a carrier of the input digital modulation signal. A detector, an A / D converter for converting an output complex modulated signal of the quadrature quasi-synchronous detector into a digital signal, and a forward type for performing a forward equalization process on the output digital signal of the A / D converter A forward equalizer having a configuration of a transversal filter, a complex multiplier for performing synchronous detection by multiplying an output digital signal of the forward equalizer with a reproduced carrier, and a synchronous detection signal output from the complex multiplier as a decision signal By synthesizing the signal obtained by filtering the determination signal and the synchronous detection signal by an adder,
Line Now equalization processing for synchronous detection signal, the configuration of the rear equalizer of the transversal filter Bas Kkuwado shaped, the determination signal based on the equalized signal taken out from the aft equalizer And a determiner for generating and outputting an error signal, and a determination unit based on the determination signal and the error signal extracted from the determination unit.
The carrier wave and the reproduction of the baseband complex modulated signal.
A phase error detector for detecting a phase error with a carrier, and smoothing an output phase error detection signal of the phase error detector
A loop filter and an output signal of the loop filter as a control voltage,
The source synchronized with the carrier of the baseband complex modulated signal
Output to the complex multiplier as the reproduced carrier.
That the variable frequency oscillator and have a, the decision feedback loop-format
A carrier recovery method characterized by comprising only a constantizer and a rear equalizer .