JPS60141155U - hybrid circuit - Google Patents
hybrid circuitInfo
- Publication number
- JPS60141155U JPS60141155U JP1984027083U JP2708384U JPS60141155U JP S60141155 U JPS60141155 U JP S60141155U JP 1984027083 U JP1984027083 U JP 1984027083U JP 2708384 U JP2708384 U JP 2708384U JP S60141155 U JPS60141155 U JP S60141155U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- flat package
- board
- terminals
- hybrid circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Multi-Conductor Connections (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来の混成回路の説明図、第２図は本考案の混
成回路に用いられるバッフアートディレーラインの回路
図、第３図、考４図、第７図は本考案の混成回路の実施
例を示す説明図、第５図と第６図は本考案の混成回路の
部分斜視図である。
１：入力端子、２・３・４・５・６：出力端子、１０ニ
ー基板、１１：フラットパッケージ、１２・１３：導体
パターン、１４：底面、１５・１６：水平部分、ＩＡ〜
６Ａ：外部端子、０１〜Ｇ５：ＴＴＬ素子、Ｊｌ・Ｊ２
：ジャンパーリード。Figure 1 is an explanatory diagram of a conventional hybrid circuit, Figure 2 is a circuit diagram of a buffer art delay line used in the hybrid circuit of the present invention, Figures 3, 4, and 7 are diagrams of the hybrid circuit of the present invention. 5 and 6 are partial perspective views of the hybrid circuit of the present invention. 1: Input terminal, 2, 3, 4, 5, 6: Output terminal, 10 knee board, 11: Flat package, 12, 13: Conductor pattern, 14: Bottom, 15, 16: Horizontal part, IA~
6A: External terminal, 01-G5: TTL element, Jl/J2
: Jumper lead.
Claims (1)
集積回路のフラットパッケージ上に載置してあり、集積
回路と基板の回路の接続が該基板の側辺でフラットパッ
ケージの端子を介して行われており、該基板と該フラッ
トパッケージを挾んで２列に外部端子を露呈させた状態
で全体を樹脂封止しである混成回路において、フラット
パッケージの端子に接続する外部端子は該接続部分から
上側に延在した後水平に屈曲されており、該水平部分が
基板に接続する外部端子の水平部分と同じ高さにしであ
ることを特徴とする混成回路。A board on which a circuit is constructed by arranging a plurality of circuit elements is placed on a flat package of an integrated circuit, and the connection between the integrated circuit and the circuit of the board is made on the side of the board through the terminals of the flat package. In a hybrid circuit in which the board and the flat package are sandwiched together and the whole is sealed with resin with external terminals exposed in two rows, the external terminals connected to the terminals of the flat package are connected to the terminals of the flat package. 1. A hybrid circuit, which extends upwardly from a portion and then is bent horizontally, the horizontal portion being at the same height as the horizontal portion of an external terminal connected to the substrate.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984027083U JPS60141155U (en) | 1984-02-27 | 1984-02-27 | hybrid circuit |
| US06/701,211 US4656442A (en) | 1984-02-27 | 1985-02-13 | Hybrid circuit device |
| IT8547722A IT1180736B (en) | 1984-02-27 | 1985-02-25 | HYBRID CIRCUIT DEVICE |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984027083U JPS60141155U (en) | 1984-02-27 | 1984-02-27 | hybrid circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60141155U true JPS60141155U (en) | 1985-09-18 |
| JPH0129979Y2 JPH0129979Y2 (en) | 1989-09-12 |
Family
ID=30523699
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1984027083U Granted JPS60141155U (en) | 1984-02-27 | 1984-02-27 | hybrid circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60141155U (en) |
-
1984
- 1984-02-27 JP JP1984027083U patent/JPS60141155U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0129979Y2 (en) | 1989-09-12 |
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