JPS60136991A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To attain high speed operation with a simple circuit constitution by connecting electrically a bit line and an input/output data line with a column selection signal and connecting a sense input/output line and the input/output data line electrically with a control signal. CONSTITUTION:When the potential of D, D is established by a sense input circuit 6, a data is transferred to bit lines B, B through a column selection circuit 4 with a column selection signal Y. In case of precharge at write, when a signal of the input/output data lines D, D is outputted from the column selection circuit 4, the bit line is brought into a high impedance state. The drive capability at write is increased by inputting a signal phi3 by a latch circuit 3 when the potential of the data to be written in a memory cell is established. The load capacitance of the bit line is decreased, the precharge time is decreased and the access time is quickened, and since the bit line only selected as the column is supplied with the electric charge for the precharge from a power supply line, low power consumption is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a semiconductor memory that can be used to speed up the sense amplifier of a static random access memory (hereinafter referred to as SRAM).Conventional structure and problems thereof In the read operation of SRAM, by inputting an address, the row decoder and column decoder generate a selection signal, read the data of the memory cell group corresponding to the address to the bit line, and read the data to the bit line. The data is amplified by a sense amplifier and the data of the memory cell is output to the output buffer. On the other hand, in a write operation, the data given to the input/output buffer is transferred to the bit line by the sense amplifier, and the data is written according to the input address.
Writing is performed by selecting a memory cell group and supplying the bit line potential to the memory cells.

Conventionally, various circuit formats have been proposed to speed up access time. FIG. 1 shows the circuit configuration of a conventional SRAM. In FIG. 1, 1 is a precharge circuit, 2 is a memory cell, 1o is a sense amplifier, 11
is a latch circuit, and 12 is a buffer.

X is a row selection signal, Y, Y are column selection signals, B, B are bit line data signals, DIN, DIN are input data signals, Dovr is an output data signal, φP is a precharge signal, φL is a latch signal .

The operation shown in FIG. 1 will be explained below. First, in a read operation, when an address is input, a change in the address is detected and a precharge signal φP is generated.
Precharge B. B.

When precharging is completed, a row selection signal state, and the potentials of B and B change according to the data Da and Da of the selected memory cell 2.

When a potential difference occurs between the data signals B and H on the bit line,
The latch signal φL is changed from n L II to H''.

The latch circuit 11 receives B by the latch signal φL.

It operates by lowering the lower potential to L II and holding the higher potential at "H".

The data signal B on the bit line is amplified by the buffer 12 and becomes a sense amplifier output signal as Dayτ using the column selection signals Y and Y. However, in read operation, DIN
, DIN must be set to "L".

On the other hand, in a write operation, when an address is input, a change in the address is detected, a precharge signal φP is generated, and the bit lines B and B are precharged. When precharging is completed, one of the bit lines is set to °l by the column selection signal YK depending on the states of the input data signals Dn+ and DIH.
L II and the other are set to °IHI''.Then, the transfer gate of the memory cell 2 is opened by the row selection signal X, data B on the bit line is transferred to the memory cell 2, and a write operation is performed.

In order to reduce power consumption in SRAM, as the bit capacity increases, peripheral circuits are replaced with complementary MO8 circuits (
(hereinafter referred to as CMO3). However, as a problem caused by converting the peripheral circuit to 0MO8, -1
) increase in the number of circuit elements; 2) countermeasures against latch-up phenomena; and 3) increase in chip area of peripheral circuits.

In particular, in the system where a sense amplifier is provided for each bit line as shown in Figure 1, the P-channel MO8FKT and N-channel MO8FICT must be placed close to each other, so the layout of the mask pattern must be very carefully designed. No.

Further, since a sense amplifier is provided for each bit line, the horizontal size of the memory cell restricts the horizontal size of the sense amplifier circuit, so the mask pattern of the sense amplifier becomes long in the vertical direction.

As a result, parasitic resistance and parasitic capacitance due to wiring etc. increase, which becomes a factor that slows down access time. Furthermore, there are three data input/output signal lines (Dovτ.

Since wiring for DIN and DIN is required, there is a problem in mask layout.

Purpose of the Invention The present invention provides a sense amplifier for reading data from and writing data to an SRAM with a simple circuit configuration.
The present invention provides a semiconductor memory that can operate at high speed.

Structure of the Invention The present invention includes means for electrically connecting a bit line and an input/output data line using a column selection signal, and means for applying a signal to a sense input/output line according to a signal on the input/output data line using a first control signal. , the sense input/output line and the input/output data line are connected to a second
This semiconductor memory is characterized in that it is configured to include a means for electrically connecting it by means of a control signal.

Description of examples FIG. 2 is a block configuration diagram according to an embodiment of the present invention.

In Fig. 2, 1, 1' are precharge circuits, 2, 2
' is a memory cell, 3 and 3' are latch circuits, 4 and 4' are column selection circuits, 5 is a sense output circuit, 6 is a sense input circuit,
7 is a human output buffer.

B, B, B', B- are bit lines, D, D are input/output data lines, S, S are sense input/output lines, Ilo is input/output terminal, X
is a row selection signal, Y and Y are column selection signals, φ1 is a control signal for transferring the D signal to S, and φ1 is used during reading.
2 is a control signal for transferring the S and S signals to D during writing, φ3 is a control signal for latching bit line data to latch circuits 3 and 3' during reading, and φ4 is a control signal for s , s is a control signal for precharging s, φ5 is a control signal for setting Ilo to a non-impedance state during writing, and φ6 is a control signal for precharging Ilo during writing.
The control signal -φ7 for inputting data is connected to bit line B
, B is a control signal for precharging.

FIG. 3 shows a specific circuit configuration of each block in FIG. 2, and the same parts as in FIG. 2 are given the same numbers.

FIG. 4 shows a specific circuit configuration of the input/output buffer shown in FIG. The operations in FIGS. 2, 3, and 4 will be explained.

The operation will be described below with reference to the drawings. When reading without switching, when an address is input, a change in the address is detected and various control signals are generated. First, control signal φ7
As a result, the MOSFET of the precharge circuit 1 is turned on on the Leavitt line B.

(2) Precharge to a potential near VDD. When the precharge is completed, the MOS of the precharging circuit 1 is
Bit line B with FET off.

is in a high impedance state. Next to the control signal of φ7, the row selection signal Transferred to B and B.

As a result, the potentials of bit lines B and B, which were in a high impedance state, begin to change to the potentials of Da and Da. A control signal φ3 is inputted to the latch circuit 3 at the time when a certain level of potential difference between the bit lines B and B is generated. In the latch circuit 3, one bit line that has changed to the 'L' side is suddenly changed to 'L'.
It has been lowered to

As a result, the other bit line is held at II HII by a MOSFET in the precharge circuit 1 which has one bit line as its gate and the other bit line as its drain.

When the bit line data is held in the latch circuit 3' by φ3, the column selection signal Y is transferred to the MOSFET of the column selection circuit 4.
In order to turn on the bit line data B, B is transferred to the input/output data line D through the column selection circuit 4.

When the potential of the input/output data line D is determined, the control signal φ
1 is input to the sense output circuit 5. In the sense output circuit 5, one of the sense input/output lines S and ■ is pulled down to "L''' by the control signal φ1.

Note that during reading, the control signal φ2 turns off the MOSFET of the sense input circuit 6, so the sense input circuit 6 does not operate.

In the input/output buffer 7, φ6'== lI at the time of reading
'By setting H1+, the potential of the I10 terminal is not transmitted.Furthermore, by setting φ4==IIHI+, the sense input/output lines S and S are set to a no-impedance state, and the sense input/output circuit 6 The potential of the line S,1 is fixed. S and ``transferred from the sense output circuit 6 are held by a latch circuit composed of two inverters and set to φ5-11H++, thereby outputting a signal corresponding to S and S to the I10 terminal.

On the other hand, during writing, when an address is input, changes in the address are detected and various control signals are generated. Also, input data is given to the I10 terminal. In order to put the output buffer into a high impedance state, the human output buffer 7 first sets φ5-'L". Next, by setting φ6-"L", the input data of the I10 terminal is read into the input/output buffer 7. .The read input data is φ
By setting 4=IILII, the sense input/output line S,
"Data can be transferred to.

The signal transferred to S9g by φ4 is held in the latch circuit 3 made up of two inverters. In the input/output cover sofa 7, the control signal φ4. φ5. The input data of the I10 terminal is sensed by φ6 to the input/output line S.

Transferring to g.

When the potential of the sense input/output line S9g is determined, the control signal φ
2 is input to the sense input circuit 6, and S.

" is transferred to D via the input/output data line. When writing -
Since the control signal φ1 is not input to the sense output circuit 5,
S and S are in a high impedance state.

When the potential of D is determined by the sense input circuit 6, a column selection signal Y is sent to the bit lines B and H through the column selection circuit 4.
will be forwarded to.

When the signal from the I10 terminal is transmitted to the bit lines B and B, the row selection signal X is driven and the memory cell 2 is selected. Bit line B in the selected memory cell.

0 At this time, the potentials of the bit lines B and B are fixed, and the driving capacity is greater than that of the memory cell, so the data Da and Da of the memory cell 2 are given. Precharging and latching are not particularly necessary, but when precharging, it is necessary to put the bit line in a non-impedance state when outputting the input/output data line D signal from the column selection circuit 4. Good 1-11, the latch circuit 3 can increase the drive capability during writing by inputting φ3 once the potential of the data to be written into the memory cell is determined on the bit line.

According to the above-described procedure, data at the I10 terminal can be written into the selected memory cell by combining the column selection signals according to the present embodiment. The figure shows the circuit configuration of an SRAM using a second embodiment of the present invention.

FIG. 4 differs from FIG. 3 in the method of precharging the bit lines. In FIG. 4, the control signal φ7 is a signal generated by detecting a change in the address, so when the address changes, the bit lines B and B are electrically shorted, and the load on B and B is The charges charged in the capacitors move, and due to this charge movement, the potentials of B and B become the same potential near the end of the power supply voltage.On the other hand, φ8 and φ8' are connected to the bits selected by the column selection signal Y. ...This is a control signal to precharge the 8th line, and the bit line is precharged to near the power supply voltage by φ8 and φ8', and after reaching the same potential, φB and φ7 are turned off, and the bit line goes high. The row selection signal X is driven into an impedance state, and the data of the selected memory cell 2 is output to the bit lines B and B.

On the other hand, since the bit line of memory cell 2', which has not been column selected but has been selected by the row selection signal XK, is in a high impedance state, the data in the memory cell is
However, since the column selection circuit 4' is in an off state, it is not transferred to the input/output data line D.

FIG. 6 shows an SRA configured using the third embodiment of the present invention.
Figure 6, which shows the circuit configuration of M, has a precharge circuit in which a circuit 1P consisting only of -P channel MO8FXT is arranged on one side of the memory cell 2, and a circuit 1N consisting only of H channel MO8FICT on the other side. Place it and
A precharge circuit is composed of 1P and 1NlC.

φ7. The bit line B detects the change in the address input and
Normally, if the column selection signal Y is in a non-selected state, the bit lines B and B are at the same potential.
The word line
Even if becomes "H", the data will not be rewritten.

If column selection signal Y is in the selected state, bit line B.

Since it is short-circuited for a period of II L 11 of Bld$y and at the same time short-circuited to VDD at 1N during a period of ff HII of φ7, it is precharged to a potential near VDD through 111.

At the rising edge of 77 (falling edge of φ7), bit line B
, B are in a high impedance state, and the word line
”, data Da and Dc of the memory cell 2 are output to the bit line.

In conventional SRAMs, all bit lines are precharged, but by using the method shown in Figures 4 and 5, only selected bit lines are precharged, and unselected bit lines are not charged. Since there is only a movement of charge between the pinpoint lines and no charge is supplied from the power supply line, power consumption can be reduced.

Effects of the Invention The present invention has the following advantages in converting the SRAM peripheral circuit to 0MO8: (1) Since the sense amplifier section can be composed of only one conductivity type MO8FET, the mask pattern layout can be easily done and the shape can be made compact. Therefore, it is possible to reduce the chip area, and at the same time, it is possible to reduce the parasitic resistance and parasitic capacitance due to the wiring of the sense amplifier portion, so that the access time can be increased.

(2) Since the bit line is configured to have a small load capacitance when precharging the bit line, the precharging time can be shortened and the access time can be increased.

(3) During reading, since the bit line and the sense input/output line are electrically isolated, the influence of noise received by the I10 terminal is not propagated to the bit line, making it a structure that is resistant to noise. There is.

(4) In the embodiment in which a column selection signal is used to precharge bit lines, only the bit line selected in one column is supplied with precharge charge from the power supply line.
Reduces power consumption 0

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a conventional SRAM, and FIG. 2 is a block diagram of an SRAM using the first embodiment of the present invention.
FIG. 3 is a specific circuit configuration diagram of FIG. 2, FIG. 4 is a circuit configuration diagram of an SRAM using the second embodiment of the present invention, and FIG. 6 is a circuit diagram using the third embodiment of the present invention. FIG. 2 is a circuit configuration diagram of an SRAM. 1.1'...Precharge circuit-2,2'...
...Memory cell, 3.3' River...Latch circuit, 4
, 4'゛・river/column selection circuit, 6... sense output circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person
1 @ Figure 2 Figure N3 Figure 4

Claims (1)

[Claims] means for electrically connecting the bit line and the input/output data line according to a column selection signal; means for applying a signal to the sense input/output line according to the signal on the input/output data line according to a first control signal; A semiconductor memory comprising: a line and means for electrically connecting the input/output data line by a second control signal.