JPH07244986A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To reduce the number of element data busses and to reduce electric power by performing data transfers via sense amplifiers. CONSTITUTION:When data of a low level are inputted to a latch circuit LTC101, the level of a node NDA makes a transition from high to low and the node NDB makes a trasition from a low level to a high level because the low level of the node NDA is inverted in level by an inverter INV 101-Consequently, the state of an NMOS transistor NT102 makes a transition from OFF to ON. Thus, the input side of the inverter INV 101 where the node NDA is connected is pulled in to a grounded level to be held stably at the low level and the node NDB is held at the high level. That is, a data inverse-latching is performed in the circuit LTC101. Further, when data of data busses are in the high level, the inverse-latching operation is not performed and the holding operation of levels prior to the start of writings is performed. In such a manner, the number of element data busses is reduced, operation in a low voltage is made possible and power consumption is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device such as a DRAM, and more particularly to a column selector buffer circuit for performing write / read operations.

[0002]

2. Description of the Related Art First to fourth conventional examples of column selector buffer circuits of a DRAM will be described with reference to FIGS.

FIG. 6 is a circuit diagram showing a first conventional example and shows the most basic circuit configuration. In this configuration, each bit line pair BL1 and BL1B, BL2 and BL2B, BL3 and BL3B, BL4 and BL4.
B is a sense amplifier (S / S) provided for each bit line pair.
A) NMOS transistors NT ₁₁ and NT ₁₂ , NT ₂₁ and NT ₂₂ , NT ₃₁ and NT ₃₂ , N which are connected to SNS _{1 to} SNS ₄ and serve as transfer gates.
Data bus DB1, DB1B via T ₄₁ and NT ₄₂
Directly connected to each. In addition, each bit line BL
1, BL1B, BL2, BL2B, BL3, BL3B and BL4, BL4B are arranged with orthogonal word lines (not shown), to which memory cells each consisting of a MOS transistor and a capacitor are connected.

In such a structure, for example, when data is written to the memory cells connected to the bit line pair BL1 and BL1B, the data bus pair DB1, DB1B is driven by the write buffer (not shown), If the data of the pair DB1 and DB1B is determined, only the control signal φ ₁ is set to the high level and the NMOS transistor N as the transfer gate is set.
T ₁₁ and NT ₁₂ are controlled to be conductive. As a result, the sense amplifier SNS ₁ is inverted and data is written.

When reading is performed, a desired memory cell transistor is driven via a word line (not shown), whereby the data appearing on the bit lines BL1 and BL1B are amplified by the sense amplifier SNS _1. receiving, is transmitted to the data bus DB1, DB 1 b via the NMOS transistor NT _11, NT _12, which is controlled in a conductive state by the control signal phi _1, as described above. In this read operation, the sense amplifier SNS ₁ causes the data bus DB1,
The DB1B is driven, and in order to prevent a malfunction, the NMOS transistors NT ₁₁ and N as transfer gates are opened after the bit line pair BL1 / BL1B is sufficiently opened.
T ₁₂ is controlled to be conductive.

FIG. 7 is a circuit diagram showing a second conventional example. In this circuit, NM as a transfer gate
The OS transistors NT ₁₁ , NT ₂₁ , NT ₃₁ , and NT ₄₁ are connected to the common line CML1, and the NMOS transistor N
T ₁₂ , NT ₂₂ , NT ₃₂ , and NT ₄₂ are connected to the common line CML2. Two CMOs on common lines CML1 and CML2
Two common lines, each of which is connected to two outputs of a flip-flop type latch circuit LTC ₁ which connects the input and output of the S inverter, and which is composed of three NMOS transistors and is driven and controlled by a control signal φ _P CML1,
An equalizer circuit EQC for CML2 is provided.
The common line CML1 is connected to the data bus DB via the NMOS transistor NT ₅ as a transfer gate.
1 and the common line CML2 is connected to the data bus DB1B via the NMOS transistor NT ₆ as a transfer gate.

In such a configuration, the data bus D
Since it is not necessary to consider the loads on the B1 and DB1B sides, data can be latched at high speed during reading and the data buses DB1 and DB1B can be driven. Also,
By precharging the latch circuit LTC ₁ to (1/2) V _CC , the bus is so-called TRUE / bar (B
It is not necessary to provide two (AR) and write / read operation is possible with one data bus. Further, it can be shared by a plurality of bit line pairs or a plurality of mats which are memory cell groups divided by sense amplifier groups.

FIG. 8 is a circuit diagram showing a third conventional example. In this circuit, in order to solve the problem in the read operation of the circuit of FIG.
1, BL1B, BL2, BL2B are configured to be received by the gates of the NMOS transistors NT ₁₃ , NT ₁₄ , NT ₂₃ , NT ₂₄ . And the NMOS transistor N
T ₁₃ and NT ₁₄ are NMOS transistors NT as transfer gates whose conduction is controlled by the read signal φ _1R.
15 and NT ₁₆ to be connected to the data buses DB1 and DB1B. Similarly, NMOS transistors NT ₂₃ and NT ₂₄
Is connected to the data bus DB1, DB 1 b via the NMOS transistor NT _25, NT ₂₆ as a transfer gate which is conducting controlled by the read signal phi _2R is. With such a configuration, the bit line pair BL1, BL
1B and BL2, BL2B are held at stable potentials.

FIG. 9 is a circuit diagram showing a fourth conventional example.
It This circuit is a bit line pair for reading shown in FIG.
The gate receiving method of the plurality of bit line pairs BL1, BL1
B, BL2, BL2B, BL3, BL3B and BL
4, shared by BL4B. That is, the tiger
NMOS transistor N as a transfer gate
T₁₁, NT _{twenty one}, NT₃₁, NT₄₁Connected to common line CML1
NMOS transistor NT₁₂, NT_{twenty two}, NT₃₂，
NT₄₂Is connected to the common line CML2, and the common line CML1 is
NMOS transistor NT_7aWhen connected to the gate of
The common line CML2 is the NMOS transistor NT._7bof
It is connected to the gate. And the NMOS transistor
TNT_7a, NT_7bIs the read signal φ_RIs controlled by
NMOS transistor as a transfer gate
NT_8a, NT_8bTo the data buses DB1 and DB1B via
Each is connected. Also, the common line CML1 and
CML2 is a write signal φ_WA tiger whose continuity is controlled by
NMOS transistor N as a transfer gate
T_9a, NT_9bTo the data buses DB1 and DB1B via
Each is connected. With this configuration
Each bit line pair BL1, BL1B, BL2, BL2
Read B, BL3, BL3B and BL4, BL4B
The potential is kept stable during the operation.

[0010]

However, in the above-mentioned first conventional circuit, two data buses are required to invert the sense amplifier SNS in the write operation, and in the read operation, the sense amplifier SNS is required. It is necessary to consider the load of the bus to drive the bus at, and to open the transfer gate after the bit line pair BL / BLB is sufficiently opened to prevent malfunction, and also to reset the word line, bit line pair BL / BL / High-speed operation is difficult because it needs to be performed after the BLB is sufficiently stabilized.

Further, in the second conventional circuit, since it is not necessary to consider the load on the data bus side, it is possible to latch data at a high speed at the time of reading and drive the data bus, and the latch circuit ( 1/2) precharge to V _CC to put the bus into TRUE / bar (BA
Although there is no need to provide two R), the write / read operation can be performed by one data bus, but there is a problem that the number of elements is large and the circuit area is increased.

In the third conventional circuit, the bit line pair at the time of reading can be held at a stable potential, but in consideration of the write operation, it is necessary to provide two data buses of true (TRUE) / bar (BAR). .

Further, although the fourth conventional circuit has the advantage that it is composed of only N-channel transistors and the number of elements is small and an increase in the circuit surface diagram can be prevented, there are the following problems in consideration of voltage driving. . That is, N in FIG.
The node indicated by DA or NDB becomes (V _CC -V _TH ) at the time of reading. Therefore, considering the operation at low voltage, the transfer gate of the column selector is
It is necessary to use MOS, and the number of elements in this case becomes so large that it exceeds the number of elements of the second conventional circuit of FIG.
The circuit area is large. Also, two data buses are required as in the third conventional circuit of FIG.

The bus method will be described in more detail. In the method having two lines of TRUE / BAR, the bus is equalized at the time of resetting, precharged to (1/2) V _CC , and half The swing operation has merits in terms of power consumption and operation speed. However, in consideration of the low electricity consumption in recent years or in the future, (1 /
2) We must consider the V _CC charge circuit.
At the present time, there is no circuit technology with low voltage and large supply capacity. For this reason, the method using two buses is becoming less advantageous from the viewpoint of operating margin against fluctuations in the power supply voltage.

Further, since the circuit so far has a large area, the buffer portion must be shared by many bit line pairs. For example, in the case of a specification that requires input / output of a large number of data with one access such as an image memory, there is no choice but to operate a plurality of mats simultaneously to secure a desired number of data. Since the power consumption of the dynamic memory is dominated by the charge / discharge current of the selected mat, it is a big problem that the area of the column selector imposes a restriction on the number of selected mats. As described above, in the conventional column selector circuit, each method has problems such as the number of elements, the number of data buses, a low voltage margin, and the influence on power consumption.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor memory device capable of reducing the number of elements and the number of data buses, operating at low voltage, and reducing power consumption. To do.

[0017]

In order to achieve the above object, data is transferred between a bit line pair to which a memory cell of the present invention is connected and one data bus via a sense amplifier. A semiconductor memory device that performs a write operation and a read operation of first level data or second level data of opposite phases to the memory cell is configured to detect the sense amplifier and the sense amplifier in response to input of a first control signal. Switching means for operatively connecting the amplifier and the first and second connection lines of the data bus, and the data bus and the first bus in response to the input of the second control signal.
Gate means for operatively connecting the connecting line of the
Latching means for holding the levels of the first connection line and the second connection line at the first level or the second level opposite to each other in response to the input of the control signal.

In the semiconductor memory device of the present invention, the latch means includes means for holding the level of the first connection line at one of the first level and the second level in the initial state. Have.

Further, in the semiconductor memory device of the present invention, a plurality of sense amplifiers to which a pair of bit lines are connected are connected to the first and second connection lines to the data bus via the switching means, respectively. The sense amplifier is selectively connected to the first and second connection lines according to the input of the control signal to the switching means.

[0020]

According to the semiconductor memory device of the present invention, since the write destination of the write data can be specified when the address is determined at the time of writing, after the address is determined in the write cycle, the data bus is driven by the write buffer. . When the data on the data bus is set to the second level, for example, the low level, the gate means is controlled to be conductive by the second control signal, and the data on the data bus is transferred to the first connection line. . At this time, at the same time, the third control signal of a predetermined level is input to the latch means, and the first connection line is stably held at the second level and the second connection line is stably held at the first level. Then the first
The switching means is controlled to the open state by the input of the control signal of, the data held in the latch means is transferred to the bit line pair through the sense amplifier, and the data is written to the specified memory cell by a predetermined procedure. Be seen. For example, when the data is inverted, the switching means is switched to the closed state by the first control signal to separate the bit line pair from the latch means. Then, after the bit line is sufficiently stabilized, the word line and the bit line pair are reset.

Further, at the time of reading, when the address is fixed and the word line is switched from the low level to the high level, the data is output from the memory cell to the bit line,
This data is amplified by the sense amplifier. If the data is amplified, the switching means is controlled to the open state by the input of the first control signal, and the read data output to the bit line, for example, the second level (low level) data is stored in the latch means. Transferred. At this time, at the same time, the third control signal of a predetermined level is input to the latch means, and the first connection line is at the second level (low level).
In addition, the second connection line is stably held at the first level (high level). Next, the gate means is controlled to be conductive by the second control signal, and the low-level data held on the first connection line side of the latch means is transferred to the data bus.

Further, according to the present invention, in the latch circuit, in the initial state, the level of the first connection line is the first level.
Or the second level.

Further, according to the present invention, the plurality of sense amplifiers to which the bit line pair is connected are connected to the first and second connection lines with the data bus via the switching means, respectively, and the plurality of bit lines are connected. The data bus, the latch means and the gate means are shared between the line pairs. Then, each sense amplifier is selectively connected to the first and second connection lines in response to the input of the control signal to the switching means.

[0024]

[Embodiment 1] FIG. 1 is a circuit diagram showing a first embodiment of a semiconductor memory device according to the present invention.
The same components as those in FIG. 9 are represented by the same reference numerals. That is, BL1 and BL1B, BL2 and BL2B, BL3 and B
L3B, BL4 and BL4B are bit line pairs, WL is a word line, CL ₁ and CL ₂ are DRAM cells, and SNS _{1 to} SNS.
₄ is a sense amplifier (S / A), NT ₁₁ , NT ₁₂ , N
T ₂₁ , NT ₂₂ , NT ₃₁ , NT ₃₂ , NT ₄₁ and NT ₄₂ are NM
OS transistor, CML1 and CML2 are common line, DB
Is a data bus, TFG ₁₀₁ is a transfer gate, L
TC _{10 1} indicates a latch circuit, respectively.

The NMOS transistors NT ₁₁ , NT ₂₁ , NT ₃₁ , and NT ₄₁ as transfer gates are connected to the common line C.
NMOS transistors NT ₁₂ and NT connected to ML1
₂₂ , NT ₃₂ and NT ₄₂ are connected to the common line CML2.

The transfer gate TFG _{101 operatively connects} the common line CML1 and the data bus DB in response to the input of the control signal φ _TFGP and the control signal φ _TFGN which complementarily _attain the high level and the low level. The transfer gate TFG ₁₀₁ has two input / output terminals configured by connecting sources and drains of the PMOS transistor PT ₁₀₁ and the NMOS transistor, and one input / output terminal of the transfer gate TFG ₁₀₁ is connected to the common line CM.
Is connected to L1, the other input terminal connected to the data bus DB, the gate of the PMOS transistor PT ₁₀₁ is connected to the supply line of the control signal φ _TFGP, the supply line of the gate control signal phi _TFGN of the NMOS transistor NT ₁₀₁ It is connected to the.

The latch circuit LTC ₁₀₁ has a control signal φ _LTC.
Node NDA on the common line CML1 side according to the input level of
And the node NDB on the common line CML2 side is held at high level or low level. This latch circuit LTC ₁₀₁
Is an inverter INV _{101, a} PMOS transistor PT _102, and an NMOS transistor N connected in series.
It is composed of T ₁₀₂ and NT 1 ₁₀₃ , which are connected as follows. Input of the inverter INV ₁₀₁ is connected to the drain of the common line CML1, PMOS transistor PT _{10 2} of the drain and NMOS transistor NT _102, the input is connected to the common line CML2. P
The source of the MOS transistor PT ₁₀₂ is connected to the supply line of the power source voltage V _CC , and the NMOS transistor NT ₁₀₃
Source is connected to the ground line. And NM
The gate of the OS transistor NT ₁₀₂ is connected to the supply line CML2, and the gate of the PMOS transistor PT _{102 and} the gate of the NMOS transistor NT ₁₀₃ are connected to the control signal φ.
Connected to _LTC supply line.

Next, the write and read operations with the above configuration will be described with reference to the timing charts shown in FIGS. Here, the bit line pair BL
The write and read operations for the memory cell CL ₁ connected to 1, BL1B will be described as an example.

In the initial state, the control signal φ₁Is low
NMOS transistor NT at level ₁₁And NT₁₂Ge of
Control signal φ₂Is a low level NMOS transistor
Star NT_{twenty one}And NT_{twenty two}Control signal φ to the gate of₃Is
-Level NMOS transistor NT₃₁And NT₃₂of
Control signal φ at the gate_FourIs a low level NMOS transistor
Dista NT₄₁And NT₄₂Is supplied to each gate
It As a result, each NMOS transistor is kept off.
Held, each bit line pair BL1, BL1B, BL2, BL
2B, BL3, BL3B, BL4, BL4B and latch times
Road LTC₁₀₁Are separated. In addition, the control signal φ_TFGP
Is at high level and PMOS transistor PT₁₀₁The gate of
Supplied to the control signal φ_TFGNIs low level
Langista NT₁₀₁Is supplied to the gate. as a result,
Transfer Gate TFG₁₀₁Is kept non-conducting
Data bus DB and latch circuit LTC₁₀₁Separated from
Has been.

First, the write operation will be described with reference to FIG. Before the start of writing, as shown in FIG. 2, the data bus DB is precharged to the power supply voltage V _CC level, and the control signal φ _LTC is held at the low level.
As a result, the PMOS transistor PT ₁₀₂ is held in the ON state, and the node NDA is at the high level (V _CC level).
In addition, the node NDB is fixed to the low level.

Since the write destination of the write data can be specified by determining the address, the data bus DB is driven by the write buffer (not shown) after determining the address in the write cycle. If the data of the data bus DB is fixed to, for example, the low level, the control signal φ _TFGN is set to the high level and the control signal φ _TFGP is set to the low level, and the NMOS of the transfer gate TFG ₁₀₁ is set.
It is supplied to the gate of the transistor NT _{101 and} the gate of the PMOS transistor PT ₁₀₁ , respectively. As a result, the transfer gate TFG ₁₀₁ becomes conductive, and the data on the data bus DB is transferred to the latch circuit LTC ₁₀₁ through the common line CML1. At the same time, the control signal φ _LTC for the latch circuit LTC ₁₀₁ is switched from low level to high level, and the gate of the PMOS transistor PT ₁₀₂ and the NMOS transistor NT ₁₀₃ are switched.
Is supplied to the gate. As a result, the PMOS transistor PT _{102 changes} to the off state, and the NMOS transistor NT _{103 changes} to the on state.

In this state, when low level data is input to the latch circuit LTC ₁₀₁ , the node NDA transits from high level to low level, and the node N on the common line CML2 side.
As for DB, the high level of the node NDA is the inverter INV.
_{Since the} level is inverted at ₁₀₁ , the low level transits to the high level. As a result, the NMOS transistor NT
₁₀₂ transits from the off state to the on state. This allows
The input side of the inverter INV ₁₀₁ to which the node NDA is connected is pulled to the ground level and stably held at the low level, and the node NDB is stably held at the high level. That is, the latch circuit LTC ₁₀₁ performs data inversion latch. When the data on the data bus DB is at the high level, the inversion latch operation is not performed and the level holding operation before the writing is started is performed.

Next, the control signal φ ₁ is set to a high level and supplied to the gates of the NMOS transistors NT ₁₁ and NT ₁₂ as transfer gates. As a result, N
The MOS transistors NT ₁₁ and NT ₁₂ are turned on,
The transfer operation of the latched write data of the latch circuit LTC ₁₀₁ to the bit line pair BL1, BL1B is performed.
In the write operation, the node NDA is connected to one bit line BL.
And the data bus DB via the transfer gate TFG ₁₀₁ and the write buffer (not shown) ahead of the data bus DB, and the other bit line BL1B is connected to the inverter INV ₁₀₁ of the latch circuit LTC _{10 1} by a sense amplifier if necessary. This is done by reversing SNS ₁ . When the data is inverted, the control signal φ ₁ is switched from the high level to the low level, the NMOS transistors NT ₁₁ and NT ₁₂ are controlled to the off state, and the bit lines BL1 and BL1B and the latch circuit LTC ₁₀₁ are separated. . Then, after the bit lines BL1 and BL1B are sufficiently stabilized, the word line WL and the bit lines BL1 / BL1B are reset.

Next, the read operation will be described with reference to FIG. When the address is fixed and the word line WL is switched from the low level to the high level, the memory cell CL
Data is output to bit lines BL1 and BL1B from ₁ .
This data is amplified by the sense amplifier SNS ₁ . When the data is amplified, the control signal φ ₁ is set to the high level and supplied to the gates of the NMOS transistors NT ₁₁ and NT ₁₂ as transfer gates. As a result, the NMOS transistors NT ₁₁ and NT ₁₂ are turned on, and the read data output to the bit lines BL1 and BL1B are transferred to the nodes NDA and ND of the latch circuit LTC _101.
Transferred to B. At this time, at the same time, the control signal φ _LTC for the latch circuit LTC ₁₀₁ is switched from low level to high level and supplied to the gate of the PMOS transistor PT _{102 and} the gate of the NMOS transistor NT ₁₀₃ . As a result, the PMOS transistor PT _{102 changes} to the off state, and the NMOS transistor NT _{103 changes} to the on state.

In this state, when low level data is input to the node NDA of the latch circuit LTC ₁₀₁ , the node N
DA changes from high level to low level, and the common line CM
The node NDB on the L2 side transitions from the low level to the high level because the high level of the node NDA is inverted by the inverter INV ₁₀₁ . As a result, NMOS
Transistor NT ₁₀₂ transitions from the off state to the on state. As a result, the input side of the inverter INV ₁₀₁ connected to the node NDA is pulled to the ground level,
It is stably held at the low level and the node NDB is stably held at the high level. That is, the latch circuit L
In TC ₁₀₁ , data inversion latch is performed. In addition,
When the data on the bit line BL1 is at the high level, the inverting latch operation is not performed and the level holding operation before the start of reading is performed.

Next, the control signal φ _TFGN is set to the high level and the control signal φ _TFGP is set to the low level, and supplied to the gate of the NMOS transistor NT ₁₀₁ of the transfer gate TFG ₁₀₁ and the gate of the PMOS transistor PT ₁₀₁ , respectively. As a result, the transfer gate TFG ₁₀₁ becomes conductive, and the data at the node NDA of the latch circuit LTC ₁₀₁ is transferred to the data bus DB.
At this time, since the data bus DB is precharged to the power supply voltage V _CC level and the read data is at the low level, the PMOS transistors PT ₁₀₁ , NMO.
It is discharged through the S transistors NT _{101 to} NT ₁₀₃ . When the read data is at high level, it is held at the same potential.

Further, in parallel with the control operation of the transfer gate TFG _{101 to} the conductive state, the control signal φ ₁ is switched from the high level to the low level, the NMOS transistors NT ₁₁ and NT ₁₂ are controlled to the off state, and the bit The lines BL1 and BL1B are separated from the latch circuit LTC ₁₀₁ . Then, the reset operation of the word line WL and the bit lines BL1 / BL1B is performed regardless of the data transfer.

Since the data transfer by the data bus DB is performed in a full swing, either the latch reception or the amplifier reception can correspond to the end of the data bus DB. Further, the setting of each transistor size is a force relationship of the sense amplifier, the load of the bit line, and the force of the latch circuit LTC ₁₀₁ via the transfer gate for writing. In addition, it may be set in consideration of the supply capacity of the data bus DB via the transfer gate and the write buffer not shown. For writing, the latched data may be set stable when the transfer gate TFG ₁₀₁ is in a conductive state, and the data bus DB may be discharged within a set time.

As described above, according to this embodiment,
Control signal φ for one data bus DB and common line CML1
Transfer gate TFG _{101 that} is operatively connected according to the inputs of _TFGP and φ _TFGN , and node NDA is kept at a high level in the initial state according to the input of control signal φ _LTC , and node NDA is written during the write or read operation. A latch circuit LTC ₁₀₁ which holds the data level or the read data level and holds the node NDB at the opposite phase level, and the sense amplifiers SNS _{1 to} SNS.
₄ and the latch circuit LTC ₁₀₁ are selectively connected to the control signals φ _{1 to} φ ₄ by an NMOS transistor NT.
₁₁ , NT ₁₂ , NT ₂₁ , NT ₂₂ , NT ₃₁ , NT ₃₂ , N
By providing T ₄₁ and NT ₄₂ , the number of data buses can be minimized to one, and full swing drive can be surely realized even at a low voltage, and can be shared between bit line pairs and mats. . Further, since it can be realized with a small number of elements such as seven elements, there is a degree of freedom in the mat structure. Therefore, the present semiconductor memory device is an optimum circuit as a column selector buffer for future low-electricity dynamic memories, especially image memories.

[0040]

Second Embodiment FIG. 4 is a circuit diagram showing a second embodiment of the semiconductor memory device according to the present invention. The present embodiment is different from the above-described first embodiment in that the PMO transistor PT ₁₀₂ for initializing the so-called latch circuit for keeping the node NDA at the power supply voltage level in the initial state is deleted, and the transfer gate TFG is initialized at the time of initialization.
_{The configuration is such that 101} is controlled to be conductive and the level of the node NDA is fixed via the data bus DB.

According to this embodiment, not only the effect of the first embodiment described above can be obtained, but also the circuit area can be further reduced.

[0042]

Third Embodiment FIG. 5 is a circuit diagram showing a third embodiment of the semiconductor memory device according to the present invention. This embodiment is different from the above-described second embodiment in that the transfer gate TFG ₁₀₁
Is constituted by only the NMOS transistor NT ₁₀₁ . In such a configuration, the low voltage margin becomes worse, but the precharge level of the data bus becomes (V
_CC- V _TH ), which can reduce the number of elements in addition to the effect of the second embodiment described above.

[0043]

As described above, according to the present invention,
A semiconductor memory device that can reduce the number of elements and the number of data buses, can operate at a low voltage, and can reduce power consumption can be realized.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a semiconductor memory device according to the present invention.

FIG. 2 is a timing chart for explaining a write operation of the circuit of FIG.

FIG. 3 is a timing chart for explaining a read operation of the circuit of FIG.

FIG. 4 is a circuit diagram showing a second embodiment of the semiconductor memory device according to the present invention.

FIG. 5 is a circuit diagram showing a third embodiment of the semiconductor memory device according to the present invention.

FIG. 6 is a circuit diagram showing a first conventional example of a semiconductor memory device.

FIG. 7 is a circuit diagram showing a second conventional example of a semiconductor memory device.

FIG. 8 is a circuit diagram showing a third conventional example of a semiconductor memory device.

FIG. 9 is a circuit diagram showing a fourth conventional example of a semiconductor memory device.

[Explanation of symbols]

BL1, BL1B, BL2, BL2B, BL3, BL3
B, BL4, BL4B ... bit line pair WL ... word lines CL _1, CL ₂ ... DRAM cell SNS ₁ ~SNS ₄ ... sense amplifier _{(S / A) NT 11,} NT 12, NT 21, NT 22, NT 32, NT ₄₁ , N
T ₄₂ ... NMOS transistors CML1, CML2 ... Common line DB ... Data bus TFG ₁₀₁ , TFG _101a ... Transfer gate PT ₁₀₁ ... PMOS transistor NT ₁₀₁ ... NMOS transistor LTC ₁₀₁ , LTC _101a ... Latch circuit PT ₁₀₂ ... PMOS transistor NT ₁₀₂ , NT ₁₀₃ … NMOS transistor INV ₁₀₁ … Inverter

Claims (3)

[Claims] 1. A bit line pair and 1 to which a memory cell is connected.
By transmitting and receiving data to and from the data bus of a book via a sense amplifier, a semiconductor memory device that performs writing and reading operations of data of the first level or the second level of mutually opposite phases to the memory cell In addition, according to the input of the first control signal, the sense amplifier,
Switching means for operatively connecting the sense amplifier and the first and second connection lines of the data bus, and actuating the data bus and the first connection line in response to input of a second control signal. And a latching means for holding the levels of the first connection line and the second connection line at the first level or the second level opposite to each other in response to the input of the third control signal. And a semiconductor memory device having. 2. The semiconductor memory according to claim 1, wherein said latch means has means for holding the level of said first connection line at one of a first level and a second level in an initial state. apparatus. 3. A plurality of sense amplifiers to which a pair of bit lines are connected are respectively connected to the first and second connection lines with the data bus via switching means, and each sense amplifier is connected to the switching means. 3. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is selectively connected to the first and second connection lines according to the input of a control signal.