JP2643298B2 - Device and method for driving sense amplifier for semiconductor memory - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a driving device and a driving method of a sense amplifier circuit used in a semiconductor memory.
The present invention relates to a device for reducing a charge / discharge current of a power supply and a ground circuit during a sensing operation.

[Prior Art] FIG. 3 is a diagram schematically showing the overall configuration of a read section of a dynamic random access memory conventionally used and to which the present invention is applied.
Is a memory cell array in which a plurality of the following memory cells for storing information are arranged in rows and columns, and AB is an address buffer, which generates an internal address in response to an external address given from the outside.

ADX is an X decoder which decodes an internal address signal from the address buffer AB and selects a corresponding row of the memory cell array MA. ADY is a Y decoder, which decodes an internal address from the address buffer AB,
The corresponding column of the memory cell array MA is selected.

SI is (sense amplifier + I / O), and detects information of the following memory cell selected in the memory cell array MA,
The signal is amplified and transmitted to the following output buffer in response to a signal from the Y decoder ADY.

OB is an output buffer, SI (sense amplifier + I / O)
And outputs output data Dout in response to the read data transmitted from.

CG is a control signal generation system peripheral circuit.
Control signals (V _B , _RN , φ _E , φ _P , φ _S) for controlling the timing of various operations of the random access memory
φ _R ).

FIG. 4 is a diagram schematically showing the configuration of the memory cell array section shown in FIG. In the figure, WL ₁ , WL ₂ ,... WL
_n word _{lines, BL 0, ▲ ▼ 0,} BL 1, ▲ ▼ 1, ...... BL m,
▲ ▼ _m is a bit line.

_{One of} the following memory cells is connected to each of the word lines WL ₁ ,..., WL _n . The bit lines BL ₀ ,..., BL _{m form} a folded bit line, and the two bit lines form one bit line pair.

That is, the bit lines BL ₀ , ▼ ₀ constitute a pair of bit lines, and the bit lines BL _m , ▼ _m constitute a bit line pair in the same manner. (1) Each bit line BL ₀ be a memory cell for storing information, a memory cell (1) is connected to a cross point of a word line of every other in ...... ▲ ▼ _m. That is,
In each bit line pair, a memory cell (1) is located at the intersection of one word line and one of the bit lines of the pair of bit lines.
Are connected. (150) is a precharge / equalize circuit that balances the potential of each bit line pair,
And for precharging to a predetermined potential V _B, it is provided for each bit line pair. (14) is the first signal line, (17)
Is a second signal line, and (50) is a sense amplifier. The sense amplifier (50) is provided for each bit line pair and is transmitted through the first and second signal lines (14) and (17). Activated in response to the first and second signals φ _A and φ _B for driving the sense amplifier (50) to be detected, the potential difference between the connected bit line pair is detected and differentially amplified. I / O, ▲ ▼ data output _{bus, T 0, T 0 ',} ...... T m, T m' is the transfer gates, the bit lines BL _0, ...... ▲ ▼ _m is, Y decoder AD
In response to the address decode signal from Y, transfer gates T ₀ , T ₀ ′,..., T _m , T _m ′ are selectively connected to the data input / output bus I / O, ▲ ▼. That is, the bit line BL
₀ , ▲ ▼ ₀ are connected to data input / output bus I / O, ▲ ▼ via transfer gates T ₀ , T ₀ ′, respectively.
Similarly, bit lines BL ₁ , ▲ ▼ ₁ are connected to data input / output bus I / O, ▲ via transfer gates T ₁ , T ₁ ′, respectively.
▼ connected to the bit line BL _m, ▲ ▼ _m each transfer gate T _m, via the T _m 'data output bus I / O, is connected to ▲ ▼.

An address decoder signal from the Y decoder ADY is transmitted to the gates of the transfer gates T ₀ , T ₀ ′,..., T _m , T _m , whereby the pair of bit lines is connected to the data input / output bus I. / O, ▲ ▼ will be connected.

FIG. 5 is a circuit diagram of a sense amplifier driving device of a dynamic random access memory showing one embodiment of the related art connected to a pair of bit lines of the bit line pair shown in FIG.

In the figure, (2) and (7) are bit lines, (3) is a word line, (4) is a storage node of the memory cell (1),
(5) is a selection transistor of the memory cell (1),
An n-channel insulated gate field effect transistor (hereinafter referred to as n
−FET), the gate of which is a word line (3)
The source is connected to the bit line (2).
(6) is a memory capacity for storing information of the memory cell (1), one of which is connected to the drain of the selection transistor (5) via the storage node (4), and the other is connected to the ground line described below. . (8) is a power supply line for the bit lines (2) and (7), to which a constant voltage of about half of the power supply voltage is supplied. (9) and (10) are n-FETs for applying the voltage of the power supply line (8) to the bit lines (2) and (7), and (11) is an n-FET.
Signal lines for inputting signals for controlling the operation timings of (9) and (10), and (12) is an n-FET provided between the bit lines (2) and (7), and the memory cell (1) Operates at the beginning of the waiting state to balance the potentials of the bit lines (2) and (7). (13) is a signal line to which a signal for controlling the operation timing of the n-FET (12) is input, and (15) and (16) are p-channel insulated gate field-effect transistors (hereinafter referred to as p-channel transistors) constituting the sense amplifier (50). −FET), (18), (1
Reference numeral 9) denotes an n-FET constituting the sense amplifier (50). The sense amplifier (50) is a pair of gate electrodes and one of the electrodes cross-connected to the bit lines (2) and (7), respectively. P-FETs (15) and (16) and bit lines (2) and (7) where one electrode and the gate electrode are cross-connected.
And a pair of n-FETs (18) and (19) respectively connected to the N-FET. Then, the p-FET (15), (1
Receiving the other electrode are both connected to a first signal line (14) activating signal phi _A 6). Also, n-FETs (18), (1
The other electrode of 9) receives the connected activation signal phi _B to the second signal line (17). (20) and (21) are the parasitic capacitances of the bit lines (2) and (7) respectively, (22) is a p-FET for transmitting the power supply voltage to the first signal line (14), and (23) is a p-FET −FET
(22) An input terminal for a signal that controls the operation, (24)
Power supply terminal to which the power supply voltage is supplied to the signal line (14), (2
5) is an n-FE conducting between the second signal line (17) and the ground line.
T, (26), the input terminal of the signal for controlling the operation of the n-FET (25), Vcc is the power supply voltage, V _B is the bit lines (2), (7)
And is kept at 1/2 Vcc.

phi _P is n-FET (9), the operation signal for controlling the timing, phi _E is equalizing signal for controlling the timing to balance the potentials of the predetermined bit line pair, Rn is given (10),
Word line drive signal for controlling the timing for selecting a memory cell, _S, respectively _{φ s p-FET (22)} , n-FET (2
The first and second signals for controlling the operation timing of 5), G
ND is a ground line, _VTP is a threshold voltage of p-FETs (15) and (16), and V _Tn is a threshold voltage of n-FETs (18) and (19).

FIG. 6 is a timing chart for explaining the operation of the circuit configuration shown in FIG. 5. In FIG. 6, information of logic "1" is stored in the memory cell (1). The operation when reading the storage information “1” is shown.

In a period from the time t ₀ of t _1, the bit line (2), (7)
Is a power line (8) by n-FETs (9) and (10), respectively.
And its potential is held at V _B = V _CC / 2,
The potential between the two bit lines (2) and (7) is balanced by the n-FET (12). At this time, the potentials of the first and second sense amplifier driving signal lines (14) and (17) are held at V _CC / 2 + | V _TP | and V _CC / 2−V _TN , respectively.

Becomes time t _2, the control signal φ _P, φ _E goes low n-FET (9), when (10) is after the OFF, word line drive signal Rn is inputted is a time t ₃ , N-FET (5) is ON
As a result, the charge stored in the storage node (4) moves to the bit line (2), and the potential of the bit line (2) rises slightly (僅 か V). The rise value is determined by the storage voltage V ₄ of the capacitance value C ₂₀ in the parasitic capacitance of the capacitance value C ₆ and the bit lines of the memory capacity (6) (2) (20), and the storage node (4), usually 100
The value is about 200 mV.

Next, increase control signal phi _S becomes a time t _4, p-FET and phi _s is lowered (22), n-FET (25) is turned ON, the potential of the first signal line (14) is increased , The potential of the second signal line (17) starts to decrease. Then, the rise and fall of the potentials of the first and second signal lines (14) and (17) cause the p-FET
A flip-flop circuit composed of (15), (16) and n-FETs (18), (19) starts a sensing operation to amplify a small potential difference ΔV between the bit lines (2), (7).

In this case, when the potential of the bit line (2) rises by ΔV and the n-FET (19) turns on, the second signal line (1)
As the potential drops in 7), the parasitic capacitance (2
Charge stored in 1) is discharged through the n-FET (19), at time t ₅ is discharged to approximately 0 ^V.

On the other hand, due to the potential drop of the bit line (7), the p-FET (1
5) is turned on, the potential of the bit line (2) is raised to the V _CC level, and the storage node (4) is again at the high level (V _CC −V _TN ).
And the logic level is reproduced.

The above is the operation of reading, amplifying, and reproducing information from the memory cell (1). When these series of operations are completed, the system enters a standby state in preparation for the next operation.

First, Then n-FET become time t ₈ the word line drive signal Rn becomes a time t ₉ the descent began (5) is OFF, the memory cells (1) enters a standby state.

Next, the control signal phi _{S, S} descends becomes time t _10, begins to rise, low respectively at time t _11, goes high,
The p-FET (22) and the n-FET (25) are turned off. Next, at time t ₁₂
P-FET (12) is ON started rising control signal phi _E becomes
Then, the bit lines (2) are connected is (7), electric charge is moved to the bit line (7) low potential level from the potential high-level bit line (2), both the bit lines at approximately the time t ₁₃ ( In both 2) and (7), the same potential V _B = V _CC / 2. At the same time, the first and second signal lines (14) and (17) and the bit line (2) which are in a high impedance state by turning off the p-FET (22) and the n-FET (25). , (7), the potential level of both signal lines (14), (17) becomes V _CC / 2 + | V _TP | and V _CC / 2−V _TN respectively.

Then, n start control signal phi _P is increased therefore the time t ₁₄
When the FETs (9) and (10) are turned on, the power supply line (8) and the bit lines (2) and (7) are connected, and the bit lines (2) and (7) are connected.
The potential level of (7) is stabilized to prepare for the next read operation.

[Problems to be Solved by the Invention] As described above, in the read operation, one of the pair of bit lines is discharged from the _Vcc / 2 + ΔV level to the _Vcc level, and the other is the _Vcc / 2 level. To the 0 level. This operation needs to be performed relatively quickly in order to increase the reading speed of the information stored in the memory cell. Normally, the charging / discharging is performed within a short time of about 15 ns. Therefore, a relatively large charge / discharge current flows through the power supply line and the ground line.

Then, let this charge / discharge flow be i. The next (1
Expression).

Here, C; the capacitance value of the bit line ΔV; the change in the voltage of the bit line Δt; the time required for charging and discharging the bit line. As an example, a standard dynamic random access having a storage capacity of 4 Mbits -Considering the memory, the capacity per bit line is 0.5 PF, and 4096 bit lines operate by one operation. Therefore, C = 0.5 PF x 4096 = 2048 PF. / 2V _CC , so V _CC = 5
Assuming V, ΔV = 5/2 = 2.5V Δt is 15ns, Since this relatively large current flows through the power supply line and the ground line, voltage noise is generated in each of these lines due to parasitic resistance, which affects the operation of other circuits commonly connected to these lines. Become. Therefore, in the worst case, there is a problem that these other circuits may malfunction.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and a sense amplifier driving device for a dynamic random access memory which does not generate voltage noise on a power supply line and a ground line during a sensing operation, and a drive thereof. The aim is to get the method.

[Means for Solving the Problems] A sense amplifier driving device for a semiconductor memory according to the present invention comprises a first and a second for transmitting a sense amplifier activation signal.
A coupling capacitor for charging / discharging the signal line to activate the sense amplifier; a first switching element provided between a first potential terminal and the coupling capacitor; and a second potential terminal connected to the second potential terminal. A first switching means having a second switching element provided between the capacitors and first control signal generating means for generating a signal for controlling the operation of the first and second switching elements; A third switching element provided between the first switching element side and the first signal line, and a third switching element provided between the second switching element side of the coupling capacitor and the second signal line. And a second opening / closing means having a second control signal generating means for generating a signal for controlling the operation of the third and fourth switching elements. The method is Turning off the first open / close means, turning on the first open / close means, turning on the first open / close means to precharge the coupling capacitance, and then turning off the first open / close means to bring the coupling capacitance into a floating state; Precharging the pair and the first and second signal lines,
After selecting the memory cell and transmitting the storage signal to the bit line, the second switching means is turned on,
The precharged coupling capacitance is connected between the first and second signal lines.

[Embodiment] FIG. 1 is a diagram showing a dynamic system according to an embodiment of the present invention.
FIG. 9 is a circuit diagram of a sense amplifier driving device for a random access memory, and the same reference numerals as those in FIG.

In the figure, (27) and (28) are nodes, respectively, and the node (27) has an n-FET (22) and a p-FET (30).
The source electrode of the n-FET (25) and the drain electrode of the n-FET (32) are connected to the source electrode and the node (28), respectively. (29) is a coupling capacitance provided between the nodes (27) and (28), (30) is a p-FET that supplies the voltage V _CC applied to the power supply terminal (24) to the node (27), (31) ) Is p
An input terminal of a signal _P for controlling the operation timing of the FET (30), (32) an n-FET for discharging the potential of the node (28) to the ground line GND level, and (33) and (34)
The parasitic capacitance of the nodes (27) and (28), (35) is a p-FET for supplying the power supply voltage V _CC to the first signal line (14), and (36) is p-FET.
An input terminal for a signal for controlling the operation timing of the FET (35), (37) an n-FET for discharging the potential of the second signal line (17) to the level of the ground line GND, and (38) an n-FET. An input terminal of a signal for controlling (37), (60) is a first opening / closing means, and includes a p-FET (22), an n-FET (25), an input terminal (23),
(26) and the control signal phi _S, consisting of a control signal generation system CG of phi _s. (70) is a second opening / closing means, which is a p-FET (30), n
-Consisting of an FET (32), input terminals (11), (24), (31) and a control signal generation system CG for control signals φ _P and φ _P. φ _SD , φ
_SD is a signal for controlling the operation timing of the p-FET (35) and the n-FET (37), respectively.

FIG. 2 is a timing chart for explaining the operation of the circuit configuration shown in FIG. 1. In the case where the storage information "1" of the memory cell (1) is read out as in the conventional example of FIG. The operation of FIG.

Hereinafter, the operation will be described with reference to FIG. The time t ₀ ~
Operation up to t ₄ will be omitted the description are the same as those in the conventional example, to this case, until the time t ₁ at a low impedance node (27) power supply voltage V _CC and the node (2
8) are respectively connected to the ground line GND, the time t ₂ after the node (27) is kept at a potential level of the far becomes (28) with high impedance (floating state). Then, the amplification operation starts at time t _4, the signal φ
_{When S} and _S are input and the p-FET (22) and the n-FET (25) start to turn on, the charge of the parasitic capacitance (21) is reduced by the operation of the sense amplifier (50) to the n-FET (19) and the n-FET (19). 2 signal lines (17),
n-FET (25), coupling capacitance (29), node (27), p-F
After moving to the first signal line (14) via the ET (22),
-Is stored in the parasitic capacitance (20) through the FET (15), the potential of the bit line (2) rises by the amount of the stored charge, and the potential of the bit line (7) is released. It falls in response to the charge. However, in practice, the parasitic capacitance (3
3), (34) causes loss due to this,
Not all charges of the parasitic capacitance (21) move to the parasitic capacitance (20). Therefore, the potentials of the bit lines (2) and (7) do not reach the final level (V _CC , 0 ^V ), and a slight difference (ΔV _H , ΔV _L ) occurs.

For this reason, signal, φ delay signal _SD of _S, the φ _SD time t
_7. Input from input terminals (36) and (38) at p-FET (35)
By turning on the n-FET (37) and compensating for the loss, the potentials of the bit lines (2) and (7) are set to the final level V _CC , 0 ^V. However, at this time, charging / discharging currents corresponding to △ V _H and △ V _L flow to the power supply line or the ground line, but the value is much smaller than that in the conventional device, causing malfunction of other circuits. It is not something to do.

By this time, the potential change of the second signal line (17) at time t ₇ (High → the low △ V _L min only), a node (28), coupling capacitor (29), the node (27), p-FET In order to prevent the potential of the bit line (2) from dropping via (22) and (15), the p-FET (2
Must OFF 2) and n-FET (25), and Therefore, the signal _S at time t _6, increasing the phi _S, or lowered.

In the above embodiment, the FETs (22), (30), (3)
5) shows a p-FET, but the present invention is not limited to this. The polarity of each of the signals φ _S , φ _P , φ _SD input to the gate electrode is reversed, and the high level thereof is set to V _CC + V _TN (n −FET threshold voltage) or more, it may be configured using an n-FET.

Similarly, for the n-FETs (25), (32), and (37), by selecting the polarity and voltage value of the signals φ _S , φ _P , and φ _SD input to the gate electrodes, using the p-FETs Can be configured.

[Effect of the Invention] As described above, according to the present invention, during the sensing operation, the precharged first and second signal lines of the sense amplifier are coupled by the precharged capacitance, and the low level of the bit line pair is obtained. Since the charge accumulated on the level side is transferred to the high level side, the charge / discharge current during the sensing operation hardly flows through the power supply line and the ground line, and therefore, the voltage noise of these lines is reduced. Since the occurrence can be eliminated, there is an effect that a sense amplifier driving device and a driving method thereof for a semiconductor memory which does not cause malfunction of other circuits can be obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a sense amplifier driving apparatus according to an embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation shown in FIG. 1, and FIG. 3 is a dynamic random access memory. FIG. 4 shows a schematic configuration of the entire read section, FIG. 4 shows a schematic configuration of the memory cell array shown in FIG. 3, and FIG. 5 is a circuit diagram showing a conventional sense amplifier driving device. FIG. 6 is a timing chart for explaining the operation of the circuit shown in FIG. In the figure, (1) is a memory cell, (2) and (7) are bit lines, (3) is a word line, (14) is a first signal line,
(17) is a second signal line, (22) and (30) are p-type field effect transistors (p-FET), (25) and (32) are n-type field effect transistors (n-FET), (24) ) Is the power terminal, (2
9) is the coupling capacitance, (50) is the sense amplifier, (60) is the first
(70) is a second opening / closing means, (150) is a precharge / equalize circuit, GND is a ground terminal, and CG is a control signal generation system peripheral circuit. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (2)

(57) [Claims] A memory cell is provided for each of a plurality of bit line pairs connected thereto, and receives an activation signal from a first signal line and a second signal line to differentially amplify a read signal of the memory cell. A drive device for a sense amplifier of a semiconductor memory, comprising: a coupling capacitor for charging and discharging the first and second signal lines to activate the sense amplifier; and a coupling capacitor between a terminal at a first potential and the coupling capacitor. A first switching element provided, a second switching element provided between a terminal of a second potential and the coupling capacitor, and a first which generates a signal for controlling operation of the first and second switching elements.
First switching means having a control signal generating means, a third switching element provided between the first switching element side of the coupling capacitor and the first signal line, and a second switching element provided in the coupling capacitance. Switching element side and the second
And a second control means for generating a signal for controlling the operation of the third and fourth switching elements. A sense amplifier driving device for a semiconductor memory. 2. The semiconductor memory sense amplifier driving device according to claim 1, wherein said second switching means is turned off, said first switching means is turned on, and said coupling capacitance is precharged. (1) turning off the switching means to bring the coupling capacitance into a floating state;
After precharging the bit line pair and the first and second signal lines, selecting the memory cell and transmitting the storage signal to the bit line, turning on the second opening / closing means, Connecting a precharged coupling capacitance between the first and second signal lines.